Target refactoring and cube update (#161)

* Lib: move cube to libs. Firmware: prepare for code base refactoring, detach from cube, port to cmsis_os2. * Firmware, target f2: regenerate project with latest cube package, tim17 for os ticks. * Firmware: unified codebase. * Core: do not include semaphore on old targets. Firmware: dfu uplaod target. * CI: submodules, add firmware build. * CI: proper submodule config. * refactor build system * CI: update chain to use new targets. Documentation: update to match current structure. * CI: clean before rebuild. * Add local test docker-compose exec dev make -C firmware TARGET=local TEST=1 run * Makefile: target specific build directory. CI: updated artifacts path. * Makefile: init git submodules if they don't exists. * Makefile: debug rule now doesn't reset MCU, prevent SIGINT propagation to st-util. * Makefile: proper rebuild sequence in zz and zzz * Makefile: timestamp tracking for flash and upload commands. * Apps: modular build. Input: fix flipper hal inline. * Wiki: proper bootloader link. * Applications: fix broken build for local targets. * add st-flash to docker * fix build * force rebuild app * move app force to firmware part * fix build deps * qrcode build ok * fix example display * add testing routine * update build instruction Co-authored-by: Aleksandr Kutuzov <aku@plooks.com> Co-authored-by: aanper <mail@s3f.ru>
2020-10-07 12:37:43 +03:00 · 2020-10-07 12:37:43 +03:00 · 3c2711102c
commit 3c2711102c
parent 04bf049612
2232 changed files with 5937 additions and 2060599 deletions
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@ -14,6 +14,8 @@ jobs:
    steps:
      - name: Checkout code
        uses: actions/checkout@v2
        with:
            submodules: true
      - uses: satackey/action-docker-layer-caching@v0.0.8
        continue-on-error: true
@ -29,52 +31,37 @@ jobs:
        with:
          run: /syntax_check.sh
-      - name: Build target_lo in docker
+      - name: Build F2 bootloader in docker
        uses: ./.github/actions/docker
        with:
-          run: make -C target_lo
+          run: make -C bootloader TARGET=f2
-      - name: Build target_f1 in docker
+      - name: Publish F2 bootloader artifacts
        uses: ./.github/actions/docker
        with:
          run: make -C target_f1
      - name: Publish target_f1 artifacts
        uses: actions/upload-artifact@v2
        with:
-          name: target_f1
+          name: bootloader_f2
          path: |
-            target_f1/build/target_prod.elf
+            bootloader/.obj/f2/bootloader.elf
-            target_f1/build/target_prod.bin
+            bootloader/.obj/f2/bootloader.bin
-            target_f1/build/target_prod.hex
+            bootloader/.obj/f2/bootloader.hex
          if-no-files-found: error
-      - name: Build target_f2 in docker
+      - name: Build local testing firmware in docker
        uses: ./.github/actions/docker
        with:
-          run: make -C target_f2
+          run: make -C firmware TARGET=local
-      - name: Publish target_f2 artifacts
+      - name: Build F2 firmware in docker
        uses: actions/upload-artifact@v2
        with:
          name: target_f2
          path: |
            target_f2/build/target_prod.elf
            target_f2/build/target_prod.bin
            target_f2/build/target_prod.hex
          if-no-files-found: error
      - name: Build bootloader in docker
        uses: ./.github/actions/docker
        with:
-          run: make -C bootloader
+          run: make -C firmware TARGET=f2
-      - name: Publish bootloader artifacts
+      - name: Publish F2 firmware artifacts
        uses: actions/upload-artifact@v2
        with:
-          name: bootloader
+          name: firmware_f2
          path: |
-            bootloader/.obj/bootloader.elf
+            firmware/.obj/f2/firmware.elf
-            bootloader/.obj/bootloader.bin
+            firmware/.obj/f2/firmware.bin
-            bootloader/.obj/bootloader.hex
+            firmware/.obj/f2/firmware.hex
          if-no-files-found: error
--- a/.gitignore
+++ b/.gitignore
@ -3,6 +3,8 @@
 target_lo/build/
 target_*/build/
 bindings/
 .DS_Store
 .mxproject
 # Visual Studio Code
 .vscode/
--- a/.gitmodules
+++ b/.gitmodules
@ -0,0 +1,3 @@
 [submodule "lib/STM32CubeL4"]
 	path = lib/STM32CubeL4
 	url = https://github.com/STMicroelectronics/STM32CubeL4.git
--- a/README.md
+++ b/README.md
@ -22,10 +22,14 @@ You can read project updates in our developer blog:
 ## Build and run:
-You can run firmware locally (with HAL stub).
+You can run firmware locally (with HAL stub):
-* `docker-compose exec dev make -C target_lo` for build
+* `docker-compose exec dev make -C firmware TARGET=local APP_TEST=1 run` for running tests
-* `docker-compose exec dev target_lo/build/target_lo` for run
+* `docker-compose exec dev make -C firmware TARGET=local APP_*=1 run` for running examples (see `applications/applications.mk` for list of applications/examples)
 Or you can use your dev. board:
 `docker-compose exec dev make -C firmware TARGET=f2 APP_*=1 flash` for build and flash dev board (see `applications/applications.mk` for list of applications/examples)
 ## Architecture and components
--- a/applications/applications.mk
+++ b/applications/applications.mk
@ -0,0 +1,71 @@
 APP_DIR		= $(PROJECT_ROOT)/applications
 LIB_DIR 	= $(PROJECT_ROOT)/lib
 CFLAGS		+= -I$(APP_DIR)
 APP_RELEASE ?= 0
 ifeq ($(APP_RELEASE), 1)
 APP_DISPLAY = 1
 APP_INPUT = 1
 endif
 APP_TEST	?= 0
 ifeq ($(APP_TEST), 1)
 CFLAGS		+= -DAPP_TEST
 C_SOURCES	+= $(APP_DIR)/tests/furiac_test.c
 C_SOURCES	+= $(APP_DIR)/tests/furi_record_test.c
 C_SOURCES	+= $(APP_DIR)/tests/test_index.c
 endif
 APP_EXAMPLE_BLINK ?= 0
 ifeq ($(APP_EXAMPLE_BLINK), 1)
 CFLAGS		+= -DAPP_EXAMPLE_BLINK
 C_SOURCES	+= $(APP_DIR)/examples/blink.c
 endif
 APP_EXAMPLE_UART_WRITE ?= 0
 ifeq ($(APP_EXAMPLE_UART_WRITE), 1)
 CFLAGS		+= -DAPP_EXAMPLE_UART_WRITE
 C_SOURCES	+= $(APP_DIR)/examples/uart_write.c
 endif
 APP_EXAMPLE_IPC ?= 0
 ifeq ($(APP_EXAMPLE_IPC), 1)
 CFLAGS		+= -DAPP_EXAMPLE_IPC
 C_SOURCES	+= $(APP_DIR)/examples/ipc.c
 endif
 APP_EXAMPLE_INPUT_DUMP ?= 0
 ifeq ($(APP_EXAMPLE_INPUT_DUMP), 1)
 CFLAGS		+= -DAPP_EXAMPLE_INPUT_DUMP
 C_SOURCES	+= $(APP_DIR)/examples/input_dump.c
 APP_INPUT = 1
 endif
 APP_EXAMPLE_QRCODE ?= 0
 ifeq ($(APP_EXAMPLE_QRCODE), 1)
 CFLAGS		+= -DAPP_EXAMPLE_QRCODE
 C_SOURCES	+= $(APP_DIR)/examples/u8g2_qrcode.c
 C_SOURCES	+= $(LIB_DIR)/qrcode/qrcode.c
 APP_DISPLAY = 1
 endif
 APP_EXAMPLE_DISPLAY ?= 0
 ifeq ($(APP_EXAMPLE_DISPLAY), 1)
 CFLAGS		+= -DAPP_EXAMPLE_DISPLAY
 C_SOURCES	+= $(APP_DIR)/examples/u8g2_example.c
 APP_DISPLAY = 1
 endif
 # device drivers
 ifeq ($(APP_DISPLAY), 1)
 CFLAGS		+= -DAPP_DISPLAY
 C_SOURCES	+= $(APP_DIR)/display-u8g2/display-u8g2.c
 endif
 APP_INPUT	?= 0
 ifeq ($(APP_INPUT), 1)
 CFLAGS		+= -DAPP_INPUT
 C_SOURCES	+= $(APP_DIR)/input/input.c
 endif
--- a/applications/display-u8g2/display-u8g2.c
+++ b/applications/display-u8g2/display-u8g2.c
@ -3,7 +3,10 @@
 extern SPI_HandleTypeDef hspi1;
-// #define DEBUG 1
+// TODO: fix log
 #ifdef DEBUG
 #undef DEBUG
 #endif
 // TODO rewrite u8g2 to pass thread-local context in this handlers
--- a/applications/startup.h
+++ b/applications/startup.h
@ -8,7 +8,7 @@ typedef struct {
    const char* libs;
 } FlipperStartupApp;
-#ifdef TEST
+#ifdef APP_TEST
 void flipper_test_app(void* p);
 #endif
@ -23,42 +23,50 @@ void display_u8g2(void* p);
 void u8g2_example(void* p);
 void input_task(void* p);
 void menu_task(void* p);
 void coreglitch_demo_0(void* p);
 void u8g2_qrcode(void* p);
 const FlipperStartupApp FLIPPER_STARTUP[] = {
-#ifndef TEST
+#ifdef APP_DISPLAY
    {.app = display_u8g2, .name = "display_u8g2", .libs = ""},
    {.app = u8g2_example, .name = "u8g2_example", .libs = "display_u8g2"},
 #endif
-#ifdef USE_INPUT
+#ifdef APP_INPUT
    {.app = input_task, .name = "input_task", .libs = ""},
 #endif
 // {.app = coreglitch_demo_0, .name = "coreglitch_demo_0", .libs = ""},
-#ifdef TEST
+#ifdef APP_TEST
    {.app = flipper_test_app, .name = "test app", .libs = ""},
 #endif
-#ifdef EXAMPLE_BLINK
+#ifdef APP_EXAMPLE_BLINK
    {.app = application_blink, .name = "blink", .libs = ""},
 #endif
-#ifdef EXAMPLE_UART_WRITE
+
 #ifdef APP_EXAMPLE_UART_WRITE
    {.app = application_uart_write, .name = "uart write", .libs = ""},
 #endif
-#ifdef EXAMPLE_IPC
+
 #ifdef APP_EXAMPLE_IPC
    {.app = application_ipc_display, .name = "ipc display", .libs = ""},
    {.app = application_ipc_widget, .name = "ipc widget", .libs = ""},
 #endif
-#ifdef EXAMPLE_INPUT_DUMP
+
 #ifdef APP_EXAMPLE_INPUT_DUMP
    {.app = application_input_dump, .name = "input dump", .libs = "input_task"},
 #endif
-#ifdef EXAMPLE_QRCODE
+#ifdef APP_EXAMPLE_QRCODE
    {.app = u8g2_qrcode, .name = "u8g2_qrcode", .libs = "display_u8g2"},
 #endif
 #ifdef APP_EXAMPLE_DISPLAY
    {.app = u8g2_example, .name = "u8g2_example", .libs = "display_u8g2"},
 #endif
 };
--- a/applications/tests/test_index.c
+++ b/applications/tests/test_index.c
@ -2,7 +2,7 @@
 #include "flipper.h"
 #include "log.h"
-#include "flipper-core.h"
+// #include "flipper-core.h" TODO: Rust build disabled
 bool test_furi_ac_create_kill(FuriRecordSubscriber* log);
 bool test_furi_ac_switch_exit(FuriRecordSubscriber* log);
@ -58,6 +58,8 @@ void flipper_test_app(void* p) {
        fuprintf(log, "[TEST] test_furi_mute_algorithm FAILED\n");
    }
    /*
    TODO: Rust build disabled
    if(add(1, 2) == 3) {
        fuprintf(log, "[TEST] Rust add PASSED\n");
    } else {
@ -65,6 +67,7 @@ void flipper_test_app(void* p) {
    }
    rust_uart_write();
    */
    furiac_exit(NULL);
 }
--- a/bootloader/Makefile
+++ b/bootloader/Makefile
@ -1,97 +1,16 @@
 PROJECT_ROOT	= $(abspath $(dir $(abspath $(firstword $(MAKEFILE_LIST))))..)
 PROJECT			= bootloader
-SRC_DIR			= src
+include 		$(PROJECT_ROOT)/make/base.mk
 OBJ_DIR			= .obj
-ASM_SOURCES		= $(wildcard $(SRC_DIR)/*.s)
+CFLAGS			+= -Itargets/include
-C_SOURCES		= $(wildcard $(SRC_DIR)/*.c)
+ASM_SOURCES		+= $(wildcard src/*.s)
-CPP_SOURCES		= $(wildcard $(SRC_DIR)/*.cpp)
+C_SOURCES		+= $(wildcard src/*.c)
 CPP_SOURCES		+= $(wildcard src/*.cpp)
 # 
 TARGET			?= f2
 TARGET_DIR		= targets/$(TARGET)
 include			$(TARGET_DIR)/target.mk
 CFLAGS			+= -Itargets/include
 C_SOURCES		+= $(wildcard $(TARGET_DIR)/*.c)
-DEBUG ?= 1
+include			$(PROJECT_ROOT)/make/toolchain.mk
-ifeq ($(DEBUG), 1)
+include			$(PROJECT_ROOT)/make/rules.mk
 CFLAGS += -DDEBUG -g
 else
 CFLAGS += -DNDEBUG -Os
 endif
 PREFIX = arm-none-eabi-
 ifdef GCC_PATH
 CC	= $(GCC_PATH)/$(PREFIX)gcc
 CPP	= $(GCC_PATH)/$(PREFIX)g++
 AS	= $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp
 CP	= $(GCC_PATH)/$(PREFIX)objcopy
 SZ	= $(GCC_PATH)/$(PREFIX)size
 else
 CC	= $(PREFIX)gcc
 CPP	= $(PREFIX)g++
 AS	= $(PREFIX)gcc -x assembler-with-cpp
 CP	= $(PREFIX)objcopy
 SZ	= $(PREFIX)size
 endif
 HEX	= $(CP) -O ihex
 BIN	= $(CP) -O binary -S
 $(shell mkdir -p $(OBJ_DIR))
 OBJECTS = $(addprefix $(OBJ_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
 vpath %.c $(sort $(dir $(C_SOURCES)))
 OBJECTS += $(addprefix $(OBJ_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
 vpath %.s $(sort $(dir $(ASM_SOURCES)))
 OBJECTS += $(addprefix $(OBJ_DIR)/,$(notdir $(CPP_SOURCES:.cpp=.o)))
 vpath %.cpp $(sort $(dir $(CPP_SOURCES)))
 DEPS = $(OBJECTS:.o=.d)
 CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
 CPPFLAGS = -fno-threadsafe-statics
 all: $(OBJ_DIR)/$(PROJECT).elf $(OBJ_DIR)/$(PROJECT).hex $(OBJ_DIR)/$(PROJECT).bin
 $(OBJ_DIR)/$(PROJECT).elf: $(OBJECTS)
 	@echo "\tLD\t" $@
 	@$(CC) $(LDFLAGS) $(OBJECTS) -o $@
 	$(SZ) $@
 $(OBJ_DIR)/$(PROJECT).hex: $(OBJ_DIR)/$(PROJECT).elf
 	@echo "\tHEX\t" $@
 	@$(HEX) $< $@
 $(OBJ_DIR)/$(PROJECT).bin: $(OBJ_DIR)/$(PROJECT).elf
 	@echo "\tBIN\t" $@
 	@$(BIN) $< $@
 $(OBJ_DIR)/%.o: %.c
 	@echo "\tCC\t" $@
 	@$(CC) $(CFLAGS) -c $< -o $@
 $(OBJ_DIR)/%.o: %.s
 	@echo "\tASM\t" $@
 	@$(AS) $(CFLAGS) -c $< -o $@
 $(OBJ_DIR)/%.o: %.cpp
 	@echo "\tCPP\t" $@
 	@$(CPP) $(CFLAGS) $(CPPFLAGS) -c $< -o $@
 flash: $(OBJ_DIR)/$(PROJECT).bin
 	st-flash --reset write $(OBJ_DIR)/$(PROJECT).bin $(BOOT_ADDRESS)
 debug:
 	st-util & arm-none-eabi-gdb -ex "PROJECT extended-remote 127.0.0.1:4242" $(OBJ_DIR)/$(PROJECT).elf
 clean:
 	$(RM) $(OBJ_DIR)/*
 zz: | clean flash
 zzz: | clean flash debug
 -include $(DEPS)
--- a/bootloader/targets/f2/target.c
+++ b/bootloader/targets/f2/target.c
@ -149,6 +149,6 @@ void target_switch2dfu() {
 void target_switch2os() {
    LL_GPIO_ResetOutputPin(LED_RED_PORT, LED_RED_PIN);
-    SCB->VTOR = OS_OFFSET;
+    SCB->VTOR = BOOT_ADDRESS + OS_OFFSET;
    target_switch((void*)(BOOT_ADDRESS + OS_OFFSET));
 }
--- a/bootloader/targets/f2/target.mk
+++ b/bootloader/targets/f2/target.mk
@ -1,13 +1,17 @@
-BOOT_ADDRESS	= 0x08000000
+TOOLCHAIN = arm
 OS_OFFSET		= 0x00008000
-BOOT_CFLAGS		= -DBOOT_ADDRESS=$(BOOT_ADDRESS) -DOS_OFFSET=$(OS_OFFSET)
+BOOT_ADDRESS	= 0x08000000
 FW_ADDRESS		= 0x08008000
 OS_OFFSET		= 0x00008000
 FLASH_ADDRESS	= 0x08000000
 BOOT_CFLAGS		= -DBOOT_ADDRESS=$(BOOT_ADDRESS) -DFW_ADDRESS=$(FW_ADDRESS) -DOS_OFFSET=$(OS_OFFSET)
 MCU_FLAGS		= -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard
-CFLAGS			+= $(MCU_FLAGS) $(BOOT_CFLAGS) -DSTM32L4R7xx -Wall -fdata-sections -ffunction-sections
+CFLAGS			+= $(MCU_FLAGS) $(BOOT_CFLAGS) -DSTM32L476xx -Wall -fdata-sections -ffunction-sections
 LDFLAGS			+= $(MCU_FLAGS) -specs=nosys.specs -specs=nano.specs
-CUBE_DIR		= ../target_f2
+CUBE_DIR		= ../lib/STM32CubeL4
 CUBE_CMSIS_DIR	= $(CUBE_DIR)/Drivers/CMSIS
 CUBE_HAL_DIR	= $(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver
@ -19,3 +23,7 @@ CFLAGS			+= -I$(CUBE_CMSIS_DIR)/Include
 CFLAGS			+= -I$(CUBE_CMSIS_DIR)/Device/ST/STM32L4xx/Include
 CFLAGS			+= -I$(CUBE_HAL_DIR)/Inc
 LDFLAGS			+= -Ttargets/f2/STM32L476RGTx_FLASH.ld
 ASM_SOURCES		+= $(wildcard $(TARGET_DIR)/*.s)
 C_SOURCES		+= $(wildcard $(TARGET_DIR)/*.c)
 CPP_SOURCES		+= $(wildcard $(TARGET_DIR)/*.cpp)
--- a/core-rs/core-rs.mk
+++ b/core-rs/core-rs.mk
@ -0,0 +1,42 @@
 #######################################
 # Rust library
 #######################################
 #######################################
 # Rust library
 #######################################
 RUST_LIB_SRC = $(realpath $(PROJECT_DIR)/../core-rs)
 RUST_LIB_NAME = flipper_core
 ifeq ($(ARCH), 'x86_64')
 RUST_LIB_TARGET = x86_64-unknown-linux-gnu
 else
 RUST_LIB_TARGET = thumbv7em-none-eabihf
 endif
 RUST_LIB_FLAGS = --target=$(RUST_LIB_TARGET)
 ifeq ($(DEBUG), 1)
    RUST_LIB_PATH = $(RUST_LIB_SRC)/target/$(RUST_LIB_TARGET)/debug
 else
    RUST_LIB_FLAGS += --release
    RUST_LIB_PATH = $(RUST_LIB_SRC)/target/$(RUST_LIB_TARGET)/release
 endif
 RUST_LIB_CMD = cd $(RUST_LIB_SRC) && cargo build -p flipper-core $(RUST_LIB_FLAGS)
 LD_FLAGS += -l$(RUST_LIB_NAME)
 LD_FLAGS += -L$(RUST_LIB_PATH)
 $(RUST_LIB_PATH)/lib$(RUST_LIB_NAME).a: rust_lib
 rust_lib:
 	$(RUST_LIB_CMD)
 clean:
 	-rm -fR $(BUILD_DIR)
 	cd $(RUST_LIB_SRC) && cargo clean
--- a/core/core.mk
+++ b/core/core.mk
@ -0,0 +1,6 @@
 CORE_DIR		= $(PROJECT_ROOT)/core
 CFLAGS			+= -I$(CORE_DIR)
 ASM_SOURCES		+= $(wildcard $(CORE_DIR)/*.s)
 C_SOURCES		+= $(wildcard $(CORE_DIR)/*.c)
 CPP_SOURCES		+= $(wildcard $(CORE_DIR)/*.cpp)
--- a/core/furi.h
+++ b/core/furi.h
@ -1,6 +1,9 @@
 #pragma once
 #include "cmsis_os.h"
 #ifdef HAVE_FREERTOS
 #include <semphr.h>
 #endif
 #include <stdbool.h>
 #include <stdint.h>
--- a/docker/Dockerfile
+++ b/docker/Dockerfile
@ -26,6 +26,17 @@ RUN apt update && \
 RUN curl https://sh.rustup.rs -sSf | sh -s -- -y --profile=minimal --target thumbv7em-none-eabi thumbv7em-none-eabihf && \
    rustup component add rustfmt --toolchain stable-x86_64-unknown-linux-gnu
 # st-flash
 RUN apt update && \
    apt install -y --no-install-recommends \
    gcc build-essential cmake libusb-1.0 libusb-1.0-0-dev libgtk-3-dev pandoc \
    && apt-get clean && rm -rf /var/lib/apt/lists/* /tmp/* /var/tmp/*
 RUN wget https://github.com/stlink-org/stlink/archive/v1.5.1.zip
 RUN unzip v1.5.1.zip
 RUN cd stlink-1.5.1 && make clean && make release
 RUN cd stlink-1.5.1/build/Release && make install && ldconfig
 COPY entrypoint.sh syntax_check.sh /
 RUN chmod +x /syntax_check.sh
--- a/firmware/Makefile
+++ b/firmware/Makefile
@ -0,0 +1,17 @@
 PROJECT_ROOT	= $(abspath $(dir $(abspath $(firstword $(MAKEFILE_LIST))))..)
 PROJECT			= firmware
 include 		$(PROJECT_ROOT)/make/base.mk
 include			$(PROJECT_ROOT)/core/core.mk
 include			$(PROJECT_ROOT)/lib/lib.mk
 include 		$(PROJECT_ROOT)/applications/applications.mk
 TARGET			?= f2
 TARGET_DIR		= targets/$(TARGET)
 include			$(TARGET_DIR)/target.mk
 include			$(PROJECT_ROOT)/make/toolchain.mk
 include			$(PROJECT_ROOT)/make/rules.mk
 $(OBJ_DIR)/app.o:   .FORCE
 .PHONY: .FORCE
--- a/firmware/ReadMe.md
+++ b/firmware/ReadMe.md
@ -0,0 +1,104 @@
 _Overview of Flipper firmware architecture:_
 ![FW arch](https://github.com/Flipper-Zero/flipperzero-firmware-community/raw/master/wiki_static/flipper_fw_arch.png)
 # Project structure
 ```
 .
 ├── applications    # Flipper applications
 ├── bootloader      # Bootloader make project
 ├── core            # Main feature like OS, HAL (target-independed)
 ├── core-rs         # Rust code
 ├── docker          # Docker toolchain container
 ├── firmware        # Firmware make project
 ├── lib             # Libs and 3rd parties
 ├── make            # Makefile scripts
 ├── wiki            # Documentation (wiki) generates from this files
 └── wiki_static     # Static files for wiki
 ```
 # HAL
 We use STM32 HAL/LL. Description available here: [dm00105879.pdf](https://github.com/Flipper-Zero/flipperzero-firmware-community/raw/master/wiki_static/dm00105879-description-of-stm32f4-hal-and-ll-drivers-stmicroelectronics.pdf)
 ## Flipper HAL
 Some flipper-specific implementation of gpio/HAL:
 * Init gpio pin: `app_gpio_init`
 * Fast write gpio (inline): `app_gpio_write`
 * Fast read gpio (inline): `app_gpio_read`
 * Microsecond delay `delay_us`
 * Set PWM on timer's pin: `pwm_set`
 Files location: `/app/app_hal.[ch]`
 # Bootloader
 For production targets('f2' and newer) bootloader must be flashed first.
 Detailed instruction on how to compile and flash it you can find in `bootloader` folder.
 Production version is going to have following features:
 - Hardware initialization
 - Firmware CRC check
 - Firmware update
 - Interactive UI
 - Boot process LED indicators
 - FS check
 - Recovery mode
 # OS
 CMSIS-RTOS2 over FreeRTOS
 **[Timers map](Timers)**
 # Platform code
 CMSIS, Freertos and HAL files are generated by CubeMX.
 You can find platform code for L476 version in `f2` folder:
 * `Inc` `Src` — CubeMX generated headers & code
 * `Middlewares/Third_Party/FreeRTOS/Source` — freeRTOS
 * `deploy.sh` — flash firmware to device
 * `STM32L476RGTx_FLASH.ld` — linker script
 * `startup_stm32l476xx.s` — board startup/initialization assembler code
 * `cube.ioc` — CubeMX project file
 You can regenerate platform code:
 1. Download CubeMX from [st.com](https://www.st.com/en/development-tools/stm32cubemx.html)
 2. Open `*.ioc` file
 3. Click `generate code`
 4. After regenerating, look at git status, regenerating may broke some files.
 # Flipper Universal Registry Implementation (FURI)
 FURI is used to:
 * application control (start, exit, switch between active)
 * data exchange between application (create/open channel, subscribe and push messages or read/write values)
 * non-volatile data storage for application (create/open value and read/write)
 Read more at [FURI page](FURI)
 # FS (not implemented)
 File system is used to volaile storage some files (config, application data, etc.). There are some folders mounted to different volumes:
 * `/usr` for store static data like assets, menu items. Build system add files to usr while building. It can be useful for exchange some static data between application. For example, your app can add link to itself to Plugins menu items file, user will see your app and can call it from this menu.
 * Specially `/usr/etc-default` folder contains default configs for apps. Bootloader has `factory default` options to reset applications config. Also when new app is bootstapping, system copy files from default config folder to `/etc`.
 * `/etc` for store configs of application. This volume not overwrite during flashing.
 * `/var` for store some application data (saved keys, application database, logs). This volume also not overwrite during flashing.
 * `/media/*` mounted if SD card is inserted.
 # Flipper applications
 Each flipper functionality except OS/HAL/FURI doing by Flipper application. Some application are called at startup, the rest are called by the user (for example, from menu).
 (you can see some [examples](Application-examples))
 For exchange data between application each app expose own record in FURI. You can subscribe on/read record to get data from application and write to record to send data to application.
 **[List of FURI records](FURI-records-list)**
--- a/firmware/targets/f2/Inc/FreeRTOSConfig.h
+++ b/firmware/targets/f2/Inc/FreeRTOSConfig.h
@ -1,7 +1,8 @@
 /* USER CODE BEGIN Header */
 /*
- * FreeRTOS Kernel V10.0.1
+ * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 * Portion Copyright (C) 2019 StMicroelectronics, Inc.  All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of
 * this software and associated documentation files (the "Software"), to deal in
@ -48,10 +49,12 @@
 /* Ensure definitions are only used by the compiler, and not by the assembler. */
 #if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
-#include <stdint.h>
+  #include <stdint.h>
-extern uint32_t SystemCoreClock;
+  extern uint32_t SystemCoreClock;
 void xPortSysTickHandler(void);
 #endif
 #define configENABLE_FPU                         0
 #define configENABLE_MPU                         0
 #define configUSE_PREEMPTION                     1
 #define configSUPPORT_STATIC_ALLOCATION          1
 #define configSUPPORT_DYNAMIC_ALLOCATION         1
@ -59,24 +62,31 @@ void xPortSysTickHandler(void);
 #define configUSE_TICK_HOOK                      0
 #define configCPU_CLOCK_HZ                       ( SystemCoreClock )
 #define configTICK_RATE_HZ                       ((TickType_t)1000)
-#define configMAX_PRIORITIES                     ( 7 )
+#define configMAX_PRIORITIES                     ( 56 )
 #define configMINIMAL_STACK_SIZE                 ((uint16_t)128)
 #define configTOTAL_HEAP_SIZE                    ((size_t)8192)
 #define configMAX_TASK_NAME_LEN                  ( 16 )
 #define configUSE_TRACE_FACILITY                 1
 #define configUSE_16_BIT_TICKS                   0
 #define configUSE_MUTEXES                        1
 #define configQUEUE_REGISTRY_SIZE                8
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION  1
+#define configUSE_RECURSIVE_MUTEXES              1
 #define configUSE_COUNTING_SEMAPHORES            1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION  0
 /* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
 /* Defaults to size_t for backward compatibility, but can be changed
   if lengths will always be less than the number of bytes in a size_t. */
 #define configMESSAGE_BUFFER_LENGTH_TYPE         size_t
 #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 1
 /* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */
 /* Co-routine definitions. */
 #define configUSE_CO_ROUTINES                    0
-#define configMAX_CO_ROUTINE_PRIORITIES (2)
+#define configMAX_CO_ROUTINE_PRIORITIES          ( 2 )
 /* Software timer definitions. */
 #define configUSE_TIMERS                         1
-#define configTIMER_TASK_PRIORITY (2)
+#define configTIMER_TASK_PRIORITY                ( 2 )
 #define configTIMER_QUEUE_LENGTH                 10
 #define configTIMER_TASK_STACK_DEPTH             256
@ -87,16 +97,26 @@ to exclude the API function. */
 #define INCLUDE_vTaskDelete                  1
 #define INCLUDE_vTaskCleanUpResources        0
 #define INCLUDE_vTaskSuspend                 1
-#define INCLUDE_vTaskDelayUntil 0
+#define INCLUDE_vTaskDelayUntil              1
 #define INCLUDE_vTaskDelay                   1
 #define INCLUDE_xTaskGetSchedulerState       1
 #define INCLUDE_xTimerPendFunctionCall       1
 #define INCLUDE_xQueueGetMutexHolder         1
 #define INCLUDE_uxTaskGetStackHighWaterMark  1
 #define INCLUDE_eTaskGetState                1
 /*
 * The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used
 * by the application thus the correct define need to be enabled below
 */
 #define USE_FreeRTOS_HEAP_4
 /* Cortex-M specific definitions. */
 #ifdef __NVIC_PRIO_BITS
-/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
-#define configPRIO_BITS __NVIC_PRIO_BITS
+ #define configPRIO_BITS         __NVIC_PRIO_BITS
 #else
-#define configPRIO_BITS 4
+ #define configPRIO_BITS         4
 #endif
 /* The lowest interrupt priority that can be used in a call to a "set priority"
@ -111,22 +131,15 @@ PRIORITY THAN THIS! (higher priorities are lower numeric values. */
 /* Interrupt priorities used by the kernel port layer itself.  These are generic
 to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY \
+#define configKERNEL_INTERRUPT_PRIORITY 		( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
    (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
 /* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY \
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
    (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
 /* Normal assert() semantics without relying on the provision of an assert.h
 header file. */
 /* USER CODE BEGIN 1 */
-#define configASSERT(x)           \
+#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}
    if((x) == 0) {                \
        taskDISABLE_INTERRUPTS(); \
        for(;;)                   \
            ;                     \
    }
 /* USER CODE END 1 */
 /* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
@ -137,7 +150,7 @@ standard names. */
 /* IMPORTANT: This define is commented when used with STM32Cube firmware, when the timebase source is SysTick,
              to prevent overwriting SysTick_Handler defined within STM32Cube HAL */
-/* #define xPortSysTickHandler SysTick_Handler */
+#define xPortSysTickHandler SysTick_Handler
 /* USER CODE BEGIN Defines */
 /* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
--- a/target_f2/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc_if_template.h
+++ b/target_f2/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc_if_template.h
@ -1,45 +1,58 @@
 /**
  ******************************************************************************
-  * @file    usbd_cdc_if_template.h
+  * File Name          : ADC.h
-  * @author  MCD Application Team
+  * Description        : This file provides code for the configuration
-  * @brief   Header for usbd_cdc_if_template.c file.
+  *                      of the ADC instances.
  ******************************************************************************
  * @attention
  *
-  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
-  *                      http://www.st.com/SLA0044
+  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CDC_IF_TEMPLATE_H
+#ifndef __adc_H
-#define __USBD_CDC_IF_TEMPLATE_H
+#define __adc_H
 #ifdef __cplusplus
 extern "C" {
 #endif
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_cdc.h"
+#include "main.h"
-/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
 /* Exported constants --------------------------------------------------------*/
-extern USBD_CDC_ItfTypeDef  USBD_CDC_Template_fops;
+/* USER CODE END Includes */
-/* Exported macro ------------------------------------------------------------*/
+extern ADC_HandleTypeDef hadc1;
-/* Exported functions ------------------------------------------------------- */
+
 /* USER CODE BEGIN Private defines */
 /* USER CODE END Private defines */
 void MX_ADC1_Init(void);
 /* USER CODE BEGIN Prototypes */
 /* USER CODE END Prototypes */
 #ifdef __cplusplus
 }
 #endif
 #endif /*__ adc_H */
-#endif /* __USBD_CDC_IF_TEMPLATE_H */
+/**
  * @}
  */
 /**
  * @}
  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/target_f1/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc_if_template.h
+++ b/target_f1/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc_if_template.h
@ -1,45 +1,58 @@
 /**
  ******************************************************************************
-  * @file    usbd_cdc_if_template.h
+  * File Name          : COMP.h
-  * @author  MCD Application Team
+  * Description        : This file provides code for the configuration
-  * @brief   Header for usbd_cdc_if_template.c file.
+  *                      of the COMP instances.
  ******************************************************************************
  * @attention
  *
-  * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
-  *                      http://www.st.com/SLA0044
+  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CDC_IF_TEMPLATE_H
+#ifndef __comp_H
-#define __USBD_CDC_IF_TEMPLATE_H
+#define __comp_H
 #ifdef __cplusplus
 extern "C" {
 #endif
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_cdc.h"
+#include "main.h"
-/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
 /* Exported constants --------------------------------------------------------*/
-extern USBD_CDC_ItfTypeDef  USBD_CDC_Template_fops;
+/* USER CODE END Includes */
-/* Exported macro ------------------------------------------------------------*/
+extern COMP_HandleTypeDef hcomp1;
-/* Exported functions ------------------------------------------------------- */
+
 /* USER CODE BEGIN Private defines */
 /* USER CODE END Private defines */
 void MX_COMP1_Init(void);
 /* USER CODE BEGIN Prototypes */
 /* USER CODE END Prototypes */
 #ifdef __cplusplus
 }
 #endif
 #endif /*__ comp_H */
-#endif /* __USBD_CDC_IF_TEMPLATE_H */
+/**
  * @}
  */
 /**
  * @}
  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Inc/flipper_hal.h
+++ b/firmware/targets/f2/Inc/flipper_hal.h
--- a/firmware/targets/f2/Inc/gpio.h
+++ b/firmware/targets/f2/Inc/gpio.h
@ -0,0 +1,57 @@
 /**
  ******************************************************************************
  * File Name          : gpio.h
  * Description        : This file contains all the functions prototypes for
  *                      the gpio
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __gpio_H
 #define __gpio_H
 #ifdef __cplusplus
 extern "C" {
 #endif
 /* Includes ------------------------------------------------------------------*/
 #include "main.h"
 /* USER CODE BEGIN Includes */
 /* USER CODE END Includes */
 /* USER CODE BEGIN Private defines */
 /* USER CODE END Private defines */
 void MX_GPIO_Init(void);
 /* USER CODE BEGIN Prototypes */
 /* USER CODE END Prototypes */
 #ifdef __cplusplus
 }
 #endif
 #endif /*__ pinoutConfig_H */
 /**
  * @}
  */
 /**
  * @}
  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Inc/input_priv.h
+++ b/firmware/targets/f2/Inc/input_priv.h
--- a/firmware/targets/f2/Inc/main.h
+++ b/firmware/targets/f2/Inc/main.h
@ -38,8 +38,6 @@ extern "C" {
 /* Exported types ------------------------------------------------------------*/
 /* USER CODE BEGIN ET */
 typedef enum { TimerEventInputCapture, TimerEventEndOfPulse } TimerEvent;
 /* USER CODE END ET */
 /* Exported constants --------------------------------------------------------*/
@ -52,21 +50,16 @@ typedef enum { TimerEventInputCapture, TimerEventEndOfPulse } TimerEvent;
 /* USER CODE END EM */
 void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim);
 /* Exported functions prototypes ---------------------------------------------*/
 void Error_Handler(void);
 /* USER CODE BEGIN EFP */
 void register_tim8_callback_ch2(void (*callback)(uint16_t ccr, TimerEvent tim_event));
 /* USER CODE END EFP */
 /* Private defines -----------------------------------------------------------*/
 #define BUTTON_BACK_Pin GPIO_PIN_13
 #define BUTTON_BACK_GPIO_Port GPIOC
 #define BUTTON_BACK_EXTI_IRQn EXTI15_10_IRQn
 #define CHRG_Pin GPIO_PIN_2
 #define CHRG_GPIO_Port GPIOC
 #define CHRG_EXTI_IRQn EXTI2_IRQn
@ -131,31 +124,6 @@ void register_tim8_callback_ch2(void (*callback)(uint16_t ccr, TimerEvent tim_ev
 #define BUTTON_OK_EXTI_IRQn EXTI9_5_IRQn
 /* USER CODE BEGIN Private defines */
 #define LD2_Pin LED_RED_Pin
 #define LD2_GPIO_Port LED_RED_GPIO_Port
 #define EM_PIN_GPIO_Port RFID_OUT_GPIO_Port
 #define EM_PIN_Pin RFID_OUT_Pin
 #define MISO_PIN                          \
    GpioPin {                             \
        .port = GPIOC, .pin = GPIO_PIN_11 \
    }
 // #define MOSI_PIN 11
 #define SS_PIN                                            \
    GpioPin {                                             \
        .port = CC1101_CS_GPIO_Port, .pin = CC1101_CS_Pin \
    }
 //2 main, 5 remote, 3 M16
 #define GDO2                   \
    GpioPin {                  \
        .port = NULL, .pin = 0 \
    }
 #define GDO0                                              \
    GpioPin {                                             \
        .port = CC1101_G0_GPIO_Port, .pin = CC1101_G0_Pin \
    }
 /* USER CODE END Private defines */
 #ifdef __cplusplus
--- a/firmware/targets/f2/Inc/spi.h
+++ b/firmware/targets/f2/Inc/spi.h
@ -0,0 +1,60 @@
 /**
  ******************************************************************************
  * File Name          : SPI.h
  * Description        : This file provides code for the configuration
  *                      of the SPI instances.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __spi_H
 #define __spi_H
 #ifdef __cplusplus
 extern "C" {
 #endif
 /* Includes ------------------------------------------------------------------*/
 #include "main.h"
 /* USER CODE BEGIN Includes */
 /* USER CODE END Includes */
 extern SPI_HandleTypeDef hspi1;
 extern SPI_HandleTypeDef hspi3;
 /* USER CODE BEGIN Private defines */
 /* USER CODE END Private defines */
 void MX_SPI1_Init(void);
 void MX_SPI3_Init(void);
 /* USER CODE BEGIN Prototypes */
 /* USER CODE END Prototypes */
 #ifdef __cplusplus
 }
 #endif
 #endif /*__ spi_H */
 /**
  * @}
  */
 /**
  * @}
  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/target_f1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h
+++ b/target_f1/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h
@ -36,55 +36,60 @@
  */
 #define HAL_MODULE_ENABLED
 #define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
+/*#define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
+/*#define HAL_CAN_MODULE_ENABLED   */
 #define HAL_COMP_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
+/*#define HAL_CRC_MODULE_ENABLED   */
-#define HAL_CRC_MODULE_ENABLED
+/*#define HAL_CRYP_MODULE_ENABLED   */
-#define HAL_CRYP_MODULE_ENABLED
+/*#define HAL_DAC_MODULE_ENABLED   */
-#define HAL_DAC_MODULE_ENABLED
+/*#define HAL_DCMI_MODULE_ENABLED   */
-#define HAL_DCMI_MODULE_ENABLED
+/*#define HAL_DMA2D_MODULE_ENABLED   */
-#define HAL_DFSDM_MODULE_ENABLED
+/*#define HAL_DFSDM_MODULE_ENABLED   */
-#define HAL_DMA_MODULE_ENABLED
+/*#define HAL_DSI_MODULE_ENABLED   */
-#define HAL_DMA2D_MODULE_ENABLED
+/*#define HAL_FIREWALL_MODULE_ENABLED   */
-#define HAL_DSI_MODULE_ENABLED
+/*#define HAL_GFXMMU_MODULE_ENABLED   */
-#define HAL_EXTI_MODULE_ENABLED
+/*#define HAL_HCD_MODULE_ENABLED   */
-#define HAL_FIREWALL_MODULE_ENABLED
+/*#define HAL_HASH_MODULE_ENABLED   */
-#define HAL_FLASH_MODULE_ENABLED
+/*#define HAL_I2S_MODULE_ENABLED   */
-#define HAL_GFXMMU_MODULE_ENABLED
+/*#define HAL_IRDA_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
+/*#define HAL_IWDG_MODULE_ENABLED   */
-#define HAL_HASH_MODULE_ENABLED
+/*#define HAL_LTDC_MODULE_ENABLED   */
-#define HAL_HCD_MODULE_ENABLED
+/*#define HAL_LCD_MODULE_ENABLED   */
-#define HAL_I2C_MODULE_ENABLED
+/*#define HAL_LPTIM_MODULE_ENABLED   */
-#define HAL_IRDA_MODULE_ENABLED
+/*#define HAL_MMC_MODULE_ENABLED   */
-#define HAL_IWDG_MODULE_ENABLED
+/*#define HAL_NAND_MODULE_ENABLED   */
-#define HAL_LCD_MODULE_ENABLED
+/*#define HAL_NOR_MODULE_ENABLED   */
-#define HAL_LPTIM_MODULE_ENABLED
+/*#define HAL_OPAMP_MODULE_ENABLED   */
-#define HAL_LTDC_MODULE_ENABLED
+/*#define HAL_OSPI_MODULE_ENABLED   */
-#define HAL_MMC_MODULE_ENABLED
+/*#define HAL_OSPI_MODULE_ENABLED   */
 #define HAL_NAND_MODULE_ENABLED
 #define HAL_NOR_MODULE_ENABLED
 #define HAL_OPAMP_MODULE_ENABLED
 #define HAL_OSPI_MODULE_ENABLED
 #define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
+/*#define HAL_PKA_MODULE_ENABLED   */
-#define HAL_QSPI_MODULE_ENABLED
+/*#define HAL_QSPI_MODULE_ENABLED   */
-#define HAL_RCC_MODULE_ENABLED
+/*#define HAL_QSPI_MODULE_ENABLED   */
-#define HAL_RNG_MODULE_ENABLED
+/*#define HAL_RNG_MODULE_ENABLED   */
-#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_RTC_MODULE_ENABLED   */
-#define HAL_SAI_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
-#define HAL_SD_MODULE_ENABLED
+/*#define HAL_SD_MODULE_ENABLED   */
-#define HAL_SMARTCARD_MODULE_ENABLED
+/*#define HAL_SMBUS_MODULE_ENABLED   */
-#define HAL_SMBUS_MODULE_ENABLED
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
 #define HAL_SPI_MODULE_ENABLED
-#define HAL_SRAM_MODULE_ENABLED
+/*#define HAL_SRAM_MODULE_ENABLED   */
-#define HAL_SWPMI_MODULE_ENABLED
+/*#define HAL_SWPMI_MODULE_ENABLED   */
 #define HAL_TIM_MODULE_ENABLED
-#define HAL_TSC_MODULE_ENABLED
+/*#define HAL_TSC_MODULE_ENABLED   */
 #define HAL_UART_MODULE_ENABLED
-#define HAL_USART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
-#define HAL_WWDG_MODULE_ENABLED
+/*#define HAL_WWDG_MODULE_ENABLED   */
-
+/*#define HAL_EXTI_MODULE_ENABLED   */
 /*#define HAL_PSSI_MODULE_ENABLED   */
 #define HAL_GPIO_MODULE_ENABLED
 #define HAL_EXTI_MODULE_ENABLED
 #define HAL_I2C_MODULE_ENABLED
 #define HAL_DMA_MODULE_ENABLED
 #define HAL_RCC_MODULE_ENABLED
 #define HAL_FLASH_MODULE_ENABLED
 #define HAL_PWR_MODULE_ENABLED
 #define HAL_CORTEX_MODULE_ENABLED
 /* ########################## Oscillator Values adaptation ####################*/
 /**
@ -93,11 +98,11 @@
  *        (when HSE is used as system clock source, directly or through the PLL).
  */
 #if !defined  (HSE_VALUE)
-  #define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */
+  #define HSE_VALUE    ((uint32_t)16000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 #if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 /**
@ -105,16 +110,15 @@
  *        This value is the default MSI range value after Reset.
  */
 #if !defined  (MSI_VALUE)
-  #define MSI_VALUE    4000000U /*!< Value of the Internal oscillator in Hz*/
+  #define MSI_VALUE    ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/
 #endif /* MSI_VALUE */
 /**
  * @brief Internal High Speed oscillator (HSI) value.
  *        This value is used by the RCC HAL module to compute the system frequency
  *        (when HSI is used as system clock source, directly or through the PLL).
  */
 #if !defined  (HSI_VALUE)
-  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 /**
@ -125,7 +129,7 @@
  *        which is subject to manufacturing process variations.
  */
 #if !defined  (HSI48_VALUE)
-  #define HSI48_VALUE   48000000U             /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+ #define HSI48_VALUE   ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
                                              The real value my vary depending on manufacturing process variations.*/
 #endif /* HSI48_VALUE */
@ -137,6 +141,7 @@
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                             The real value may vary depending on the variations
                                             in voltage and temperature.*/
 /**
  * @brief External Low Speed oscillator (LSE) value.
  *        This value is used by the UART, RTC HAL module to compute the system frequency
@ -155,7 +160,7 @@
  *        frequency.
  */
 #if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
-  #define EXTERNAL_SAI1_CLOCK_VALUE    48000U /*!< Value of the SAI1 External clock source in Hz*/
+  #define EXTERNAL_SAI1_CLOCK_VALUE    2097000U /*!< Value of the SAI1 External clock source in Hz*/
 #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
 /**
@ -164,7 +169,7 @@
  *        frequency.
  */
 #if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)
-  #define EXTERNAL_SAI2_CLOCK_VALUE    48000U /*!< Value of the SAI2 External clock source in Hz*/
+  #define EXTERNAL_SAI2_CLOCK_VALUE    2097000U /*!< Value of the SAI2 External clock source in Hz*/
 #endif /* EXTERNAL_SAI2_CLOCK_VALUE */
 /* Tip: To avoid modifying this file each time you need to use different HSE,
@ -174,10 +179,11 @@
 /**
  * @brief This is the HAL system configuration section
  */
 #define  VDD_VALUE					  3300U /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            0x0FU /*!< tick interrupt priority */
+#define  TICK_INT_PRIORITY            0U    /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              0U
+#define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
 #define  DATA_CACHE_ENABLE            1U
@ -240,7 +246,7 @@
 * Deactivated: CRC code cleaned from driver
 */
-#define USE_SPI_CRC                   1U
+#define USE_SPI_CRC                   0U
 /* Includes ------------------------------------------------------------------*/
 /**
@ -379,6 +385,14 @@
  #include "stm32l4xx_hal_pcd.h"
 #endif /* HAL_PCD_MODULE_ENABLED */
 #ifdef HAL_PKA_MODULE_ENABLED
  #include "stm32l4xx_hal_pka.h"
 #endif /* HAL_PKA_MODULE_ENABLED */
 #ifdef HAL_PSSI_MODULE_ENABLED
  #include "stm32l4xx_hal_pssi.h"
 #endif /* HAL_PSSI_MODULE_ENABLED */
 #ifdef HAL_PWR_MODULE_ENABLED
  #include "stm32l4xx_hal_pwr.h"
 #endif /* HAL_PWR_MODULE_ENABLED */
@ -447,7 +461,7 @@
 #ifdef  USE_FULL_ASSERT
 /**
  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
+  * @param  expr If expr is false, it calls assert_failed function
  *         which reports the name of the source file and the source
  *         line number of the call that failed.
  *         If expr is true, it returns no value.
@ -466,5 +480,4 @@
 #endif /* STM32L4xx_HAL_CONF_H */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Inc/stm32l4xx_it.h
+++ b/firmware/targets/f2/Inc/stm32l4xx_it.h
@ -23,7 +23,7 @@
 #define __STM32L4xx_IT_H
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 /* Private includes ----------------------------------------------------------*/
@ -53,12 +53,12 @@ void MemManage_Handler(void);
 void BusFault_Handler(void);
 void UsageFault_Handler(void);
 void DebugMon_Handler(void);
 void SysTick_Handler(void);
 void EXTI0_IRQHandler(void);
 void EXTI1_IRQHandler(void);
 void EXTI2_IRQHandler(void);
 void EXTI4_IRQHandler(void);
 void EXTI9_5_IRQHandler(void);
 void TIM1_TRG_COM_TIM17_IRQHandler(void);
 void TIM8_CC_IRQHandler(void);
 void OTG_FS_IRQHandler(void);
 /* USER CODE BEGIN EFP */
--- a/firmware/targets/f2/Inc/tim.h
+++ b/firmware/targets/f2/Inc/tim.h
@ -0,0 +1,64 @@
 /**
  ******************************************************************************
  * File Name          : TIM.h
  * Description        : This file provides code for the configuration
  *                      of the TIM instances.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __tim_H
 #define __tim_H
 #ifdef __cplusplus
 extern "C" {
 #endif
 /* Includes ------------------------------------------------------------------*/
 #include "main.h"
 /* USER CODE BEGIN Includes */
 /* USER CODE END Includes */
 extern TIM_HandleTypeDef htim5;
 extern TIM_HandleTypeDef htim8;
 extern TIM_HandleTypeDef htim15;
 /* USER CODE BEGIN Private defines */
 /* USER CODE END Private defines */
 void MX_TIM5_Init(void);
 void MX_TIM8_Init(void);
 void MX_TIM15_Init(void);
 void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
 /* USER CODE BEGIN Prototypes */
 /* USER CODE END Prototypes */
 #ifdef __cplusplus
 }
 #endif
 #endif /*__ tim_H */
 /**
  * @}
  */
 /**
  * @}
  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Inc/usart.h
+++ b/firmware/targets/f2/Inc/usart.h
@ -0,0 +1,58 @@
 /**
  ******************************************************************************
  * File Name          : USART.h
  * Description        : This file provides code for the configuration
  *                      of the USART instances.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __usart_H
 #define __usart_H
 #ifdef __cplusplus
 extern "C" {
 #endif
 /* Includes ------------------------------------------------------------------*/
 #include "main.h"
 /* USER CODE BEGIN Includes */
 /* USER CODE END Includes */
 extern UART_HandleTypeDef huart1;
 /* USER CODE BEGIN Private defines */
 /* USER CODE END Private defines */
 void MX_USART1_UART_Init(void);
 /* USER CODE BEGIN Prototypes */
 /* USER CODE END Prototypes */
 #ifdef __cplusplus
 }
 #endif
 #endif /*__ usart_H */
 /**
  * @}
  */
 /**
  * @}
  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Inc/usb_device.h
+++ b/firmware/targets/f2/Inc/usb_device.h
@ -24,7 +24,7 @@
 #define __USB_DEVICE__H__
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 /* Includes ------------------------------------------------------------------*/
--- a/firmware/targets/f2/Inc/usbd_cdc_if.h
+++ b/firmware/targets/f2/Inc/usbd_cdc_if.h
@ -24,7 +24,7 @@
 #define __USBD_CDC_IF_H__
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 /* Includes ------------------------------------------------------------------*/
@ -49,6 +49,10 @@ extern "C" {
  * @{
  */
 /* USER CODE BEGIN EXPORTED_DEFINES */
 /* Define size for the receive and transmit buffer over CDC */
 /* It's up to user to redefine and/or remove those define */
 #define APP_RX_DATA_SIZE  2048
 #define APP_TX_DATA_SIZE  2048
 /* USER CODE END EXPORTED_DEFINES */
--- a/firmware/targets/f2/Inc/usbd_conf.h
+++ b/firmware/targets/f2/Inc/usbd_conf.h
@ -24,7 +24,7 @@
 #define __USBD_CONF__H__
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 /* Includes ------------------------------------------------------------------*/
@ -92,44 +92,41 @@ extern "C" {
 /* Memory management macros */
 /** Alias for memory allocation. */
-#define USBD_malloc (uint32_t*)USBD_static_malloc
+#define USBD_malloc         malloc
 /** Alias for memory release. */
-#define USBD_free USBD_static_free
+#define USBD_free          free
 /** Alias for memory set. */
-#define USBD_memset /* Not used */
+#define USBD_memset         memset
 /** Alias for memory copy. */
-#define USBD_memcpy /* Not used */
+#define USBD_memcpy         memcpy
 /** Alias for delay. */
 #define USBD_Delay          HAL_Delay
 /* DEBUG macros */
-#if(USBD_DEBUG_LEVEL > 0)
+#if (USBD_DEBUG_LEVEL > 0)
-#define USBD_UsrLog(...) \
+#define USBD_UsrLog(...)    printf(__VA_ARGS__);\
    printf(__VA_ARGS__); \
                            printf("\n");
 #else
 #define USBD_UsrLog(...)
 #endif
-#if(USBD_DEBUG_LEVEL > 1)
+#if (USBD_DEBUG_LEVEL > 1)
-#define USBD_ErrLog(...) \
+#define USBD_ErrLog(...)    printf("ERROR: ") ;\
-    printf("ERROR: ");   \
+                            printf(__VA_ARGS__);\
    printf(__VA_ARGS__); \
                            printf("\n");
 #else
 #define USBD_ErrLog(...)
 #endif
-#if(USBD_DEBUG_LEVEL > 2)
+#if (USBD_DEBUG_LEVEL > 2)
-#define USBD_DbgLog(...) \
+#define USBD_DbgLog(...)    printf("DEBUG : ") ;\
-    printf("DEBUG : ");  \
+                            printf(__VA_ARGS__);\
    printf(__VA_ARGS__); \
                            printf("\n");
 #else
 #define USBD_DbgLog(...)
@ -154,8 +151,6 @@ extern "C" {
  */
 /* Exported functions -------------------------------------------------------*/
 void* USBD_static_malloc(uint32_t size);
 void USBD_static_free(void* p);
 /**
  * @}
--- a/firmware/targets/f2/Inc/usbd_desc.h
+++ b/firmware/targets/f2/Inc/usbd_desc.h
@ -23,7 +23,7 @@
 #define __USBD_DESC__C__
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 /* Includes ------------------------------------------------------------------*/
--- a/firmware/targets/f2/Makefile
+++ b/firmware/targets/f2/Makefile
@ -0,0 +1,235 @@
 ##########################################################################################################################
 # File automatically-generated by tool: [projectgenerator] version: [3.10.0-B14] date: [Fri Oct 02 17:54:23 MSK 2020] 
 ##########################################################################################################################
 # ------------------------------------------------
 # Generic Makefile (based on gcc)
 #
 # ChangeLog :
 #	2017-02-10 - Several enhancements + project update mode
 #   2015-07-22 - first version
 # ------------------------------------------------
 ######################################
 # target
 ######################################
 TARGET = cube
 ######################################
 # building variables
 ######################################
 # debug build?
 DEBUG = 1
 # optimization
 OPT = -Og
 #######################################
 # paths
 #######################################
 # Build path
 BUILD_DIR = build
 ######################################
 # source
 ######################################
 # C sources
 C_SOURCES =  \
 Src/main.c \
 Src/gpio.c \
 Src/freertos.c \
 Src/adc.c \
 Src/comp.c \
 Src/spi.c \
 Src/tim.c \
 Src/usart.c \
 Src/usb_device.c \
 Src/usbd_conf.c \
 Src/usbd_desc.c \
 Src/usbd_cdc_if.c \
 Src/stm32l4xx_it.c \
 Src/stm32l4xx_hal_msp.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c \
 Src/system_stm32l4xx.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/Third_Party/FreeRTOS/Source/croutine.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/Third_Party/FreeRTOS/Source/list.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/Third_Party/FreeRTOS/Source/queue.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/Third_Party/FreeRTOS/Source/tasks.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/Third_Party/FreeRTOS/Source/timers.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c \
 /Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c \
 Src/stm32l4xx_hal_timebase_tim.c
 # ASM sources
 ASM_SOURCES =  \
 startup_stm32l476xx.s
 #######################################
 # binaries
 #######################################
 PREFIX = arm-none-eabi-
 # The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx)
 # either it can be added to the PATH environment variable.
 ifdef GCC_PATH
 CC = $(GCC_PATH)/$(PREFIX)gcc
 AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp
 CP = $(GCC_PATH)/$(PREFIX)objcopy
 SZ = $(GCC_PATH)/$(PREFIX)size
 else
 CC = $(PREFIX)gcc
 AS = $(PREFIX)gcc -x assembler-with-cpp
 CP = $(PREFIX)objcopy
 SZ = $(PREFIX)size
 endif
 HEX = $(CP) -O ihex
 BIN = $(CP) -O binary -S
 #######################################
 # CFLAGS
 #######################################
 # cpu
 CPU = -mcpu=cortex-m4
 # fpu
 FPU = -mfpu=fpv4-sp-d16
 # float-abi
 FLOAT-ABI = -mfloat-abi=hard
 # mcu
 MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
 # macros for gcc
 # AS defines
 AS_DEFS = 
 # C defines
 C_DEFS =  \
 -DUSE_HAL_DRIVER \
 -DSTM32L476xx
 # AS includes
 AS_INCLUDES =  \
 -IInc
 # C includes
 C_INCLUDES =  \
 -IInc \
 -I/Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Inc \
 -I/Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy \
 -I/Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/Third_Party/FreeRTOS/Source/include \
 -I/Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 \
 -I/Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F \
 -I/Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/ST/STM32_USB_Device_Library/Core/Inc \
 -I/Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc \
 -I/Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/CMSIS/Device/ST/STM32L4xx/Include \
 -I/Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/CMSIS/Include
 -I/Users/aku/Work/flipper/flipperzero-firmware-community/lib/STM32CubeL4/Drivers/CMSIS/Include
 # compile gcc flags
 ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
 CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
 ifeq ($(DEBUG), 1)
 CFLAGS += -g -gdwarf-2
 endif
 # Generate dependency information
 CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
 #######################################
 # LDFLAGS
 #######################################
 # link script
 LDSCRIPT = STM32L476RGTx_FLASH.ld
 # libraries
 LIBS = -lc -lm -lnosys 
 LIBDIR = 
 LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
 # default action: build all
 all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
 #######################################
 # build the application
 #######################################
 # list of objects
 OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
 vpath %.c $(sort $(dir $(C_SOURCES)))
 # list of ASM program objects
 OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
 vpath %.s $(sort $(dir $(ASM_SOURCES)))
 $(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) 
 	$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
 $(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
 	$(AS) -c $(CFLAGS) $< -o $@
 $(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
 	$(CC) $(OBJECTS) $(LDFLAGS) -o $@
 	$(SZ) $@
 $(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
 	$(HEX) $< $@
 $(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
 	$(BIN) $< $@	
 $(BUILD_DIR):
 	mkdir $@		
 #######################################
 # clean up
 #######################################
 clean:
 	-rm -fR $(BUILD_DIR)
 #######################################
 # dependencies
 #######################################
 -include $(wildcard $(BUILD_DIR)/*.d)
 # *** EOF ***
--- a/firmware/targets/f2/STM32L476RGTx_FLASH.ld
+++ b/firmware/targets/f2/STM32L476RGTx_FLASH.ld
@ -63,7 +63,7 @@ MEMORY
 {
 RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 96K
 RAM2 (xrw)      : ORIGIN = 0x10000000, LENGTH = 32K
-FLASH (rx)      : ORIGIN = 0x08008000, LENGTH = 992K
+FLASH (rx)      : ORIGIN = 0x8008000, LENGTH = 992K
 }
 /* Define output sections */
--- a/firmware/targets/f2/Src/adc.c
+++ b/firmware/targets/f2/Src/adc.c
@ -0,0 +1,141 @@
 /**
  ******************************************************************************
  * File Name          : ADC.c
  * Description        : This file provides code for the configuration
  *                      of the ADC instances.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* Includes ------------------------------------------------------------------*/
 #include "adc.h"
 /* USER CODE BEGIN 0 */
 /* USER CODE END 0 */
 ADC_HandleTypeDef hadc1;
 /* ADC1 init function */
 void MX_ADC1_Init(void)
 {
  ADC_MultiModeTypeDef multimode = {0};
  ADC_ChannelConfTypeDef sConfig = {0};
  /** Common config
  */
  hadc1.Instance = ADC1;
  hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
  hadc1.Init.Resolution = ADC_RESOLUTION_12B;
  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
  hadc1.Init.LowPowerAutoWait = DISABLE;
  hadc1.Init.ContinuousConvMode = DISABLE;
  hadc1.Init.NbrOfConversion = 1;
  hadc1.Init.DiscontinuousConvMode = DISABLE;
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
  hadc1.Init.DMAContinuousRequests = DISABLE;
  hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
  hadc1.Init.OversamplingMode = DISABLE;
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
  {
    Error_Handler();
  }
  /** Configure the ADC multi-mode
  */
  multimode.Mode = ADC_MODE_INDEPENDENT;
  if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
  {
    Error_Handler();
  }
  /** Configure Regular Channel
  */
  sConfig.Channel = ADC_CHANNEL_4;
  sConfig.Rank = ADC_REGULAR_RANK_1;
  sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
  sConfig.SingleDiff = ADC_SINGLE_ENDED;
  sConfig.OffsetNumber = ADC_OFFSET_NONE;
  sConfig.Offset = 0;
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
  {
    Error_Handler();
  }
 }
 void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
 {
  GPIO_InitTypeDef GPIO_InitStruct = {0};
  if(adcHandle->Instance==ADC1)
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */
  /* USER CODE END ADC1_MspInit 0 */
    /* ADC1 clock enable */
    __HAL_RCC_ADC_CLK_ENABLE();
    __HAL_RCC_GPIOC_CLK_ENABLE();
    __HAL_RCC_GPIOA_CLK_ENABLE();
    /**ADC1 GPIO Configuration
    PC3     ------> ADC1_IN4
    PA0     ------> ADC1_IN5
    */
    GPIO_InitStruct.Pin = BATT_V_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(BATT_V_GPIO_Port, &GPIO_InitStruct);
    GPIO_InitStruct.Pin = IR_RX_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(IR_RX_GPIO_Port, &GPIO_InitStruct);
  /* USER CODE BEGIN ADC1_MspInit 1 */
  /* USER CODE END ADC1_MspInit 1 */
  }
 }
 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)
 {
  if(adcHandle->Instance==ADC1)
  {
  /* USER CODE BEGIN ADC1_MspDeInit 0 */
  /* USER CODE END ADC1_MspDeInit 0 */
    /* Peripheral clock disable */
    __HAL_RCC_ADC_CLK_DISABLE();
    /**ADC1 GPIO Configuration
    PC3     ------> ADC1_IN4
    PA0     ------> ADC1_IN5
    */
    HAL_GPIO_DeInit(BATT_V_GPIO_Port, BATT_V_Pin);
    HAL_GPIO_DeInit(IR_RX_GPIO_Port, IR_RX_Pin);
  /* USER CODE BEGIN ADC1_MspDeInit 1 */
  /* USER CODE END ADC1_MspDeInit 1 */
  }
 }
 /* USER CODE BEGIN 1 */
 /* USER CODE END 1 */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Src/comp.c
+++ b/firmware/targets/f2/Src/comp.c
@ -0,0 +1,98 @@
 /**
  ******************************************************************************
  * File Name          : COMP.c
  * Description        : This file provides code for the configuration
  *                      of the COMP instances.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* Includes ------------------------------------------------------------------*/
 #include "comp.h"
 /* USER CODE BEGIN 0 */
 /* USER CODE END 0 */
 COMP_HandleTypeDef hcomp1;
 /* COMP1 init function */
 void MX_COMP1_Init(void)
 {
  hcomp1.Instance = COMP1;
  hcomp1.Init.InvertingInput = COMP_INPUT_MINUS_1_2VREFINT;
  hcomp1.Init.NonInvertingInput = COMP_INPUT_PLUS_IO1;
  hcomp1.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED;
  hcomp1.Init.Hysteresis = COMP_HYSTERESIS_NONE;
  hcomp1.Init.BlankingSrce = COMP_BLANKINGSRC_NONE;
  hcomp1.Init.Mode = COMP_POWERMODE_HIGHSPEED;
  hcomp1.Init.WindowMode = COMP_WINDOWMODE_DISABLE;
  hcomp1.Init.TriggerMode = COMP_TRIGGERMODE_NONE;
  if (HAL_COMP_Init(&hcomp1) != HAL_OK)
  {
    Error_Handler();
  }
 }
 void HAL_COMP_MspInit(COMP_HandleTypeDef* compHandle)
 {
  GPIO_InitTypeDef GPIO_InitStruct = {0};
  if(compHandle->Instance==COMP1)
  {
  /* USER CODE BEGIN COMP1_MspInit 0 */
  /* USER CODE END COMP1_MspInit 0 */
    __HAL_RCC_GPIOC_CLK_ENABLE();
    /**COMP1 GPIO Configuration
    PC5     ------> COMP1_INP
    */
    GPIO_InitStruct.Pin = RFID_RF_IN_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    HAL_GPIO_Init(RFID_RF_IN_GPIO_Port, &GPIO_InitStruct);
  /* USER CODE BEGIN COMP1_MspInit 1 */
  /* USER CODE END COMP1_MspInit 1 */
  }
 }
 void HAL_COMP_MspDeInit(COMP_HandleTypeDef* compHandle)
 {
  if(compHandle->Instance==COMP1)
  {
  /* USER CODE BEGIN COMP1_MspDeInit 0 */
  /* USER CODE END COMP1_MspDeInit 0 */
    /**COMP1 GPIO Configuration
    PC5     ------> COMP1_INP
    */
    HAL_GPIO_DeInit(RFID_RF_IN_GPIO_Port, RFID_RF_IN_Pin);
  /* USER CODE BEGIN COMP1_MspDeInit 1 */
  /* USER CODE END COMP1_MspDeInit 1 */
  }
 }
 /* USER CODE BEGIN 1 */
 /* USER CODE END 1 */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Src/flipper_hal.c
+++ b/firmware/targets/f2/Src/flipper_hal.c
--- a/firmware/targets/f2/Src/freertos.c
+++ b/firmware/targets/f2/Src/freertos.c
@ -22,10 +22,10 @@
 #include "FreeRTOS.h"
 #include "task.h"
 #include "main.h"
 #include "cmsis_os.h"
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
 #include <stdbool.h>
 /* USER CODE END Includes */
@ -48,29 +48,38 @@
 /* USER CODE BEGIN Variables */
 /* USER CODE END Variables */
 /* Definitions for defaultTask */
 osThreadId_t defaultTaskHandle;
 const osThreadAttr_t defaultTask_attributes = {
  .name = "defaultTask",
  .priority = (osPriority_t) osPriorityNormal,
  .stack_size = 1024 * 4
 };
 /* Definitions for app_main */
 osThreadId_t app_mainHandle;
 const osThreadAttr_t app_main_attributes = {
  .name = "app_main",
  .priority = (osPriority_t) osPriorityLow,
  .stack_size = 128 * 4
 };
 /* Private function prototypes -----------------------------------------------*/
 /* USER CODE BEGIN FunctionPrototypes */
 /* USER CODE END FunctionPrototypes */
-/* GetIdleTaskMemory prototype (linked to static allocation support) */
+void StartDefaultTask(void *argument);
-void vApplicationGetIdleTaskMemory(
+extern void app(void *argument);
    StaticTask_t** ppxIdleTaskTCBBuffer,
    StackType_t** ppxIdleTaskStackBuffer,
    uint32_t* pulIdleTaskStackSize);
-/* GetTimerTaskMemory prototype (linked to static allocation support) */
+extern void MX_USB_DEVICE_Init(void);
-void vApplicationGetTimerTaskMemory(
+void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */
    StaticTask_t** ppxTimerTaskTCBBuffer,
    StackType_t** ppxTimerTaskStackBuffer,
    uint32_t* pulTimerTaskStackSize);
 /* Hook prototypes */
 void vApplicationIdleHook(void);
 /* USER CODE BEGIN 2 */
-__weak void vApplicationIdleHook(void) {
+__weak void vApplicationIdleHook( void )
 {
   /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
   to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
   task. It is essential that code added to this hook function never attempts
@ -83,43 +92,67 @@ __weak void vApplicationIdleHook(void) {
 }
 /* USER CODE END 2 */
-/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
+/**
-static StaticTask_t xIdleTaskTCBBuffer;
+  * @brief  FreeRTOS initialization
-static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
+  * @param  None
  * @retval None
  */
 void MX_FREERTOS_Init(void) {
  /* USER CODE BEGIN Init */
  /* USER CODE END Init */
  /* USER CODE BEGIN RTOS_MUTEX */
  /* add mutexes, ... */
  /* USER CODE END RTOS_MUTEX */
  /* USER CODE BEGIN RTOS_SEMAPHORES */
  /* add semaphores, ... */
  /* USER CODE END RTOS_SEMAPHORES */
  /* USER CODE BEGIN RTOS_TIMERS */
  /* start timers, add new ones, ... */
  /* USER CODE END RTOS_TIMERS */
  /* USER CODE BEGIN RTOS_QUEUES */
  /* add queues, ... */
  /* USER CODE END RTOS_QUEUES */
  /* Create the thread(s) */
  /* creation of defaultTask */
  defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);
  /* creation of app_main */
  app_mainHandle = osThreadNew(app, NULL, &app_main_attributes);
  /* USER CODE BEGIN RTOS_THREADS */
  /* add threads, ... */
  /* USER CODE END RTOS_THREADS */
 void vApplicationGetIdleTaskMemory(
    StaticTask_t** ppxIdleTaskTCBBuffer,
    StackType_t** ppxIdleTaskStackBuffer,
    uint32_t* pulIdleTaskStackSize) {
    *ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer;
    *ppxIdleTaskStackBuffer = &xIdleStack[0];
    *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
    /* place for user code */
 }
 /* USER CODE END GET_IDLE_TASK_MEMORY */
-/* USER CODE BEGIN GET_TIMER_TASK_MEMORY */
+/* USER CODE BEGIN Header_StartDefaultTask */
-static StaticTask_t xTimerTaskTCBBuffer;
+/**
-static StackType_t xTimerStack[configTIMER_TASK_STACK_DEPTH];
+  * @brief  Function implementing the defaultTask thread.
-
+  * @param  argument: Not used
-void vApplicationGetTimerTaskMemory(
+  * @retval None
-    StaticTask_t** ppxTimerTaskTCBBuffer,
+  */
-    StackType_t** ppxTimerTaskStackBuffer,
+/* USER CODE END Header_StartDefaultTask */
-    uint32_t* pulTimerTaskStackSize) {
+void StartDefaultTask(void *argument)
-    *ppxTimerTaskTCBBuffer = &xTimerTaskTCBBuffer;
+{
-    *ppxTimerTaskStackBuffer = &xTimerStack[0];
+  /* init code for USB_DEVICE */
-    *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+  MX_USB_DEVICE_Init();
-    /* place for user code */
+  /* USER CODE BEGIN StartDefaultTask */
  /* Infinite loop */
  for(;;)
  {
    osDelay(1);
  }
  /* USER CODE END StartDefaultTask */
 }
 /* USER CODE END GET_TIMER_TASK_MEMORY */
 /* Private application code --------------------------------------------------*/
 /* USER CODE BEGIN Application */
 bool task_equal(TaskHandle_t a, TaskHandle_t b) {
    if(a == NULL || b == NULL) return false;
    return a == b;
 }
 /* USER CODE END Application */
--- a/firmware/targets/f2/Src/gpio.c
+++ b/firmware/targets/f2/Src/gpio.c
@ -0,0 +1,184 @@
 /**
  ******************************************************************************
  * File Name          : gpio.c
  * Description        : This file provides code for the configuration
  *                      of all used GPIO pins.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* Includes ------------------------------------------------------------------*/
 #include "gpio.h"
 /* USER CODE BEGIN 0 */
 /* USER CODE END 0 */
 /*----------------------------------------------------------------------------*/
 /* Configure GPIO                                                             */
 /*----------------------------------------------------------------------------*/
 /* USER CODE BEGIN 1 */
 /* USER CODE END 1 */
 /** Configure pins as
        * Analog
        * Input
        * Output
        * EVENT_OUT
        * EXTI
 */
 void MX_GPIO_Init(void)
 {
  GPIO_InitTypeDef GPIO_InitStruct = {0};
  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
  __HAL_RCC_GPIOH_CLK_ENABLE();
  __HAL_RCC_GPIOA_CLK_ENABLE();
  __HAL_RCC_GPIOB_CLK_ENABLE();
  __HAL_RCC_GPIOD_CLK_ENABLE();
  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOA, DISPLAY_DI_Pin|CC1101_CS_Pin, GPIO_PIN_RESET);
  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOC, NFC_CS_Pin|VIBRO_Pin|DISPLAY_CS_Pin|SD_CS_Pin, GPIO_PIN_RESET);
  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOB, LED_BLUE_Pin|LED_GREEN_Pin, GPIO_PIN_SET);
  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOB, DISPLAY_RST_Pin|IR_TX_Pin|DISPLAY_BACKLIGHT_Pin, GPIO_PIN_RESET);
  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(LED_RED_GPIO_Port, LED_RED_Pin, GPIO_PIN_SET);
  /*Configure GPIO pin : PtPin */
  GPIO_InitStruct.Pin = BUTTON_BACK_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
  HAL_GPIO_Init(BUTTON_BACK_GPIO_Port, &GPIO_InitStruct);
  /*Configure GPIO pins : PC0 PC1 */
  GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  /*Configure GPIO pin : PtPin */
  GPIO_InitStruct.Pin = CHRG_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
  GPIO_InitStruct.Pull = GPIO_PULLUP;
  HAL_GPIO_Init(CHRG_GPIO_Port, &GPIO_InitStruct);
  /*Configure GPIO pin : PtPin */
  GPIO_InitStruct.Pin = BUTTON_DOWN_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
  HAL_GPIO_Init(BUTTON_DOWN_GPIO_Port, &GPIO_InitStruct);
  /*Configure GPIO pins : PAPin PAPin */
  GPIO_InitStruct.Pin = DISPLAY_DI_Pin|CC1101_CS_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  /*Configure GPIO pins : PA4 PA5 PA6 PA7 */
  GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  /*Configure GPIO pins : PCPin PCPin PCPin PCPin */
  GPIO_InitStruct.Pin = NFC_CS_Pin|VIBRO_Pin|DISPLAY_CS_Pin|SD_CS_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  /*Configure GPIO pins : PBPin PBPin PBPin */
  GPIO_InitStruct.Pin = BUTTON_UP_Pin|BUTTON_RIGHT_Pin|BUTTON_OK_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  /*Configure GPIO pins : PBPin PBPin */
  GPIO_InitStruct.Pin = LED_BLUE_Pin|LED_GREEN_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  /*Configure GPIO pins : PB2 PB12 */
  GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_12;
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  /*Configure GPIO pins : PBPin PBPin PBPin */
  GPIO_InitStruct.Pin = DISPLAY_RST_Pin|IR_TX_Pin|DISPLAY_BACKLIGHT_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  /*Configure GPIO pin : PtPin */
  GPIO_InitStruct.Pin = LED_RED_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
  HAL_GPIO_Init(LED_RED_GPIO_Port, &GPIO_InitStruct);
  /*Configure GPIO pin : PD2 */
  GPIO_InitStruct.Pin = GPIO_PIN_2;
  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
  /*Configure GPIO pin : PtPin */
  GPIO_InitStruct.Pin = BUTTON_LEFT_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
  HAL_GPIO_Init(BUTTON_LEFT_GPIO_Port, &GPIO_InitStruct);
  /*Configure GPIO pin : PtPin */
  GPIO_InitStruct.Pin = CC1101_G0_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  HAL_GPIO_Init(CC1101_G0_GPIO_Port, &GPIO_InitStruct);
  /* EXTI interrupt init*/
  HAL_NVIC_SetPriority(EXTI0_IRQn, 5, 0);
  HAL_NVIC_EnableIRQ(EXTI0_IRQn);
  HAL_NVIC_SetPriority(EXTI1_IRQn, 5, 0);
  HAL_NVIC_EnableIRQ(EXTI1_IRQn);
  HAL_NVIC_SetPriority(EXTI2_IRQn, 5, 0);
  HAL_NVIC_EnableIRQ(EXTI2_IRQn);
  HAL_NVIC_SetPriority(EXTI4_IRQn, 5, 0);
  HAL_NVIC_EnableIRQ(EXTI4_IRQn);
  HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0);
  HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
 }
 /* USER CODE BEGIN 2 */
 /* USER CODE END 2 */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Src/hacks.c
+++ b/firmware/targets/f2/Src/hacks.c
@ -0,0 +1,7 @@
 #include <cmsis_os.h>
 #include <stdbool.h>
 bool task_equal(TaskHandle_t a, TaskHandle_t b) {
    if(a == NULL || b == NULL) return false;
    return a == b;
 }
--- a/firmware/targets/f2/Src/main.c
+++ b/firmware/targets/f2/Src/main.c
@ -0,0 +1,242 @@
 /* USER CODE BEGIN Header */
 /**
  ******************************************************************************
  * @file           : main.c
  * @brief          : Main program body
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* USER CODE END Header */
 /* Includes ------------------------------------------------------------------*/
 #include "main.h"
 #include "cmsis_os.h"
 #include "adc.h"
 #include "comp.h"
 #include "spi.h"
 #include "tim.h"
 #include "usart.h"
 #include "usb_device.h"
 #include "gpio.h"
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
 /* USER CODE END Includes */
 /* Private typedef -----------------------------------------------------------*/
 /* USER CODE BEGIN PTD */
 /* USER CODE END PTD */
 /* Private define ------------------------------------------------------------*/
 /* USER CODE BEGIN PD */
 /* USER CODE END PD */
 /* Private macro -------------------------------------------------------------*/
 /* USER CODE BEGIN PM */
 /* USER CODE END PM */
 /* Private variables ---------------------------------------------------------*/
 /* USER CODE BEGIN PV */
 /* USER CODE END PV */
 /* Private function prototypes -----------------------------------------------*/
 void SystemClock_Config(void);
 void MX_FREERTOS_Init(void);
 /* USER CODE BEGIN PFP */
 /* USER CODE END PFP */
 /* Private user code ---------------------------------------------------------*/
 /* USER CODE BEGIN 0 */
 /* USER CODE END 0 */
 /**
  * @brief  The application entry point.
  * @retval int
  */
 int main(void)
 {
  /* USER CODE BEGIN 1 */
  /* USER CODE END 1 */
  /* MCU Configuration--------------------------------------------------------*/
  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
  /* USER CODE BEGIN Init */
  /* USER CODE END Init */
  /* Configure the system clock */
  SystemClock_Config();
  /* USER CODE BEGIN SysInit */
  /* USER CODE END SysInit */
  /* Initialize all configured peripherals */
  MX_GPIO_Init();
  MX_SPI1_Init();
  MX_SPI3_Init();
  MX_ADC1_Init();
  MX_COMP1_Init();
  MX_TIM5_Init();
  MX_TIM15_Init();
  MX_USART1_UART_Init();
  MX_TIM8_Init();
  /* USER CODE BEGIN 2 */
  /* USER CODE END 2 */
  /* Init scheduler */
  osKernelInitialize();  /* Call init function for freertos objects (in freertos.c) */
  MX_FREERTOS_Init();
  /* Start scheduler */
  osKernelStart();
  /* We should never get here as control is now taken by the scheduler */
  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
  {
    /* USER CODE END WHILE */
    /* USER CODE BEGIN 3 */
  }
  /* USER CODE END 3 */
 }
 /**
  * @brief System Clock Configuration
  * @retval None
  */
 void SystemClock_Config(void)
 {
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = 2;
  RCC_OscInitStruct.PLL.PLLN = 16;
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }
  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
  {
    Error_Handler();
  }
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USB
                              |RCC_PERIPHCLK_ADC;
  PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
  PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK;
  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
  PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
  PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
  PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
  PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
  PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
  PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
  PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
  {
    Error_Handler();
  }
  /** Configure the main internal regulator output voltage
  */
  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
  {
    Error_Handler();
  }
 }
 /* USER CODE BEGIN 4 */
 /* USER CODE END 4 */
 /**
  * @brief  Period elapsed callback in non blocking mode
  * @note   This function is called  when TIM17 interrupt took place, inside
  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
  * a global variable "uwTick" used as application time base.
  * @param  htim : TIM handle
  * @retval None
  */
 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
 {
  /* USER CODE BEGIN Callback 0 */
  /* USER CODE END Callback 0 */
  if (htim->Instance == TIM17) {
    HAL_IncTick();
  }
  /* USER CODE BEGIN Callback 1 */
  /* USER CODE END Callback 1 */
 }
 /**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
 void Error_Handler(void)
 {
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  /* USER CODE END Error_Handler_Debug */
 }
 #ifdef  USE_FULL_ASSERT
 /**
  * @brief  Reports the name of the source file and the source line number
  *         where the assert_param error has occurred.
  * @param  file: pointer to the source file name
  * @param  line: assert_param error line source number
  * @retval None
  */
 void assert_failed(uint8_t *file, uint32_t line)
 {
  /* USER CODE BEGIN 6 */
  /* User can add his own implementation to report the file name and line number,
     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
  /* USER CODE END 6 */
 }
 #endif /* USE_FULL_ASSERT */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Src/spi.c
+++ b/firmware/targets/f2/Src/spi.c
@ -0,0 +1,180 @@
 /**
  ******************************************************************************
  * File Name          : SPI.c
  * Description        : This file provides code for the configuration
  *                      of the SPI instances.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* Includes ------------------------------------------------------------------*/
 #include "spi.h"
 /* USER CODE BEGIN 0 */
 /* USER CODE END 0 */
 SPI_HandleTypeDef hspi1;
 SPI_HandleTypeDef hspi3;
 /* SPI1 init function */
 void MX_SPI1_Init(void)
 {
  hspi1.Instance = SPI1;
  hspi1.Init.Mode = SPI_MODE_MASTER;
  hspi1.Init.Direction = SPI_DIRECTION_2LINES;
  hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
  hspi1.Init.NSS = SPI_NSS_SOFT;
  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
  hspi1.Init.CRCPolynomial = 7;
  hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
  hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
  if (HAL_SPI_Init(&hspi1) != HAL_OK)
  {
    Error_Handler();
  }
 }
 /* SPI3 init function */
 void MX_SPI3_Init(void)
 {
  hspi3.Instance = SPI3;
  hspi3.Init.Mode = SPI_MODE_MASTER;
  hspi3.Init.Direction = SPI_DIRECTION_2LINES;
  hspi3.Init.DataSize = SPI_DATASIZE_8BIT;
  hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;
  hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;
  hspi3.Init.NSS = SPI_NSS_SOFT;
  hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
  hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;
  hspi3.Init.TIMode = SPI_TIMODE_DISABLE;
  hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
  hspi3.Init.CRCPolynomial = 7;
  hspi3.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
  hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
  if (HAL_SPI_Init(&hspi3) != HAL_OK)
  {
    Error_Handler();
  }
 }
 void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
 {
  GPIO_InitTypeDef GPIO_InitStruct = {0};
  if(spiHandle->Instance==SPI1)
  {
  /* USER CODE BEGIN SPI1_MspInit 0 */
  /* USER CODE END SPI1_MspInit 0 */
    /* SPI1 clock enable */
    __HAL_RCC_SPI1_CLK_ENABLE();
    __HAL_RCC_GPIOB_CLK_ENABLE();
    /**SPI1 GPIO Configuration
    PB3 (JTDO-TRACESWO)     ------> SPI1_SCK
    PB5     ------> SPI1_MOSI
    */
    GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  /* USER CODE BEGIN SPI1_MspInit 1 */
  /* USER CODE END SPI1_MspInit 1 */
  }
  else if(spiHandle->Instance==SPI3)
  {
  /* USER CODE BEGIN SPI3_MspInit 0 */
  /* USER CODE END SPI3_MspInit 0 */
    /* SPI3 clock enable */
    __HAL_RCC_SPI3_CLK_ENABLE();
    __HAL_RCC_GPIOC_CLK_ENABLE();
    /**SPI3 GPIO Configuration
    PC10     ------> SPI3_SCK
    PC11     ------> SPI3_MISO
    PC12     ------> SPI3_MOSI
    */
    GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
    GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
  /* USER CODE BEGIN SPI3_MspInit 1 */
  /* USER CODE END SPI3_MspInit 1 */
  }
 }
 void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
 {
  if(spiHandle->Instance==SPI1)
  {
  /* USER CODE BEGIN SPI1_MspDeInit 0 */
  /* USER CODE END SPI1_MspDeInit 0 */
    /* Peripheral clock disable */
    __HAL_RCC_SPI1_CLK_DISABLE();
    /**SPI1 GPIO Configuration
    PB3 (JTDO-TRACESWO)     ------> SPI1_SCK
    PB5     ------> SPI1_MOSI
    */
    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_5);
  /* USER CODE BEGIN SPI1_MspDeInit 1 */
  /* USER CODE END SPI1_MspDeInit 1 */
  }
  else if(spiHandle->Instance==SPI3)
  {
  /* USER CODE BEGIN SPI3_MspDeInit 0 */
  /* USER CODE END SPI3_MspDeInit 0 */
    /* Peripheral clock disable */
    __HAL_RCC_SPI3_CLK_DISABLE();
    /**SPI3 GPIO Configuration
    PC10     ------> SPI3_SCK
    PC11     ------> SPI3_MISO
    PC12     ------> SPI3_MOSI
    */
    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12);
  /* USER CODE BEGIN SPI3_MspDeInit 1 */
  /* USER CODE END SPI3_MspDeInit 1 */
  }
 }
 /* USER CODE BEGIN 1 */
 /* USER CODE END 1 */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Src/stm32l4xx_hal_msp.c
+++ b/firmware/targets/f2/Src/stm32l4xx_hal_msp.c
@ -0,0 +1,86 @@
 /* USER CODE BEGIN Header */
 /**
  ******************************************************************************
  * File Name          : stm32l4xx_hal_msp.c
  * Description        : This file provides code for the MSP Initialization
  *                      and de-Initialization codes.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* USER CODE END Header */
 /* Includes ------------------------------------------------------------------*/
 #include "main.h"
 /* USER CODE BEGIN Includes */
 /* USER CODE END Includes */
 /* Private typedef -----------------------------------------------------------*/
 /* USER CODE BEGIN TD */
 /* USER CODE END TD */
 /* Private define ------------------------------------------------------------*/
 /* USER CODE BEGIN Define */
 /* USER CODE END Define */
 /* Private macro -------------------------------------------------------------*/
 /* USER CODE BEGIN Macro */
 /* USER CODE END Macro */
 /* Private variables ---------------------------------------------------------*/
 /* USER CODE BEGIN PV */
 /* USER CODE END PV */
 /* Private function prototypes -----------------------------------------------*/
 /* USER CODE BEGIN PFP */
 /* USER CODE END PFP */
 /* External functions --------------------------------------------------------*/
 /* USER CODE BEGIN ExternalFunctions */
 /* USER CODE END ExternalFunctions */
 /* USER CODE BEGIN 0 */
 /* USER CODE END 0 */
 /**
  * Initializes the Global MSP.
  */
 void HAL_MspInit(void)
 {
  /* USER CODE BEGIN MspInit 0 */
  /* USER CODE END MspInit 0 */
  __HAL_RCC_SYSCFG_CLK_ENABLE();
  __HAL_RCC_PWR_CLK_ENABLE();
  /* System interrupt init*/
  /* PendSV_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
  /* USER CODE BEGIN MspInit 1 */
  /* USER CODE END MspInit 1 */
 }
 /* USER CODE BEGIN 1 */
 /* USER CODE END 1 */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Src/stm32l4xx_hal_timebase_tim.c
+++ b/firmware/targets/f2/Src/stm32l4xx_hal_timebase_tim.c
@ -0,0 +1,112 @@
 /* USER CODE BEGIN Header */
 /**
  ******************************************************************************
  * @file    stm32l4xx_hal_timebase_TIM.c
  * @brief   HAL time base based on the hardware TIM.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* USER CODE END Header */
 /* Includes ------------------------------------------------------------------*/
 #include "stm32l4xx_hal.h"
 #include "stm32l4xx_hal_tim.h"
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 TIM_HandleTypeDef        htim17;
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
 /**
  * @brief  This function configures the TIM17 as a time base source.
  *         The time source is configured  to have 1ms time base with a dedicated
  *         Tick interrupt priority.
  * @note   This function is called  automatically at the beginning of program after
  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
  * @param  TickPriority: Tick interrupt priority.
  * @retval HAL status
  */
 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
 {
  RCC_ClkInitTypeDef    clkconfig;
  uint32_t              uwTimclock = 0;
  uint32_t              uwPrescalerValue = 0;
  uint32_t              pFLatency;
  /*Configure the TIM17 IRQ priority */
  HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, TickPriority ,0);
  /* Enable the TIM17 global Interrupt */
  HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn);
  /* Enable TIM17 clock */
  __HAL_RCC_TIM17_CLK_ENABLE();
  /* Get clock configuration */
  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
  /* Compute TIM17 clock */
  uwTimclock = HAL_RCC_GetPCLK2Freq();
  /* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */
  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1);
  /* Initialize TIM17 */
  htim17.Instance = TIM17;
  /* Initialize TIMx peripheral as follow:
  + Period = [(TIM17CLK/1000) - 1]. to have a (1/1000) s time base.
  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
  + ClockDivision = 0
  + Counter direction = Up
  */
  htim17.Init.Period = (1000000 / 1000) - 1;
  htim17.Init.Prescaler = uwPrescalerValue;
  htim17.Init.ClockDivision = 0;
  htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
  if(HAL_TIM_Base_Init(&htim17) == HAL_OK)
  {
    /* Start the TIM time Base generation in interrupt mode */
    return HAL_TIM_Base_Start_IT(&htim17);
  }
  /* Return function status */
  return HAL_ERROR;
 }
 /**
  * @brief  Suspend Tick increment.
  * @note   Disable the tick increment by disabling TIM17 update interrupt.
  * @param  None
  * @retval None
  */
 void HAL_SuspendTick(void)
 {
  /* Disable TIM17 update Interrupt */
  __HAL_TIM_DISABLE_IT(&htim17, TIM_IT_UPDATE);
 }
 /**
  * @brief  Resume Tick increment.
  * @note   Enable the tick increment by Enabling TIM17 update interrupt.
  * @param  None
  * @retval None
  */
 void HAL_ResumeTick(void)
 {
  /* Enable TIM17 Update interrupt */
  __HAL_TIM_ENABLE_IT(&htim17, TIM_IT_UPDATE);
 }
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Src/stm32l4xx_it.c
+++ b/firmware/targets/f2/Src/stm32l4xx_it.c
@ -0,0 +1,279 @@
 /* USER CODE BEGIN Header */
 /**
  ******************************************************************************
  * @file    stm32l4xx_it.c
  * @brief   Interrupt Service Routines.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* USER CODE END Header */
 /* Includes ------------------------------------------------------------------*/
 #include "main.h"
 #include "stm32l4xx_it.h"
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
 /* USER CODE END Includes */
 /* Private typedef -----------------------------------------------------------*/
 /* USER CODE BEGIN TD */
 /* USER CODE END TD */
 /* Private define ------------------------------------------------------------*/
 /* USER CODE BEGIN PD */
 /* USER CODE END PD */
 /* Private macro -------------------------------------------------------------*/
 /* USER CODE BEGIN PM */
 /* USER CODE END PM */
 /* Private variables ---------------------------------------------------------*/
 /* USER CODE BEGIN PV */
 /* USER CODE END PV */
 /* Private function prototypes -----------------------------------------------*/
 /* USER CODE BEGIN PFP */
 /* USER CODE END PFP */
 /* Private user code ---------------------------------------------------------*/
 /* USER CODE BEGIN 0 */
 /* USER CODE END 0 */
 /* External variables --------------------------------------------------------*/
 extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
 extern TIM_HandleTypeDef htim8;
 extern TIM_HandleTypeDef htim17;
 /* USER CODE BEGIN EV */
 /* USER CODE END EV */
 /******************************************************************************/
 /*           Cortex-M4 Processor Interruption and Exception Handlers          */
 /******************************************************************************/
 /**
  * @brief This function handles Non maskable interrupt.
  */
 void NMI_Handler(void)
 {
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  /* USER CODE END NonMaskableInt_IRQn 1 */
 }
 /**
  * @brief This function handles Hard fault interrupt.
  */
 void HardFault_Handler(void)
 {
  /* USER CODE BEGIN HardFault_IRQn 0 */
  /* USER CODE END HardFault_IRQn 0 */
  while (1)
  {
    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
    /* USER CODE END W1_HardFault_IRQn 0 */
  }
 }
 /**
  * @brief This function handles Memory management fault.
  */
 void MemManage_Handler(void)
 {
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
  {
    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
    /* USER CODE END W1_MemoryManagement_IRQn 0 */
  }
 }
 /**
  * @brief This function handles Prefetch fault, memory access fault.
  */
 void BusFault_Handler(void)
 {
  /* USER CODE BEGIN BusFault_IRQn 0 */
  /* USER CODE END BusFault_IRQn 0 */
  while (1)
  {
    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
    /* USER CODE END W1_BusFault_IRQn 0 */
  }
 }
 /**
  * @brief This function handles Undefined instruction or illegal state.
  */
 void UsageFault_Handler(void)
 {
  /* USER CODE BEGIN UsageFault_IRQn 0 */
  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
  {
    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
    /* USER CODE END W1_UsageFault_IRQn 0 */
  }
 }
 /**
  * @brief This function handles Debug monitor.
  */
 void DebugMon_Handler(void)
 {
  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
  /* USER CODE END DebugMonitor_IRQn 1 */
 }
 /******************************************************************************/
 /* STM32L4xx Peripheral Interrupt Handlers                                    */
 /* Add here the Interrupt Handlers for the used peripherals.                  */
 /* For the available peripheral interrupt handler names,                      */
 /* please refer to the startup file (startup_stm32l4xx.s).                    */
 /******************************************************************************/
 /**
  * @brief This function handles EXTI line0 interrupt.
  */
 void EXTI0_IRQHandler(void)
 {
  /* USER CODE BEGIN EXTI0_IRQn 0 */
  /* USER CODE END EXTI0_IRQn 0 */
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
  /* USER CODE BEGIN EXTI0_IRQn 1 */
  /* USER CODE END EXTI0_IRQn 1 */
 }
 /**
  * @brief This function handles EXTI line1 interrupt.
  */
 void EXTI1_IRQHandler(void)
 {
  /* USER CODE BEGIN EXTI1_IRQn 0 */
  /* USER CODE END EXTI1_IRQn 0 */
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
  /* USER CODE BEGIN EXTI1_IRQn 1 */
  /* USER CODE END EXTI1_IRQn 1 */
 }
 /**
  * @brief This function handles EXTI line2 interrupt.
  */
 void EXTI2_IRQHandler(void)
 {
  /* USER CODE BEGIN EXTI2_IRQn 0 */
  /* USER CODE END EXTI2_IRQn 0 */
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
  /* USER CODE BEGIN EXTI2_IRQn 1 */
  /* USER CODE END EXTI2_IRQn 1 */
 }
 /**
  * @brief This function handles EXTI line4 interrupt.
  */
 void EXTI4_IRQHandler(void)
 {
  /* USER CODE BEGIN EXTI4_IRQn 0 */
  /* USER CODE END EXTI4_IRQn 0 */
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
  /* USER CODE BEGIN EXTI4_IRQn 1 */
  /* USER CODE END EXTI4_IRQn 1 */
 }
 /**
  * @brief This function handles EXTI line[9:5] interrupts.
  */
 void EXTI9_5_IRQHandler(void)
 {
  /* USER CODE BEGIN EXTI9_5_IRQn 0 */
  /* USER CODE END EXTI9_5_IRQn 0 */
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
  /* USER CODE BEGIN EXTI9_5_IRQn 1 */
  /* USER CODE END EXTI9_5_IRQn 1 */
 }
 /**
  * @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
  */
 void TIM1_TRG_COM_TIM17_IRQHandler(void)
 {
  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
  HAL_TIM_IRQHandler(&htim17);
  /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
  /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
 }
 /**
  * @brief This function handles TIM8 capture compare interrupt.
  */
 void TIM8_CC_IRQHandler(void)
 {
  /* USER CODE BEGIN TIM8_CC_IRQn 0 */
  /* USER CODE END TIM8_CC_IRQn 0 */
  HAL_TIM_IRQHandler(&htim8);
  /* USER CODE BEGIN TIM8_CC_IRQn 1 */
  /* USER CODE END TIM8_CC_IRQn 1 */
 }
 /**
  * @brief This function handles USB OTG FS global interrupt.
  */
 void OTG_FS_IRQHandler(void)
 {
  /* USER CODE BEGIN OTG_FS_IRQn 0 */
  /* USER CODE END OTG_FS_IRQn 0 */
  HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
  /* USER CODE BEGIN OTG_FS_IRQn 1 */
  /* USER CODE END OTG_FS_IRQn 1 */
 }
 /* USER CODE BEGIN 1 */
 /* USER CODE END 1 */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/target_f1/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c
+++ b/target_f1/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c
@ -69,10 +69,10 @@
  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
  *
  ******************************************************************************
  */
@ -123,7 +123,7 @@
 /*!< Uncomment the following line if you need to relocate your vector Table in
     Internal SRAM. */
 /* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+#define VECT_TAB_OFFSET  0x8000 /*!< Vector Table base offset field.
                                   This value must be a multiple of 0x200. */
 /******************************************************************************/
 /**
--- a/firmware/targets/f2/Src/tim.c
+++ b/firmware/targets/f2/Src/tim.c
@ -0,0 +1,334 @@
 /**
  ******************************************************************************
  * File Name          : TIM.c
  * Description        : This file provides code for the configuration
  *                      of the TIM instances.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* Includes ------------------------------------------------------------------*/
 #include "tim.h"
 /* USER CODE BEGIN 0 */
 /* USER CODE END 0 */
 TIM_HandleTypeDef htim5;
 TIM_HandleTypeDef htim8;
 TIM_HandleTypeDef htim15;
 /* TIM5 init function */
 void MX_TIM5_Init(void)
 {
  TIM_MasterConfigTypeDef sMasterConfig = {0};
  TIM_OC_InitTypeDef sConfigOC = {0};
  htim5.Instance = TIM5;
  htim5.Init.Prescaler = 500 - 1;
  htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
  htim5.Init.Period = 291;
  htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  if (HAL_TIM_PWM_Init(&htim5) != HAL_OK)
  {
    Error_Handler();
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
  {
    Error_Handler();
  }
  sConfigOC.OCMode = TIM_OCMODE_PWM1;
  sConfigOC.Pulse = 145;
  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
  if (HAL_TIM_PWM_ConfigChannel(&htim5, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
  {
    Error_Handler();
  }
  HAL_TIM_MspPostInit(&htim5);
 }
 /* TIM8 init function */
 void MX_TIM8_Init(void)
 {
  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
  TIM_MasterConfigTypeDef sMasterConfig = {0};
  TIM_IC_InitTypeDef sConfigIC = {0};
  htim8.Instance = TIM8;
  htim8.Init.Prescaler = 64-1;
  htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
  htim8.Init.Period = 32768-1;
  htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  htim8.Init.RepetitionCounter = 0;
  htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
  {
    Error_Handler();
  }
  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
  if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_TIM_IC_Init(&htim8) != HAL_OK)
  {
    Error_Handler();
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
  sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
  {
    Error_Handler();
  }
  sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_BOTHEDGE;
  sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
  sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
  sConfigIC.ICFilter = 0;
  if (HAL_TIM_IC_ConfigChannel(&htim8, &sConfigIC, TIM_CHANNEL_2) != HAL_OK)
  {
    Error_Handler();
  }
 }
 /* TIM15 init function */
 void MX_TIM15_Init(void)
 {
  TIM_MasterConfigTypeDef sMasterConfig = {0};
  TIM_OC_InitTypeDef sConfigOC = {0};
  TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
  htim15.Instance = TIM15;
  htim15.Init.Prescaler = 0;
  htim15.Init.CounterMode = TIM_COUNTERMODE_UP;
  htim15.Init.Period = 65535;
  htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  htim15.Init.RepetitionCounter = 0;
  htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  if (HAL_TIM_OC_Init(&htim15) != HAL_OK)
  {
    Error_Handler();
  }
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK)
  {
    Error_Handler();
  }
  sConfigOC.OCMode = TIM_OCMODE_TIMING;
  sConfigOC.Pulse = 0;
  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
  sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
  sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
  sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
  if (HAL_TIM_OC_ConfigChannel(&htim15, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
  {
    Error_Handler();
  }
  if (HAL_TIM_OC_ConfigChannel(&htim15, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
  {
    Error_Handler();
  }
  sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
  sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
  sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
  sBreakDeadTimeConfig.DeadTime = 0;
  sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
  sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
  sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
  if (HAL_TIMEx_ConfigBreakDeadTime(&htim15, &sBreakDeadTimeConfig) != HAL_OK)
  {
    Error_Handler();
  }
  HAL_TIM_MspPostInit(&htim15);
 }
 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle)
 {
  if(tim_pwmHandle->Instance==TIM5)
  {
  /* USER CODE BEGIN TIM5_MspInit 0 */
  /* USER CODE END TIM5_MspInit 0 */
    /* TIM5 clock enable */
    __HAL_RCC_TIM5_CLK_ENABLE();
  /* USER CODE BEGIN TIM5_MspInit 1 */
  /* USER CODE END TIM5_MspInit 1 */
  }
 }
 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
 {
  GPIO_InitTypeDef GPIO_InitStruct = {0};
  if(tim_baseHandle->Instance==TIM8)
  {
  /* USER CODE BEGIN TIM8_MspInit 0 */
  /* USER CODE END TIM8_MspInit 0 */
    /* TIM8 clock enable */
    __HAL_RCC_TIM8_CLK_ENABLE();
    __HAL_RCC_GPIOC_CLK_ENABLE();
    /**TIM8 GPIO Configuration
    PC7     ------> TIM8_CH2
    */
    GPIO_InitStruct.Pin = iButton_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
    GPIO_InitStruct.Alternate = GPIO_AF3_TIM8;
    HAL_GPIO_Init(iButton_GPIO_Port, &GPIO_InitStruct);
    /* TIM8 interrupt Init */
    HAL_NVIC_SetPriority(TIM8_CC_IRQn, 5, 0);
    HAL_NVIC_EnableIRQ(TIM8_CC_IRQn);
  /* USER CODE BEGIN TIM8_MspInit 1 */
  /* USER CODE END TIM8_MspInit 1 */
  }
 }
 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle)
 {
  if(tim_ocHandle->Instance==TIM15)
  {
  /* USER CODE BEGIN TIM15_MspInit 0 */
  /* USER CODE END TIM15_MspInit 0 */
    /* TIM15 clock enable */
    __HAL_RCC_TIM15_CLK_ENABLE();
  /* USER CODE BEGIN TIM15_MspInit 1 */
  /* USER CODE END TIM15_MspInit 1 */
  }
 }
 void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
 {
  GPIO_InitTypeDef GPIO_InitStruct = {0};
  if(timHandle->Instance==TIM5)
  {
  /* USER CODE BEGIN TIM5_MspPostInit 0 */
  /* USER CODE END TIM5_MspPostInit 0 */
    __HAL_RCC_GPIOA_CLK_ENABLE();
    /**TIM5 GPIO Configuration
    PA3     ------> TIM5_CH4
    */
    GPIO_InitStruct.Pin = SPEAKER_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
    GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
    HAL_GPIO_Init(SPEAKER_GPIO_Port, &GPIO_InitStruct);
  /* USER CODE BEGIN TIM5_MspPostInit 1 */
  /* USER CODE END TIM5_MspPostInit 1 */
  }
  else if(timHandle->Instance==TIM15)
  {
  /* USER CODE BEGIN TIM15_MspPostInit 0 */
  /* USER CODE END TIM15_MspPostInit 0 */
    __HAL_RCC_GPIOB_CLK_ENABLE();
    /**TIM15 GPIO Configuration
    PB13     ------> TIM15_CH1N
    PB15     ------> TIM15_CH2
    */
    GPIO_InitStruct.Pin = RFID_OUT_Pin|RFID_PULL_Pin;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
    GPIO_InitStruct.Alternate = GPIO_AF14_TIM15;
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  /* USER CODE BEGIN TIM15_MspPostInit 1 */
  /* USER CODE END TIM15_MspPostInit 1 */
  }
 }
 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* tim_pwmHandle)
 {
  if(tim_pwmHandle->Instance==TIM5)
  {
  /* USER CODE BEGIN TIM5_MspDeInit 0 */
  /* USER CODE END TIM5_MspDeInit 0 */
    /* Peripheral clock disable */
    __HAL_RCC_TIM5_CLK_DISABLE();
  /* USER CODE BEGIN TIM5_MspDeInit 1 */
  /* USER CODE END TIM5_MspDeInit 1 */
  }
 }
 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
 {
  if(tim_baseHandle->Instance==TIM8)
  {
  /* USER CODE BEGIN TIM8_MspDeInit 0 */
  /* USER CODE END TIM8_MspDeInit 0 */
    /* Peripheral clock disable */
    __HAL_RCC_TIM8_CLK_DISABLE();
    /**TIM8 GPIO Configuration
    PC7     ------> TIM8_CH2
    */
    HAL_GPIO_DeInit(iButton_GPIO_Port, iButton_Pin);
    /* TIM8 interrupt Deinit */
    HAL_NVIC_DisableIRQ(TIM8_CC_IRQn);
  /* USER CODE BEGIN TIM8_MspDeInit 1 */
  /* USER CODE END TIM8_MspDeInit 1 */
  }
 }
 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef* tim_ocHandle)
 {
  if(tim_ocHandle->Instance==TIM15)
  {
  /* USER CODE BEGIN TIM15_MspDeInit 0 */
  /* USER CODE END TIM15_MspDeInit 0 */
    /* Peripheral clock disable */
    __HAL_RCC_TIM15_CLK_DISABLE();
  /* USER CODE BEGIN TIM15_MspDeInit 1 */
  /* USER CODE END TIM15_MspDeInit 1 */
  }
 }
 /* USER CODE BEGIN 1 */
 /* USER CODE END 1 */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Src/usart.c
+++ b/firmware/targets/f2/Src/usart.c
@ -0,0 +1,108 @@
 /**
  ******************************************************************************
  * File Name          : USART.c
  * Description        : This file provides code for the configuration
  *                      of the USART instances.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* Includes ------------------------------------------------------------------*/
 #include "usart.h"
 /* USER CODE BEGIN 0 */
 /* USER CODE END 0 */
 UART_HandleTypeDef huart1;
 /* USART1 init function */
 void MX_USART1_UART_Init(void)
 {
  huart1.Instance = USART1;
  huart1.Init.BaudRate = 115200;
  huart1.Init.WordLength = UART_WORDLENGTH_8B;
  huart1.Init.StopBits = UART_STOPBITS_1;
  huart1.Init.Parity = UART_PARITY_NONE;
  huart1.Init.Mode = UART_MODE_TX_RX;
  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
  if (HAL_UART_Init(&huart1) != HAL_OK)
  {
    Error_Handler();
  }
 }
 void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
 {
  GPIO_InitTypeDef GPIO_InitStruct = {0};
  if(uartHandle->Instance==USART1)
  {
  /* USER CODE BEGIN USART1_MspInit 0 */
  /* USER CODE END USART1_MspInit 0 */
    /* USART1 clock enable */
    __HAL_RCC_USART1_CLK_ENABLE();
    __HAL_RCC_GPIOA_CLK_ENABLE();
    /**USART1 GPIO Configuration
    PA9     ------> USART1_TX
    PA10     ------> USART1_RX
    */
    GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  /* USER CODE BEGIN USART1_MspInit 1 */
  /* USER CODE END USART1_MspInit 1 */
  }
 }
 void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
 {
  if(uartHandle->Instance==USART1)
  {
  /* USER CODE BEGIN USART1_MspDeInit 0 */
  /* USER CODE END USART1_MspDeInit 0 */
    /* Peripheral clock disable */
    __HAL_RCC_USART1_CLK_DISABLE();
    /**USART1 GPIO Configuration
    PA9     ------> USART1_TX
    PA10     ------> USART1_RX
    */
    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
  /* USER CODE BEGIN USART1_MspDeInit 1 */
  /* USER CODE END USART1_MspDeInit 1 */
  }
 }
 /* USER CODE BEGIN 1 */
 /* USER CODE END 1 */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Src/usb_device.c
+++ b/firmware/targets/f2/Src/usb_device.c
@ -63,22 +63,27 @@ extern USBD_DescriptorsTypeDef FS_Desc;
  * Init USB device Library, add supported class and start the library
  * @retval None
  */
-void MX_USB_DEVICE_Init(void) {
+void MX_USB_DEVICE_Init(void)
 {
  /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */
  /* USER CODE END USB_DEVICE_Init_PreTreatment */
  /* Init Device Library, add supported class and start the library. */
-    if(USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK) {
+  if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)
  {
    Error_Handler();
  }
-    if(USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK) {
+  if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK)
  {
    Error_Handler();
  }
-    if(USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK) {
+  if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK)
  {
    Error_Handler();
  }
-    if(USBD_Start(&hUsbDeviceFS) != USBD_OK) {
+  if (USBD_Start(&hUsbDeviceFS) != USBD_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */
--- a/firmware/targets/f2/Src/usbd_cdc_if.c
+++ b/firmware/targets/f2/Src/usbd_cdc_if.c
@ -63,10 +63,6 @@
  */
 /* USER CODE BEGIN PRIVATE_DEFINES */
 /* Define size for the receive and transmit buffer over CDC */
 /* It's up to user to redefine and/or remove those define */
 #define APP_RX_DATA_SIZE 2048
 #define APP_TX_DATA_SIZE 2048
 /* USER CODE END PRIVATE_DEFINES */
 /**
@ -129,7 +125,8 @@ extern USBD_HandleTypeDef hUsbDeviceFS;
 static int8_t CDC_Init_FS(void);
 static int8_t CDC_DeInit_FS(void);
 static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length);
-static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t* Len);
+static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len);
 static int8_t CDC_TransmitCplt_FS(uint8_t *pbuf, uint32_t *Len, uint8_t epnum);
 /* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */
@ -140,14 +137,21 @@ static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t* Len);
  */
 USBD_CDC_ItfTypeDef USBD_Interface_fops_FS =
-    {CDC_Init_FS, CDC_DeInit_FS, CDC_Control_FS, CDC_Receive_FS};
+{
  CDC_Init_FS,
  CDC_DeInit_FS,
  CDC_Control_FS,
  CDC_Receive_FS,
  CDC_TransmitCplt_FS
 };
 /* Private functions ---------------------------------------------------------*/
 /**
  * @brief  Initializes the CDC media low layer over the FS USB IP
  * @retval USBD_OK if all operations are OK else USBD_FAIL
  */
-static int8_t CDC_Init_FS(void) {
+static int8_t CDC_Init_FS(void)
 {
  /* USER CODE BEGIN 3 */
  /* Set Application Buffers */
  USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0);
@ -160,7 +164,8 @@ static int8_t CDC_Init_FS(void) {
  * @brief  DeInitializes the CDC media low layer
  * @retval USBD_OK if all operations are OK else USBD_FAIL
  */
-static int8_t CDC_DeInit_FS(void) {
+static int8_t CDC_DeInit_FS(void)
 {
  /* USER CODE BEGIN 4 */
  return (USBD_OK);
  /* USER CODE END 4 */
@ -173,9 +178,11 @@ static int8_t CDC_DeInit_FS(void) {
  * @param  length: Number of data to be sent (in bytes)
  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
  */
-static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) {
+static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length)
 {
  /* USER CODE BEGIN 5 */
-    switch(cmd) {
+  switch(cmd)
  {
    case CDC_SEND_ENCAPSULATED_COMMAND:
    break;
@ -242,16 +249,18 @@ static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) {
  *         through this function.
  *
  *         @note
-  *         This function will block any OUT packet reception on USB endpoint
+  *         This function will issue a NAK packet on any OUT packet received on
-  *         untill exiting this function. If you exit this function before transfer
+  *         USB endpoint until exiting this function. If you exit this function
-  *         is complete on CDC interface (ie. using DMA controller) it will result
+  *         before transfer is complete on CDC interface (ie. using DMA controller)
-  *         in receiving more data while previous ones are still not sent.
+  *         it will result in receiving more data while previous ones are still
  *         not sent.
  *
  * @param  Buf: Buffer of data to be received
  * @param  Len: Number of data received (in bytes)
  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
  */
-static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t* Len) {
+static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len)
 {
  /* USER CODE BEGIN 6 */
  USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]);
  USBD_CDC_ReceivePacket(&hUsbDeviceFS);
@ -270,11 +279,12 @@ static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t* Len) {
  * @param  Len: Number of data to be sent (in bytes)
  * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY
  */
-uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) {
+uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len)
 {
  uint8_t result = USBD_OK;
  /* USER CODE BEGIN 7 */
-    USBD_CDC_HandleTypeDef* hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData;
+  USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData;
-    if(hcdc->TxState != 0) {
+  if (hcdc->TxState != 0){
    return USBD_BUSY;
  }
  USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len);
@ -283,6 +293,29 @@ uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) {
  return result;
 }
 /**
  * @brief  CDC_TransmitCplt_FS
  *         Data transmited callback
  *
  *         @note
  *         This function is IN transfer complete callback used to inform user that
  *         the submitted Data is successfully sent over USB.
  *
  * @param  Buf: Buffer of data to be received
  * @param  Len: Number of data received (in bytes)
  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
  */
 static int8_t CDC_TransmitCplt_FS(uint8_t *Buf, uint32_t *Len, uint8_t epnum)
 {
  uint8_t result = USBD_OK;
  /* USER CODE BEGIN 13 */
  UNUSED(Buf);
  UNUSED(Len);
  UNUSED(epnum);
  /* USER CODE END 13 */
  return result;
 }
 /* USER CODE BEGIN PRIVATE_FUNCTIONS_IMPLEMENTATION */
 /* USER CODE END PRIVATE_FUNCTIONS_IMPLEMENTATION */
--- a/firmware/targets/f2/Src/usbd_conf.c
+++ b/firmware/targets/f2/Src/usbd_conf.c
@ -0,0 +1,873 @@
 /* USER CODE BEGIN Header */
 /**
  ******************************************************************************
  * @file           : usbd_conf.c
  * @version        : v2.0_Cube
  * @brief          : This file implements the board support package for the USB device library
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* USER CODE END Header */
 /* Includes ------------------------------------------------------------------*/
 #include "stm32l4xx.h"
 #include "stm32l4xx_hal.h"
 #include "usbd_def.h"
 #include "usbd_core.h"
 #include "usbd_cdc.h"
 /* USER CODE BEGIN Includes */
 /* USER CODE END Includes */
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* USER CODE BEGIN PV */
 /* Private variables ---------------------------------------------------------*/
 /* USER CODE END PV */
 PCD_HandleTypeDef hpcd_USB_OTG_FS;
 void Error_Handler(void);
 /* USER CODE BEGIN 0 */
 /* USER CODE END 0 */
 /* Exported function prototypes ----------------------------------------------*/
 extern USBD_StatusTypeDef USBD_LL_BatteryCharging(USBD_HandleTypeDef *pdev);
 /* USER CODE BEGIN PFP */
 /* Private function prototypes -----------------------------------------------*/
 /* USER CODE END PFP */
 /* Private functions ---------------------------------------------------------*/
 /* USER CODE BEGIN 1 */
 static void SystemClockConfig_Resume(void);
 /* USER CODE END 1 */
 extern void SystemClock_Config(void);
 /*******************************************************************************
                       LL Driver Callbacks (PCD -> USB Device Library)
 *******************************************************************************/
 /* MSP Init */
 void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
 {
  GPIO_InitTypeDef GPIO_InitStruct = {0};
  if(pcdHandle->Instance==USB_OTG_FS)
  {
  /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
  /* USER CODE END USB_OTG_FS_MspInit 0 */
    __HAL_RCC_GPIOA_CLK_ENABLE();
    /**USB_OTG_FS GPIO Configuration
    PA11     ------> USB_OTG_FS_DM
    PA12     ------> USB_OTG_FS_DP
    */
    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
    /* Peripheral clock enable */
    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
    /* Enable VDDUSB */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
    {
      __HAL_RCC_PWR_CLK_ENABLE();
      HAL_PWREx_EnableVddUSB();
      __HAL_RCC_PWR_CLK_DISABLE();
    }
    else
    {
      HAL_PWREx_EnableVddUSB();
    }
    /* Peripheral interrupt init */
    HAL_NVIC_SetPriority(OTG_FS_IRQn, 5, 0);
    HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
  /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
  /* USER CODE END USB_OTG_FS_MspInit 1 */
  }
 }
 void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
 {
  if(pcdHandle->Instance==USB_OTG_FS)
  {
  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */
  /* USER CODE END USB_OTG_FS_MspDeInit 0 */
    /* Peripheral clock disable */
    __HAL_RCC_USB_OTG_FS_CLK_DISABLE();
    /**USB_OTG_FS GPIO Configuration
    PA11     ------> USB_OTG_FS_DM
    PA12     ------> USB_OTG_FS_DP
    */
    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
    /* Disable VDDUSB */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
    {
      __HAL_RCC_PWR_CLK_ENABLE();
      HAL_PWREx_DisableVddUSB();
      __HAL_RCC_PWR_CLK_DISABLE();
    }
    else
    {
      HAL_PWREx_DisableVddUSB();
    }
    /* Peripheral interrupt Deinit*/
    HAL_NVIC_DisableIRQ(OTG_FS_IRQn);
  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */
  /* USER CODE END USB_OTG_FS_MspDeInit 1 */
  }
 }
 /**
  * @brief  Setup stage callback
  * @param  hpcd: PCD handle
  * @retval None
  */
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
 static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
 #else
 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
  USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
 }
 /**
  * @brief  Data Out stage callback.
  * @param  hpcd: PCD handle
  * @param  epnum: Endpoint number
  * @retval None
  */
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
 static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 #else
 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
  USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
 }
 /**
  * @brief  Data In stage callback.
  * @param  hpcd: PCD handle
  * @param  epnum: Endpoint number
  * @retval None
  */
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
 static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 #else
 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
  USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
 }
 /**
  * @brief  SOF callback.
  * @param  hpcd: PCD handle
  * @retval None
  */
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
 static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
 #else
 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
  USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
 }
 /**
  * @brief  Reset callback.
  * @param  hpcd: PCD handle
  * @retval None
  */
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
 static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
 #else
 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
  USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
  if ( hpcd->Init.speed != PCD_SPEED_FULL)
  {
    Error_Handler();
  }
    /* Set Speed. */
  USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);
  /* Reset Device. */
  USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);
 }
 /**
  * @brief  Suspend callback.
  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
  * @param  hpcd: PCD handle
  * @retval None
  */
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
 static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
 #else
 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
  __HAL_PCD_GATE_PHYCLOCK(hpcd);
  /* Inform USB library that core enters in suspend Mode. */
  USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);
  /* Enter in STOP mode. */
  /* USER CODE BEGIN 2 */
  if (hpcd->Init.low_power_enable)
  {
    /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
    SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
  }
  /* USER CODE END 2 */
 }
 /**
  * @brief  Resume callback.
  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)
  * @param  hpcd: PCD handle
  * @retval None
  */
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
 static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
 #else
 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
  __HAL_PCD_UNGATE_PHYCLOCK(hpcd);
  /* USER CODE BEGIN 3 */
  if (hpcd->Init.low_power_enable)
  {
    /* Reset SLEEPDEEP bit of Cortex System Control Register. */
    SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
    SystemClockConfig_Resume();
  }
  /* USER CODE END 3 */
  USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);
 }
 /**
  * @brief  ISOOUTIncomplete callback.
  * @param  hpcd: PCD handle
  * @param  epnum: Endpoint number
  * @retval None
  */
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
 static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 #else
 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
  USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
 }
 /**
  * @brief  ISOINIncomplete callback.
  * @param  hpcd: PCD handle
  * @param  epnum: Endpoint number
  * @retval None
  */
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
 static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 #else
 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
  USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
 }
 /**
  * @brief  Connect callback.
  * @param  hpcd: PCD handle
  * @retval None
  */
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
 static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
 #else
 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
  USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
 }
 /**
  * @brief  Disconnect callback.
  * @param  hpcd: PCD handle
  * @retval None
  */
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
 static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
 #else
 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 {
  USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
 }
 /*******************************************************************************
                       LL Driver Interface (USB Device Library --> PCD)
 *******************************************************************************/
 /**
  * @brief  Initializes the low level portion of the device driver.
  * @param  pdev: Device handle
  * @retval USBD status
  */
 USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
 {
  /* Init USB Ip. */
  if (pdev->id == DEVICE_FS) {
  /* Enable USB power on Pwrctrl CR2 register. */
  /* Link the driver to the stack. */
  hpcd_USB_OTG_FS.pData = pdev;
  pdev->pData = &hpcd_USB_OTG_FS;
  hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
  hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
  hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
  hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
  hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
  hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
  hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
  hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;
  hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
  hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
  if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
  {
    Error_Handler( );
  }
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
  /* Register USB PCD CallBacks */
  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback);
  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback);
  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback);
  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback);
  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback);
  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback);
  HAL_PCD_RegisterCallback(&hpcd_USB_OTG_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback);
  HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_OTG_FS, PCD_DataOutStageCallback);
  HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_OTG_FS, PCD_DataInStageCallback);
  HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
  HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
  HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
  }
  return USBD_OK;
 }
 /**
  * @brief  De-Initializes the low level portion of the device driver.
  * @param  pdev: Device handle
  * @retval USBD status
  */
 USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
 {
  HAL_StatusTypeDef hal_status = HAL_OK;
  USBD_StatusTypeDef usb_status = USBD_OK;
  hal_status = HAL_PCD_DeInit(pdev->pData);
  switch (hal_status) {
    case HAL_OK :
      usb_status = USBD_OK;
    break;
    case HAL_ERROR :
      usb_status = USBD_FAIL;
    break;
    case HAL_BUSY :
      usb_status = USBD_BUSY;
    break;
    case HAL_TIMEOUT :
      usb_status = USBD_FAIL;
    break;
    default :
      usb_status = USBD_FAIL;
    break;
  }
  return usb_status;
 }
 /**
  * @brief  Starts the low level portion of the device driver.
  * @param  pdev: Device handle
  * @retval USBD status
  */
 USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
 {
  HAL_StatusTypeDef hal_status = HAL_OK;
  USBD_StatusTypeDef usb_status = USBD_OK;
  hal_status = HAL_PCD_Start(pdev->pData);
  switch (hal_status) {
    case HAL_OK :
      usb_status = USBD_OK;
    break;
    case HAL_ERROR :
      usb_status = USBD_FAIL;
    break;
    case HAL_BUSY :
      usb_status = USBD_BUSY;
    break;
    case HAL_TIMEOUT :
      usb_status = USBD_FAIL;
    break;
    default :
      usb_status = USBD_FAIL;
    break;
  }
  return usb_status;
 }
 /**
  * @brief  Stops the low level portion of the device driver.
  * @param  pdev: Device handle
  * @retval USBD status
  */
 USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
 {
  HAL_StatusTypeDef hal_status = HAL_OK;
  USBD_StatusTypeDef usb_status = USBD_OK;
  hal_status = HAL_PCD_Stop(pdev->pData);
  switch (hal_status) {
    case HAL_OK :
      usb_status = USBD_OK;
    break;
    case HAL_ERROR :
      usb_status = USBD_FAIL;
    break;
    case HAL_BUSY :
      usb_status = USBD_BUSY;
    break;
    case HAL_TIMEOUT :
      usb_status = USBD_FAIL;
    break;
    default :
      usb_status = USBD_FAIL;
    break;
  }
  return usb_status;
 }
 /**
  * @brief  Opens an endpoint of the low level driver.
  * @param  pdev: Device handle
  * @param  ep_addr: Endpoint number
  * @param  ep_type: Endpoint type
  * @param  ep_mps: Endpoint max packet size
  * @retval USBD status
  */
 USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)
 {
  HAL_StatusTypeDef hal_status = HAL_OK;
  USBD_StatusTypeDef usb_status = USBD_OK;
  hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
  switch (hal_status) {
    case HAL_OK :
      usb_status = USBD_OK;
    break;
    case HAL_ERROR :
      usb_status = USBD_FAIL;
    break;
    case HAL_BUSY :
      usb_status = USBD_BUSY;
    break;
    case HAL_TIMEOUT :
      usb_status = USBD_FAIL;
    break;
    default :
      usb_status = USBD_FAIL;
    break;
  }
  return usb_status;
 }
 /**
  * @brief  Closes an endpoint of the low level driver.
  * @param  pdev: Device handle
  * @param  ep_addr: Endpoint number
  * @retval USBD status
  */
 USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
 {
  HAL_StatusTypeDef hal_status = HAL_OK;
  USBD_StatusTypeDef usb_status = USBD_OK;
  hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
  switch (hal_status) {
    case HAL_OK :
      usb_status = USBD_OK;
    break;
    case HAL_ERROR :
      usb_status = USBD_FAIL;
    break;
    case HAL_BUSY :
      usb_status = USBD_BUSY;
    break;
    case HAL_TIMEOUT :
      usb_status = USBD_FAIL;
    break;
    default :
      usb_status = USBD_FAIL;
    break;
  }
  return usb_status;
 }
 /**
  * @brief  Flushes an endpoint of the Low Level Driver.
  * @param  pdev: Device handle
  * @param  ep_addr: Endpoint number
  * @retval USBD status
  */
 USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
 {
  HAL_StatusTypeDef hal_status = HAL_OK;
  USBD_StatusTypeDef usb_status = USBD_OK;
  hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr);
  switch (hal_status) {
    case HAL_OK :
      usb_status = USBD_OK;
    break;
    case HAL_ERROR :
      usb_status = USBD_FAIL;
    break;
    case HAL_BUSY :
      usb_status = USBD_BUSY;
    break;
    case HAL_TIMEOUT :
      usb_status = USBD_FAIL;
    break;
    default :
      usb_status = USBD_FAIL;
    break;
  }
  return usb_status;
 }
 /**
  * @brief  Sets a Stall condition on an endpoint of the Low Level Driver.
  * @param  pdev: Device handle
  * @param  ep_addr: Endpoint number
  * @retval USBD status
  */
 USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
 {
  HAL_StatusTypeDef hal_status = HAL_OK;
  USBD_StatusTypeDef usb_status = USBD_OK;
  hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
  switch (hal_status) {
    case HAL_OK :
      usb_status = USBD_OK;
    break;
    case HAL_ERROR :
      usb_status = USBD_FAIL;
    break;
    case HAL_BUSY :
      usb_status = USBD_BUSY;
    break;
    case HAL_TIMEOUT :
      usb_status = USBD_FAIL;
    break;
    default :
      usb_status = USBD_FAIL;
    break;
  }
  return usb_status;
 }
 /**
  * @brief  Clears a Stall condition on an endpoint of the Low Level Driver.
  * @param  pdev: Device handle
  * @param  ep_addr: Endpoint number
  * @retval USBD status
  */
 USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
 {
  HAL_StatusTypeDef hal_status = HAL_OK;
  USBD_StatusTypeDef usb_status = USBD_OK;
  hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
  switch (hal_status) {
    case HAL_OK :
      usb_status = USBD_OK;
    break;
    case HAL_ERROR :
      usb_status = USBD_FAIL;
    break;
    case HAL_BUSY :
      usb_status = USBD_BUSY;
    break;
    case HAL_TIMEOUT :
      usb_status = USBD_FAIL;
    break;
    default :
      usb_status = USBD_FAIL;
    break;
  }
  return usb_status;
 }
 /**
  * @brief  Returns Stall condition.
  * @param  pdev: Device handle
  * @param  ep_addr: Endpoint number
  * @retval Stall (1: Yes, 0: No)
  */
 uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
 {
  PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;
  if((ep_addr & 0x80) == 0x80)
  {
    return hpcd->IN_ep[ep_addr & 0x7F].is_stall;
  }
  else
  {
    return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;
  }
 }
 /**
  * @brief  Assigns a USB address to the device.
  * @param  pdev: Device handle
  * @param  dev_addr: Device address
  * @retval USBD status
  */
 USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)
 {
  HAL_StatusTypeDef hal_status = HAL_OK;
  USBD_StatusTypeDef usb_status = USBD_OK;
  hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
  switch (hal_status) {
    case HAL_OK :
      usb_status = USBD_OK;
    break;
    case HAL_ERROR :
      usb_status = USBD_FAIL;
    break;
    case HAL_BUSY :
      usb_status = USBD_BUSY;
    break;
    case HAL_TIMEOUT :
      usb_status = USBD_FAIL;
    break;
    default :
      usb_status = USBD_FAIL;
    break;
  }
  return usb_status;
 }
 /**
  * @brief  Transmits data over an endpoint.
  * @param  pdev: Device handle
  * @param  ep_addr: Endpoint number
  * @param  pbuf: Pointer to data to be sent
  * @param  size: Data size
  * @retval USBD status
  */
 USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
 {
  HAL_StatusTypeDef hal_status = HAL_OK;
  USBD_StatusTypeDef usb_status = USBD_OK;
  hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
  switch (hal_status) {
    case HAL_OK :
      usb_status = USBD_OK;
    break;
    case HAL_ERROR :
      usb_status = USBD_FAIL;
    break;
    case HAL_BUSY :
      usb_status = USBD_BUSY;
    break;
    case HAL_TIMEOUT :
      usb_status = USBD_FAIL;
    break;
    default :
      usb_status = USBD_FAIL;
    break;
  }
  return usb_status;
 }
 /**
  * @brief  Prepares an endpoint for reception.
  * @param  pdev: Device handle
  * @param  ep_addr: Endpoint number
  * @param  pbuf: Pointer to data to be received
  * @param  size: Data size
  * @retval USBD status
  */
 USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t size)
 {
  HAL_StatusTypeDef hal_status = HAL_OK;
  USBD_StatusTypeDef usb_status = USBD_OK;
  hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
  switch (hal_status) {
    case HAL_OK :
      usb_status = USBD_OK;
    break;
    case HAL_ERROR :
      usb_status = USBD_FAIL;
    break;
    case HAL_BUSY :
      usb_status = USBD_BUSY;
    break;
    case HAL_TIMEOUT :
      usb_status = USBD_FAIL;
    break;
    default :
      usb_status = USBD_FAIL;
    break;
  }
  return usb_status;
 }
 /**
  * @brief  Returns the last transfered packet size.
  * @param  pdev: Device handle
  * @param  ep_addr: Endpoint number
  * @retval Recived Data Size
  */
 uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
 {
  return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);
 }
 /**
  * @brief  Send LPM message to user layer
  * @param  hpcd: PCD handle
  * @param  msg: LPM message
  * @retval None
  */
 void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
 {
  switch (msg)
  {
  case PCD_LPM_L0_ACTIVE:
    if (hpcd->Init.low_power_enable)
    {
      SystemClockConfig_Resume();
      /* Reset SLEEPDEEP bit of Cortex System Control Register. */
      SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
    }
    __HAL_PCD_UNGATE_PHYCLOCK(hpcd);
    USBD_LL_Resume(hpcd->pData);
    break;
  case PCD_LPM_L1_ACTIVE:
    __HAL_PCD_GATE_PHYCLOCK(hpcd);
    USBD_LL_Suspend(hpcd->pData);
    /* Enter in STOP mode. */
    if (hpcd->Init.low_power_enable)
    {
      /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */
      SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
    }
    break;
  }
 }
 /**
  * @brief  Delays routine for the USB Device Library.
  * @param  Delay: Delay in ms
  * @retval None
  */
 void USBD_LL_Delay(uint32_t Delay)
 {
  HAL_Delay(Delay);
 }
 /**
  * @brief  Static single allocation.
  * @param  size: Size of allocated memory
  * @retval None
  */
 void *USBD_static_malloc(uint32_t size)
 {
  static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */
  return mem;
 }
 /**
  * @brief  Dummy memory free
  * @param  p: Pointer to allocated  memory address
  * @retval None
  */
 void USBD_static_free(void *p)
 {
 }
 /* USER CODE BEGIN 5 */
 /**
  * @brief  Configures system clock after wake-up from USB resume callBack:
  *         enable HSI, PLL and select PLL as system clock source.
  * @retval None
  */
 static void SystemClockConfig_Resume(void)
 {
  SystemClock_Config();
 }
 /* USER CODE END 5 */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/Src/usbd_desc.c
+++ b/firmware/targets/f2/Src/usbd_desc.c
@ -0,0 +1,445 @@
 /* USER CODE BEGIN Header */
 /**
  ******************************************************************************
  * @file           : usbd_desc.c
  * @version        : v2.0_Cube
  * @brief          : This file implements the USB device descriptors.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under Ultimate Liberty license
  * SLA0044, the "License"; You may not use this file except in compliance with
  * the License. You may obtain a copy of the License at:
  *                             www.st.com/SLA0044
  *
  ******************************************************************************
  */
 /* USER CODE END Header */
 /* Includes ------------------------------------------------------------------*/
 #include "usbd_core.h"
 #include "usbd_desc.h"
 #include "usbd_conf.h"
 /* USER CODE BEGIN INCLUDE */
 /* USER CODE END INCLUDE */
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 /* USER CODE BEGIN PV */
 /* Private variables ---------------------------------------------------------*/
 /* USER CODE END PV */
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
  * @{
  */
 /** @addtogroup USBD_DESC
  * @{
  */
 /** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions
  * @brief Private types.
  * @{
  */
 /* USER CODE BEGIN PRIVATE_TYPES */
 /* USER CODE END PRIVATE_TYPES */
 /**
  * @}
  */
 /** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines
  * @brief Private defines.
  * @{
  */
 #define USBD_VID     1155
 #define USBD_LANGID_STRING     1033
 #define USBD_MANUFACTURER_STRING     "STMicroelectronics"
 #define USBD_PID_FS     22336
 #define USBD_PRODUCT_STRING_FS     "STM32 Virtual ComPort"
 #define USBD_CONFIGURATION_STRING_FS     "CDC Config"
 #define USBD_INTERFACE_STRING_FS     "CDC Interface"
 #define USB_SIZ_BOS_DESC            0x0C
 /* USER CODE BEGIN PRIVATE_DEFINES */
 /* USER CODE END PRIVATE_DEFINES */
 /**
  * @}
  */
 /* USER CODE BEGIN 0 */
 /* USER CODE END 0 */
 /** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros
  * @brief Private macros.
  * @{
  */
 /* USER CODE BEGIN PRIVATE_MACRO */
 /* USER CODE END PRIVATE_MACRO */
 /**
  * @}
  */
 /** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
  * @brief Private functions declaration.
  * @{
  */
 static void Get_SerialNum(void);
 static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len);
 /**
  * @}
  */
 /** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
  * @brief Private functions declaration for FS.
  * @{
  */
 uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
 uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
 uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
 uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
 uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
 uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
 uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
 #if (USBD_LPM_ENABLED == 1)
 uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
 #endif /* (USBD_LPM_ENABLED == 1) */
 /**
  * @}
  */
 /** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
  * @brief Private variables.
  * @{
  */
 USBD_DescriptorsTypeDef FS_Desc =
 {
  USBD_FS_DeviceDescriptor
 , USBD_FS_LangIDStrDescriptor
 , USBD_FS_ManufacturerStrDescriptor
 , USBD_FS_ProductStrDescriptor
 , USBD_FS_SerialStrDescriptor
 , USBD_FS_ConfigStrDescriptor
 , USBD_FS_InterfaceStrDescriptor
 #if (USBD_LPM_ENABLED == 1)
 , USBD_FS_USR_BOSDescriptor
 #endif /* (USBD_LPM_ENABLED == 1) */
 };
 #if defined ( __ICCARM__ ) /* IAR Compiler */
  #pragma data_alignment=4
 #endif /* defined ( __ICCARM__ ) */
 /** USB standard device descriptor. */
 __ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END =
 {
  0x12,                       /*bLength */
  USB_DESC_TYPE_DEVICE,       /*bDescriptorType*/
 #if (USBD_LPM_ENABLED == 1)
  0x01,                       /*bcdUSB */ /* changed to USB version 2.01
                                             in order to support LPM L1 suspend
                                             resume test of USBCV3.0*/
 #else
  0x00,                       /*bcdUSB */
 #endif /* (USBD_LPM_ENABLED == 1) */
  0x02,
  0x02,                       /*bDeviceClass*/
  0x02,                       /*bDeviceSubClass*/
  0x00,                       /*bDeviceProtocol*/
  USB_MAX_EP0_SIZE,           /*bMaxPacketSize*/
  LOBYTE(USBD_VID),           /*idVendor*/
  HIBYTE(USBD_VID),           /*idVendor*/
  LOBYTE(USBD_PID_FS),        /*idProduct*/
  HIBYTE(USBD_PID_FS),        /*idProduct*/
  0x00,                       /*bcdDevice rel. 2.00*/
  0x02,
  USBD_IDX_MFC_STR,           /*Index of manufacturer  string*/
  USBD_IDX_PRODUCT_STR,       /*Index of product string*/
  USBD_IDX_SERIAL_STR,        /*Index of serial number string*/
  USBD_MAX_NUM_CONFIGURATION  /*bNumConfigurations*/
 };
 /* USB_DeviceDescriptor */
 /** BOS descriptor. */
 #if (USBD_LPM_ENABLED == 1)
 #if defined ( __ICCARM__ ) /* IAR Compiler */
  #pragma data_alignment=4
 #endif /* defined ( __ICCARM__ ) */
 __ALIGN_BEGIN uint8_t USBD_FS_BOSDesc[USB_SIZ_BOS_DESC] __ALIGN_END =
 {
  0x5,
  USB_DESC_TYPE_BOS,
  0xC,
  0x0,
  0x1,  /* 1 device capability*/
        /* device capability*/
  0x7,
  USB_DEVICE_CAPABITY_TYPE,
  0x2,
  0x2,  /* LPM capability bit set*/
  0x0,
  0x0,
  0x0
 };
 #endif /* (USBD_LPM_ENABLED == 1) */
 /**
  * @}
  */
 /** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables
  * @brief Private variables.
  * @{
  */
 #if defined ( __ICCARM__ ) /* IAR Compiler */
  #pragma data_alignment=4
 #endif /* defined ( __ICCARM__ ) */
 /** USB lang indentifier descriptor. */
 __ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END =
 {
     USB_LEN_LANGID_STR_DESC,
     USB_DESC_TYPE_STRING,
     LOBYTE(USBD_LANGID_STRING),
     HIBYTE(USBD_LANGID_STRING)
 };
 #if defined ( __ICCARM__ ) /* IAR Compiler */
  #pragma data_alignment=4
 #endif /* defined ( __ICCARM__ ) */
 /* Internal string descriptor. */
 __ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
 #if defined ( __ICCARM__ ) /*!< IAR Compiler */
  #pragma data_alignment=4
 #endif
 __ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = {
  USB_SIZ_STRING_SERIAL,
  USB_DESC_TYPE_STRING,
 };
 /**
  * @}
  */
 /** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions
  * @brief Private functions.
  * @{
  */
 /**
  * @brief  Return the device descriptor
  * @param  speed : Current device speed
  * @param  length : Pointer to data length variable
  * @retval Pointer to descriptor buffer
  */
 uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
 {
  UNUSED(speed);
  *length = sizeof(USBD_FS_DeviceDesc);
  return USBD_FS_DeviceDesc;
 }
 /**
  * @brief  Return the LangID string descriptor
  * @param  speed : Current device speed
  * @param  length : Pointer to data length variable
  * @retval Pointer to descriptor buffer
  */
 uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
 {
  UNUSED(speed);
  *length = sizeof(USBD_LangIDDesc);
  return USBD_LangIDDesc;
 }
 /**
  * @brief  Return the product string descriptor
  * @param  speed : Current device speed
  * @param  length : Pointer to data length variable
  * @retval Pointer to descriptor buffer
  */
 uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
 {
  if(speed == 0)
  {
    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
  }
  else
  {
    USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length);
  }
  return USBD_StrDesc;
 }
 /**
  * @brief  Return the manufacturer string descriptor
  * @param  speed : Current device speed
  * @param  length : Pointer to data length variable
  * @retval Pointer to descriptor buffer
  */
 uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
 {
  UNUSED(speed);
  USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
  return USBD_StrDesc;
 }
 /**
  * @brief  Return the serial number string descriptor
  * @param  speed : Current device speed
  * @param  length : Pointer to data length variable
  * @retval Pointer to descriptor buffer
  */
 uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
 {
  UNUSED(speed);
  *length = USB_SIZ_STRING_SERIAL;
  /* Update the serial number string descriptor with the data from the unique
   * ID */
  Get_SerialNum();
  /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
  /* USER CODE END USBD_FS_SerialStrDescriptor */
  return (uint8_t *) USBD_StringSerial;
 }
 /**
  * @brief  Return the configuration string descriptor
  * @param  speed : Current device speed
  * @param  length : Pointer to data length variable
  * @retval Pointer to descriptor buffer
  */
 uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
 {
  if(speed == USBD_SPEED_HIGH)
  {
    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
  }
  else
  {
    USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);
  }
  return USBD_StrDesc;
 }
 /**
  * @brief  Return the interface string descriptor
  * @param  speed : Current device speed
  * @param  length : Pointer to data length variable
  * @retval Pointer to descriptor buffer
  */
 uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
 {
  if(speed == 0)
  {
    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
  }
  else
  {
    USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);
  }
  return USBD_StrDesc;
 }
 #if (USBD_LPM_ENABLED == 1)
 /**
  * @brief  Return the BOS descriptor
  * @param  speed : Current device speed
  * @param  length : Pointer to data length variable
  * @retval Pointer to descriptor buffer
  */
 uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
 {
  UNUSED(speed);
  *length = sizeof(USBD_FS_BOSDesc);
  return (uint8_t*)USBD_FS_BOSDesc;
 }
 #endif /* (USBD_LPM_ENABLED == 1) */
 /**
  * @brief  Create the serial number string descriptor
  * @param  None
  * @retval None
  */
 static void Get_SerialNum(void)
 {
  uint32_t deviceserial0, deviceserial1, deviceserial2;
  deviceserial0 = *(uint32_t *) DEVICE_ID1;
  deviceserial1 = *(uint32_t *) DEVICE_ID2;
  deviceserial2 = *(uint32_t *) DEVICE_ID3;
  deviceserial0 += deviceserial2;
  if (deviceserial0 != 0)
  {
    IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
    IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
  }
 }
 /**
  * @brief  Convert Hex 32Bits value into char
  * @param  value: value to convert
  * @param  pbuf: pointer to the buffer
  * @param  len: buffer length
  * @retval None
  */
 static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
 {
  uint8_t idx = 0;
  for (idx = 0; idx < len; idx++)
  {
    if (((value >> 28)) < 0xA)
    {
      pbuf[2 * idx] = (value >> 28) + '0';
    }
    else
    {
      pbuf[2 * idx] = (value >> 28) + 'A' - 10;
    }
    value = value << 4;
    pbuf[2 * idx + 1] = 0;
  }
 }
 /**
  * @}
  */
 /**
  * @}
  */
 /**
  * @}
  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/firmware/targets/f2/cube.ioc
+++ b/firmware/targets/f2/cube.ioc
@ -1,491 +1,488 @@
 #MicroXplorer Configuration settings - do not modify
-ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_4
+PB13.GPIOParameters=GPIO_Label
-ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,master,NbrOfConversion
+PC7.GPIOParameters=GPIO_ModeDefaultPP,GPIO_Speed,GPIO_PuPd,GPIO_Label
-ADC1.NbrOfConversion=1
+PA15\ (JTDI).GPIOParameters=GPIO_Label
-ADC1.NbrOfConversionFlag=1
+RCC.USART1Freq_Value=64000000
-ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
+TIM8.ICPolarity_CH2=TIM_INPUTCHANNELPOLARITY_BOTHEDGE
-ADC1.Rank-0\#ChannelRegularConversion=1
+SPI3.Direction=SPI_DIRECTION_2LINES
 SPI3.VirtualType=VM_MASTER
 SPI1.VirtualType=VM_MASTER
 VP_ADC1_TempSens_Input.Mode=IN-TempSens
 PC12.Locked=true
 SH.GPXTI9.0=GPIO_EXTI9
 PC12.Signal=SPI3_MOSI
 PB14.GPIO_Label=LED_GREEN
 PC7.Locked=true
 PA13\ (JTMS-SWDIO).Locked=true
 PC6.GPIO_Label=VIBRO
 PC3.Locked=true
 PA3.GPIOParameters=GPIO_Label
 PB6.GPIO_Label=DISPLAY_BACKLIGHT
 PA15\ (JTDI).Signal=GPIO_Output
 PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator
 PC5.Mode=INP
 USART1.IPParameters=VirtualMode-Asynchronous
 PB13.Signal=TIM15_CH1N
 VP_TIM8_VS_ClockSourceINT.Signal=TIM8_VS_ClockSourceINT
 PA2.GPIOParameters=GPIO_Label
 PinOutPanel.RotationAngle=0
 RCC.MCO1PinFreq_Value=64000000
 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
 TIM15.Channel-Output\ Compare1\ CH1N=TIM_CHANNEL_1
 PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator
 SH.GPXTI13.0=GPIO_EXTI13
 PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK
 RCC.LPTIM1Freq_Value=64000000
 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
 NVIC.EXTI1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
 RCC.ADCCLockSelection=RCC_ADCCLKSOURCE_SYSCLK
 SPI1.Direction=SPI_DIRECTION_2LINES
 RCC.APB2TimFreq_Value=64000000
 PB6.Signal=GPIO_Output
 PC7.Signal=S_TIM8_CH2
 SPI1.CalculateBaudRate=4.0 MBits/s
 PC3.Signal=ADCx_IN4
 RCC.SAI2Freq_Value=13714285.714285715
 PA1.GPIO_PuPd=GPIO_PULLDOWN
 RCC.PREFETCH_ENABLE=1
 PB13.Locked=true
 RCC.USART3Freq_Value=64000000
 ProjectManager.ProjectBuild=false
 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 PA0.Locked=true
 PB2.Signal=GPIO_Analog
 PA8.Locked=true
 PA4.Locked=true
 ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.16.0
 VP_ADC1_Vref_Input.Mode=IN-Vrefint
 MxDb.Version=DB.6.0.0
 PB0.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
 PA1.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
 ProjectManager.BackupPrevious=false
 VP_SYS_VS_tim17.Signal=SYS_VS_tim17
 PC4.GPIO_Label=NFC_CS
 PB1.GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM
 FREERTOS.HEAP_NUMBER=4
 PB1.GPIO_Label=LED_BLUE
 SPI1.DataSize=SPI_DATASIZE_8BIT
 PC7.GPIO_ModeDefaultPP=GPIO_MODE_AF_OD
 PA8.Signal=GPIO_Output
 PA8.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
 RCC.PLLRCLKFreq_Value=64000000
 SH.ADCx_IN4.ConfNb=1
 PB6.Locked=true
 NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
 ProjectManager.HalAssertFull=false
 ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
-ADC1.master=1
+PA0.Signal=ADCx_IN5
-FREERTOS.HEAP_NUMBER=1
+PC8.GPIOParameters=GPIO_Label
 FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE,HEAP_NUMBER,configUSE_TIMERS,configUSE_IDLE_HOOK
 FREERTOS.Tasks01=defaultTask,0,1024,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL
 FREERTOS.configTOTAL_HEAP_SIZE=8192
 FREERTOS.configUSE_IDLE_HOOK=1
 FREERTOS.configUSE_TIMERS=1
 File.Version=6
 KeepUserPlacement=false
 Mcu.Family=STM32L4
 Mcu.IP0=ADC1
 Mcu.IP1=COMP1
 Mcu.IP10=TIM15
 Mcu.IP11=USART1
 Mcu.IP12=USB_DEVICE
 Mcu.IP13=USB_OTG_FS
 Mcu.IP2=FREERTOS
 Mcu.IP3=NVIC
 Mcu.IP4=RCC
 Mcu.IP5=SPI1
 Mcu.IP6=SPI3
 Mcu.IP7=SYS
 Mcu.IP8=TIM5
 Mcu.IP9=TIM8
 Mcu.IPNb=14
 Mcu.Name=STM32L476R(C-E-G)Tx
 Mcu.Package=LQFP64
-Mcu.Pin0=PC13
+PB9.Signal=GPXTI9
-Mcu.Pin1=PC14-OSC32_IN (PC14)
+PB1.Signal=GPIO_Output
-Mcu.Pin10=PA1
+PA5.Locked=true
-Mcu.Pin11=PA2
+NVIC.TimeBase=TIM1_TRG_COM_TIM17_IRQn
-Mcu.Pin12=PA3
+SPI3.Mode=SPI_MODE_MASTER
-Mcu.Pin13=PA4
+SH.GPXTI8.0=GPIO_EXTI8
-Mcu.Pin14=PA5
+SH.GPXTI8.ConfNb=1
-Mcu.Pin15=PA6
+NVIC.TimeBaseIP=TIM17
-Mcu.Pin16=PA7
+RCC.LSCOPinFreq_Value=32000
-Mcu.Pin17=PC4
+PA10.Signal=USART1_RX
-Mcu.Pin18=PC5
+PB9.GPIO_PuPd=GPIO_PULLDOWN
-Mcu.Pin19=PB0
+FREERTOS.FootprintOK=true
-Mcu.Pin2=PC15-OSC32_OUT (PC15)
+RCC.DFSDMFreq_Value=64000000
-Mcu.Pin20=PB1
+PC11.Mode=Full_Duplex_Master
-Mcu.Pin21=PB2
+PB14.GPIOParameters=GPIO_Speed,PinState,GPIO_Label,GPIO_ModeDefaultOutputPP
-Mcu.Pin22=PB10
+NVIC.EXTI2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
-Mcu.Pin23=PB11
+RCC.PLLPoutputFreq_Value=18285714.285714287
-Mcu.Pin24=PB12
+RCC.APB1TimFreq_Value=64000000
-Mcu.Pin25=PB13
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
-Mcu.Pin26=PB14
+RCC.LPUART1Freq_Value=64000000
-Mcu.Pin27=PB15
+USB_OTG_FS.IPParameters=VirtualMode
-Mcu.Pin28=PC6
+PB13.Mode=Output Compare1 CH1N
-Mcu.Pin29=PC7
+PB10.GPIOParameters=GPIO_Label
-Mcu.Pin3=PH0-OSC_IN (PH0)
+PA13\ (JTMS-SWDIO).Signal=SYS_JTMS-SWDIO
-Mcu.Pin30=PC8
+PA13\ (JTMS-SWDIO).GPIOParameters=GPIO_Label
-Mcu.Pin31=PC9
+PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
-Mcu.Pin32=PA8
+PA8.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
-Mcu.Pin33=PA9
+ProjectManager.CustomerFirmwarePackage=../../../lib/STM32CubeL4
-Mcu.Pin34=PA10
+PC4.GPIOParameters=GPIO_Label
-Mcu.Pin35=PA11
+PC2.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
-Mcu.Pin36=PA12
+NVIC.EXTI4_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
-Mcu.Pin37=PA13 (JTMS-SWDIO)
+RCC.PLLQoutputFreq_Value=64000000
-Mcu.Pin38=PA14 (JTCK-SWCLK)
+ProjectManager.ProjectFileName=cube.ioc
-Mcu.Pin39=PA15 (JTDI)
+FREERTOS.Tasks01=defaultTask,24,1024,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;app_main,8,128,app,As external,NULL,Dynamic,NULL,NULL
-Mcu.Pin4=PH1-OSC_OUT (PH1)
+ADC1.Rank-0\#ChannelRegularConversion=1
-Mcu.Pin40=PC10
+TIM5.IPParameters=Prescaler,Period,Channel-PWM Generation4 CH4,Pulse-PWM Generation4 CH4
-Mcu.Pin41=PC11
+Mcu.PinsNb=58
-Mcu.Pin42=PC12
+PC11.Locked=true
-Mcu.Pin43=PD2
+VP_SYS_VS_tim17.Mode=TIM17
-Mcu.Pin44=PB3 (JTDO-TRACESWO)
+ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,master,NbrOfConversion
-Mcu.Pin45=PB4 (NJTRST)
+PC13.Locked=true
-Mcu.Pin46=PB5
+ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
-Mcu.Pin47=PB6
+PC13.Signal=GPXTI13
-Mcu.Pin48=PB7
+RCC.SWPMI1Freq_Value=64000000
-Mcu.Pin49=PB8
+PB8.GPIO_PuPd=GPIO_PULLDOWN
-Mcu.Pin5=PC0
+PC6.Signal=GPIO_Output
-Mcu.Pin50=PB9
+PC2.Signal=GPXTI2
 PB11.GPIO_Label=IR_TX
 SH.GPXTI0.ConfNb=1
 SPI1.CLKPhase=SPI_PHASE_1EDGE
 PC0.Signal=GPIO_Analog
 PB14.Locked=true
 SH.S_TIM8_CH2.0=TIM8_CH2,Input_Capture2_from_TI2
 PC3.GPIOParameters=GPIO_Label
 PB8.GPIO_Label=BUTTON_RIGHT
 PA11.Locked=true
 PA8.GPIO_Label=LED_RED
 SH.GPXTI2.ConfNb=1
 Mcu.Pin57=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS
 PB14.GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM
 Mcu.Pin51=VP_ADC1_TempSens_Input
 Mcu.Pin52=VP_ADC1_Vref_Input
-Mcu.Pin53=VP_COMP1_VS_VREFINT12
+Mcu.Pin50=PB9
-Mcu.Pin54=VP_FREERTOS_VS_CMSIS_V1
+Mcu.Pin55=VP_SYS_VS_tim17
 Mcu.Pin55=VP_SYS_VS_Systick
 Mcu.Pin56=VP_TIM8_VS_ClockSourceINT
-Mcu.Pin57=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS
+Mcu.Pin53=VP_COMP1_VS_VREFINT12
 Mcu.Pin54=VP_FREERTOS_VS_CMSIS_V2
 PC6.Locked=true
 PA9.Signal=USART1_TX
 PB11.GPIOParameters=GPIO_Label
 PB5.Locked=true
 PB9.Locked=true
 VP_TIM8_VS_ClockSourceINT.Mode=Internal
 PC7.GPIO_PuPd=GPIO_NOPULL
 Mcu.Pin48=PB7
 Mcu.Pin49=PB8
 RCC.PLLSAI1PoutputFreq_Value=13714285.714285715
 Mcu.Pin46=PB5
 Mcu.Pin47=PB6
 TIM15.Channel-Output\ Compare2\ CH2=TIM_CHANNEL_2
 PB10.Signal=GPIO_Output
 PB14.Signal=GPIO_Output
 RCC.PLLSAI2RoutputFreq_Value=32000000
 PA5.Signal=GPIO_Analog
 Mcu.Pin40=PC10
 Mcu.Pin41=PC11
 PC12.Mode=Full_Duplex_Master
 Mcu.Pin44=PB3 (JTDO-TRACESWO)
 Mcu.Pin45=PB4 (NJTRST)
 Mcu.Pin42=PC12
 Mcu.Pin43=PD2
 ProjectManager.LastFirmware=true
 SH.S_TIM15_CH2.ConfNb=1
 Mcu.Pin37=PA13 (JTMS-SWDIO)
 Mcu.Pin38=PA14 (JTCK-SWCLK)
 PB15.GPIO_Label=RFID_PULL
 Mcu.Pin35=PA11
 RCC.I2C1Freq_Value=64000000
 Mcu.Pin36=PA12
 SPI1.Mode=SPI_MODE_MASTER
 Mcu.Pin39=PA15 (JTDI)
 PB3\ (JTDO-TRACESWO).Mode=TX_Only_Simplex_Unidirect_Master
 RCC.RNGFreq_Value=48000000
 VP_ADC1_TempSens_Input.Signal=ADC1_TempSens_Input
 PC2.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
 Mcu.Pin30=PC8
 PA1.GPIO_Label=BUTTON_DOWN
 Mcu.Pin33=PA9
 Mcu.Pin34=PA10
 Mcu.Pin31=PC9
 SH.ADCx_IN4.0=ADC1_IN4,IN4-Single-Ended
 Mcu.Pin32=PA8
 PA9.Locked=true
 NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 SH.S_TIM5_CH4.ConfNb=1
 ProjectManager.FreePins=false
 PC9.GPIOParameters=GPIO_Label
 RCC.LPTIM2Freq_Value=64000000
 Mcu.Pin26=PB14
 Mcu.Pin27=PB15
 Mcu.Pin24=PB12
 ProjectManager.UnderRoot=false
 Mcu.Pin25=PB13
 TIM8.Period=32768-1
 Mcu.Pin28=PC6
 PC7.GPIO_Label=iButton
 Mcu.Pin29=PC7
 PA13\ (JTMS-SWDIO).Mode=Serial_Wire
 PA4.Signal=GPIO_Analog
 Mcu.Pin22=PB10
 PB5.Signal=SPI1_MOSI
 Mcu.Pin23=PB11
 Mcu.Pin20=PB1
 ADC1.master=1
 PA3.Locked=true
 Mcu.Pin21=PB2
 PA10.Locked=true
 NVIC.ForceEnableDMAVector=true
 PA14\ (JTCK-SWCLK).Locked=true
 NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 ProjectManager.CompilerOptimize=6
 PA11.Signal=USB_OTG_FS_DM
 ProjectManager.HeapSize=0x200
 PA0.GPIOParameters=GPIO_Label
 Mcu.Pin15=PA6
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 Mcu.Pin16=PA7
 Mcu.Pin13=PA4
 Mcu.Pin14=PA5
 Mcu.Pin19=PB0
 ProjectManager.ComputerToolchain=false
 Mcu.Pin17=PC4
 Mcu.Pin18=PC5
 SH.ADCx_IN5.0=ADC1_IN5,IN5-Single-Ended
 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
 Mcu.Pin11=PA2
 Mcu.Pin12=PA3
 Mcu.Pin10=PA1
 PC3.GPIO_Label=BATT_V
 RCC.PWRFreq_Value=64000000
 SH.ADCx_IN5.ConfNb=1
 PB4\ (NJTRST).GPIO_Label=BUTTON_LEFT
 PB1.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
 SH.GPXTI1.ConfNb=1
 PD2.Signal=GPIO_Analog
 PB6.GPIO_Speed=GPIO_SPEED_FREQ_LOW
 RCC.I2C2Freq_Value=64000000
 PB0.Signal=GPXTI0
 PB4\ (NJTRST).GPIO_PuPd=GPIO_PULLDOWN
 PC0.Locked=true
 PC1.Signal=GPIO_Analog
 Mcu.Family=STM32L4
 SH.GPXTI1.0=GPIO_EXTI1
 ProjectManager.MainLocation=Src
 USB_DEVICE.CLASS_NAME_FS=CDC
 RCC.SAI1Freq_Value=13714285.714285715
 RCC.CortexFreq_Value=64000000
 ProjectManager.KeepUserCode=true
 Mcu.UserName=STM32L476RGTx
 PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
 PH0-OSC_IN\ (PH0).Locked=true
 PC10.Locked=true
 PC10.Signal=SPI3_SCK
 RCC.PLLSAI1RoutputFreq_Value=48000000
 PA0.GPIO_Label=IR_RX
 ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_SPI1_Init-SPI1-false-HAL-true,4-MX_SPI3_Init-SPI3-false-HAL-true,5-MX_ADC1_Init-ADC1-false-HAL-true,6-MX_COMP1_Init-COMP1-false-HAL-true,7-MX_TIM5_Init-TIM5-false-HAL-true,8-MX_TIM15_Init-TIM15-false-HAL-true,9-MX_USART1_UART_Init-USART1-false-HAL-true,10-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false,11-MX_TIM8_Init-TIM8-false-HAL-true
 PA11.Mode=Device_Only
 PC9.Locked=true
 TIM5.Pulse-PWM\ Generation4\ CH4=145
 PB0.GPIO_Label=BUTTON_UP
 RCC.USART2Freq_Value=64000000
 PD2.Locked=true
 VP_COMP1_VS_VREFINT12.Signal=COMP1_VS_VREFINT12
 PC13.GPIO_Label=BUTTON_BACK
 PC1.Locked=true
 PB13.GPIO_Label=RFID_OUT
 PB11.Signal=GPIO_Output
 PB15.Signal=S_TIM15_CH2
 ProjectManager.StackSize=0x400
 PB3\ (JTDO-TRACESWO).Signal=SPI1_SCK
 VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
 SH.GPXTI2.0=GPIO_EXTI2
 SH.S_TIM15_CH2.0=TIM15_CH2,Output Compare2 CH2
 RCC.I2C3Freq_Value=64000000
 Mcu.IP4=RCC
 RCC.FCLKCortexFreq_Value=64000000
 Mcu.IP5=SPI1
 Mcu.IP2=FREERTOS
 Mcu.IP3=NVIC
 Mcu.IP0=ADC1
 Mcu.IP1=COMP1
 PA12.Locked=true
 PA12.Signal=USB_OTG_FS_DP
 PB8.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
 SPI1.CLKPolarity=SPI_POLARITY_LOW
 Mcu.UserConstants=
 RCC.VCOSAI1OutputFreq_Value=96000000
 SPI3.CLKPolarity=SPI_POLARITY_LOW
 RCC.SDMMCFreq_Value=48000000
 PA14\ (JTCK-SWCLK).GPIOParameters=GPIO_Label
 SH.GPXTI13.ConfNb=1
 Mcu.ThirdPartyNb=0
 RCC.HCLKFreq_Value=64000000
 Mcu.IPNb=14
 ProjectManager.PreviousToolchain=
 PA8.GPIOParameters=GPIO_Speed,PinState,GPIO_Label,GPIO_ModeDefaultOutputPP
 Mcu.Pin6=PC1
 PB9.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
 Mcu.Pin7=PC2
 Mcu.Pin8=PC3
 Mcu.Pin9=PA0
-Mcu.PinsNb=58
+FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE,HEAP_NUMBER,configUSE_TIMERS,configUSE_IDLE_HOOK,FootprintOK
-Mcu.ThirdPartyNb=0
+RCC.AHBFreq_Value=64000000
-Mcu.UserConstants=
+Mcu.Pin0=PC13
-Mcu.UserName=STM32L476RGTx
+SPI3.DataSize=SPI_DATASIZE_8BIT
-MxCube.Version=5.4.0
+Mcu.Pin1=PC14-OSC32_IN (PC14)
-MxDb.Version=DB.5.0.40
+TIM8.IPParameters=Channel-Input_Capture2_from_TI2,ICPolarity_CH2,Prescaler,Period
-NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+Mcu.Pin2=PC15-OSC32_OUT (PC15)
 Mcu.Pin3=PH0-OSC_IN (PH0)
 Mcu.Pin4=PH1-OSC_OUT (PH1)
 Mcu.Pin5=PC0
 ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_4
 PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
 RCC.HSE_VALUE=16000000
 FREERTOS.configUSE_TIMERS=1
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
-NVIC.EXTI0_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
+Mcu.IP10=TIM15
-NVIC.EXTI15_10_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:true\:false
-NVIC.EXTI1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
+Mcu.IP12=USB_DEVICE
-NVIC.EXTI2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
+Mcu.IP11=USART1
-NVIC.EXTI4_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
+PB0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
-NVIC.EXTI9_5_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
+NVIC.TIM1_TRG_COM_TIM17_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
-NVIC.ForceEnableDMAVector=true
+Mcu.IP13=USB_OTG_FS
-NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+RCC.VCOInputFreq_Value=8000000
-NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+TIM5.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
-NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PB5.Mode=TX_Only_Simplex_Unidirect_Master
-NVIC.OTG_FS_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
+File.Version=6
-NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
+PC13.GPIO_PuPd=GPIO_PULLDOWN
-NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+PB7.Signal=GPIO_Input
-NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
+PB8.Locked=true
-NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:true\:true\:true
+PB6.GPIOParameters=GPIO_Speed,GPIO_Label
-NVIC.TIM8_CC_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
+PB0.Locked=true
-NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+FREERTOS.configTOTAL_HEAP_SIZE=8192
-PA0.GPIOParameters=GPIO_Label
+VP_COMP1_VS_VREFINT12.Mode=VREFINT_12
-PA0.GPIO_Label=IR_RX
+ProjectManager.ProjectName=cube
-PA0.Locked=true
+PB1.PinState=GPIO_PIN_SET
-PA0.Signal=ADCx_IN5
+PB7.GPIO_Label=CC1101_G0
-PA1.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
+PB4\ (NJTRST).Locked=true
 PA1.GPIO_Label=BUTTON_DOWN
 PA1.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
 PA1.GPIO_PuPd=GPIO_PULLDOWN
 PA1.Locked=true
 PA1.Signal=GPXTI1
 PA10.Locked=true
 PA10.Mode=Asynchronous
 PA10.Signal=USART1_RX
 PA11.Locked=true
 PA11.Mode=Device_Only
 PA11.Signal=USB_OTG_FS_DM
 PA12.Locked=true
 PA12.Mode=Device_Only
 PA12.Signal=USB_OTG_FS_DP
 PA13\ (JTMS-SWDIO).GPIOParameters=GPIO_Label
 PA13\ (JTMS-SWDIO).GPIO_Label=TMS
 PA13\ (JTMS-SWDIO).Locked=true
 PA13\ (JTMS-SWDIO).Mode=Serial_Wire
 PA13\ (JTMS-SWDIO).Signal=SYS_JTMS-SWDIO
 PA14\ (JTCK-SWCLK).GPIOParameters=GPIO_Label
 PA14\ (JTCK-SWCLK).GPIO_Label=TCK
 PA14\ (JTCK-SWCLK).Locked=true
 PA14\ (JTCK-SWCLK).Mode=Serial_Wire
 PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK
 PA15\ (JTDI).GPIOParameters=GPIO_Label
 PA15\ (JTDI).GPIO_Label=CC1101_CS
 PA15\ (JTDI).Locked=true
 PA15\ (JTDI).Signal=GPIO_Output
 PA2.GPIOParameters=GPIO_Label
 PA2.GPIO_Label=DISPLAY_DI
 PA2.Locked=true
 PA2.Signal=GPIO_Output
 PA3.GPIOParameters=GPIO_Label
 PA3.GPIO_Label=SPEAKER
 PA3.Locked=true
 PA3.Signal=S_TIM5_CH4
 PA4.Locked=true
 PA4.Signal=GPIO_Analog
 PA5.Locked=true
 PA5.Signal=GPIO_Analog
 PA6.Locked=true
 PA6.Signal=GPIO_Analog
 PA7.Locked=true
-PA7.Signal=GPIO_Analog
+NVIC.OTG_FS_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
 PA8.GPIOParameters=GPIO_Speed,PinState,GPIO_Label,GPIO_ModeDefaultOutputPP
 PA8.GPIO_Label=LED_RED
 PA8.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
 PA8.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
 PA8.Locked=true
 PA8.PinState=GPIO_PIN_SET
 PA8.Signal=GPIO_Output
 PA9.Locked=true
 PA9.Mode=Asynchronous
 PA9.Signal=USART1_TX
 PB0.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
 PB0.GPIO_Label=BUTTON_UP
 PB0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
 PB0.GPIO_PuPd=GPIO_PULLDOWN
 PB0.Locked=true
 PB0.Signal=GPXTI0
 PB1.GPIOParameters=GPIO_Speed,PinState,GPIO_Label,GPIO_ModeDefaultOutputPP
 PB1.GPIO_Label=LED_BLUE
 PB1.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
 PB1.GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM
 PB1.Locked=true
 PB1.PinState=GPIO_PIN_SET
 PB1.Signal=GPIO_Output
 PB10.GPIOParameters=GPIO_Label
 PB10.GPIO_Label=DISPLAY_RST
 PB10.Locked=true
 PB10.Signal=GPIO_Output
 PB11.GPIOParameters=GPIO_Label
 PB11.GPIO_Label=IR_TX
 PB11.Locked=true
 PB11.Signal=GPIO_Output
 PB12.Locked=true
 PB12.Signal=GPIO_Analog
 PB13.GPIOParameters=GPIO_Label
 PB13.GPIO_Label=RFID_OUT
 PB13.Locked=true
 PB13.Mode=Output Compare1 CH1N
 PB13.Signal=TIM15_CH1N
 PB14.GPIOParameters=GPIO_Speed,PinState,GPIO_Label,GPIO_ModeDefaultOutputPP
 PB14.GPIO_Label=LED_GREEN
 PB14.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
 PB14.GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM
 PB14.Locked=true
 PB14.PinState=GPIO_PIN_SET
 PB14.Signal=GPIO_Output
 PB15.GPIOParameters=GPIO_Label
 PB15.GPIO_Label=RFID_PULL
 PB15.Locked=true
 PB15.Signal=S_TIM15_CH2
 PB2.Locked=true
 PB2.Signal=GPIO_Analog
 PB3\ (JTDO-TRACESWO).Locked=true
 PB3\ (JTDO-TRACESWO).Mode=TX_Only_Simplex_Unidirect_Master
 PB3\ (JTDO-TRACESWO).Signal=SPI1_SCK
 PB4\ (NJTRST).GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
 PB4\ (NJTRST).GPIO_Label=BUTTON_LEFT
 PB4\ (NJTRST).GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
 PB4\ (NJTRST).GPIO_PuPd=GPIO_PULLDOWN
 PB4\ (NJTRST).Locked=true
 PB4\ (NJTRST).Signal=GPXTI4
 PB5.Locked=true
 PB5.Mode=TX_Only_Simplex_Unidirect_Master
 PB5.Signal=SPI1_MOSI
 PB6.GPIOParameters=GPIO_Speed,GPIO_Label
 PB6.GPIO_Label=DISPLAY_BACKLIGHT
 PB6.GPIO_Speed=GPIO_SPEED_FREQ_LOW
 PB6.Locked=true
 PB6.Signal=GPIO_Output
 PB7.GPIOParameters=GPIO_Label
 PB7.GPIO_Label=CC1101_G0
 PB7.Locked=true
 PB7.Signal=GPIO_Input
 PB8.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
 PB8.GPIO_Label=BUTTON_RIGHT
 PB8.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
 PB8.GPIO_PuPd=GPIO_PULLDOWN
 PB8.Locked=true
 PB8.Signal=GPXTI8
 PB9.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
 PB9.GPIO_Label=BUTTON_OK
 PB9.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
 PB9.GPIO_PuPd=GPIO_PULLDOWN
 PB9.Locked=true
 PB9.Signal=GPXTI9
 PC0.Locked=true
 PC0.Signal=GPIO_Analog
 PC1.Locked=true
 PC1.Signal=GPIO_Analog
 PC10.Locked=true
 PC10.Mode=Full_Duplex_Master
 PC10.Signal=SPI3_SCK
 PC11.Locked=true
 PC11.Mode=Full_Duplex_Master
 PC11.Signal=SPI3_MISO
 PC12.Locked=true
 PC12.Mode=Full_Duplex_Master
 PC12.Signal=SPI3_MOSI
 PC13.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
 PC13.GPIO_Label=BUTTON_BACK
 PC13.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
 PC13.GPIO_PuPd=GPIO_PULLDOWN
 PC13.Locked=true
 PC13.Signal=GPXTI13
 PC14-OSC32_IN\ (PC14).Locked=true
 PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator
 PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN
 PC15-OSC32_OUT\ (PC15).Locked=true
 PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator
 PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT
 PC2.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
 PC2.GPIO_Label=CHRG
 PC2.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
 PC2.GPIO_PuPd=GPIO_PULLUP
 PC2.Locked=true
 PC2.Signal=GPXTI2
 PC3.GPIOParameters=GPIO_Label
 PC3.GPIO_Label=BATT_V
 PC3.Locked=true
 PC3.Signal=ADCx_IN4
 PC4.GPIOParameters=GPIO_Label
 PC4.GPIO_Label=NFC_CS
 PC4.Locked=true
 PC4.Signal=GPIO_Output
 PC5.GPIOParameters=GPIO_Label
 PC5.GPIO_Label=RFID_RF_IN
 PC5.Mode=INP
 PC5.Signal=COMP1_INP
 PC6.GPIOParameters=GPIO_Label
 PC6.GPIO_Label=VIBRO
 PC6.Locked=true
 PC6.Signal=GPIO_Output
 PC7.GPIOParameters=GPIO_ModeDefaultPP,GPIO_Speed,GPIO_PuPd,GPIO_Label
 PC7.GPIO_Label=iButton
 PC7.GPIO_ModeDefaultPP=GPIO_MODE_AF_OD
 PC7.GPIO_PuPd=GPIO_NOPULL
 PC7.GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM
 PC7.Locked=true
 PC7.Signal=S_TIM8_CH2
 PC8.GPIOParameters=GPIO_Label
 PC8.GPIO_Label=DISPLAY_CS
 PC8.Locked=true
 PC8.Signal=GPIO_Output
 PC9.GPIOParameters=GPIO_Label
 PC9.GPIO_Label=SD_CS
 PC9.Locked=true
 PC9.Signal=GPIO_Output
 PCC.Checker=true
 PCC.Line=STM32L4x6
 PCC.MCU=STM32L476R(C-E-G)Tx
 PCC.PartNumber=STM32L476RGTx
 PCC.Seq0=0
 PCC.Series=STM32L4
 PCC.Temperature=25
 PCC.Vdd=3.0
 PD2.Locked=true
 PD2.Signal=GPIO_Analog
 PH0-OSC_IN\ (PH0).Locked=true
 PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
 PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
 PH1-OSC_OUT\ (PH1).Locked=true
 PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
 PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
 ProjectManager.CompilerOptimize=6
 ProjectManager.ComputerToolchain=false
 ProjectManager.CoupleFile=false
 ProjectManager.CustomerFirmwarePackage=
 ProjectManager.DefaultFWLocation=true
 ProjectManager.DeletePrevious=true
 ProjectManager.DeviceId=STM32L476RGTx
 ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.14.0
 ProjectManager.FreePins=false
 ProjectManager.HalAssertFull=false
 ProjectManager.HeapSize=0x200
 ProjectManager.KeepUserCode=true
 ProjectManager.LastFirmware=true
 ProjectManager.LibraryCopy=0
 ProjectManager.MainLocation=Src
 ProjectManager.NoMain=false
 ProjectManager.PreviousToolchain=
 ProjectManager.ProjectBuild=false
 ProjectManager.ProjectFileName=flipperzero_f2.ioc
 ProjectManager.ProjectName=flipperzero_f2
 ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=Makefile
 ProjectManager.ToolChainLocation=
-ProjectManager.UnderRoot=false
+PA2.GPIO_Label=DISPLAY_DI
 ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_SPI1_Init-SPI1-false-HAL-true,4-MX_SPI3_Init-SPI3-false-HAL-true,5-MX_ADC1_Init-ADC1-false-HAL-true,6-MX_COMP1_Init-COMP1-false-HAL-true,7-MX_TIM5_Init-TIM5-false-HAL-true,8-MX_TIM15_Init-TIM15-false-HAL-true,9-MX_USART1_UART_Init-USART1-false-HAL-true,10-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false,11-MX_TIM8_Init-TIM8-false-HAL-true
 RCC.ADCCLockSelection=RCC_ADCCLKSOURCE_SYSCLK
 RCC.ADCFreq_Value=64000000
 RCC.AHBFreq_Value=64000000
 RCC.APB1Freq_Value=64000000
 RCC.APB1TimFreq_Value=64000000
 RCC.APB2Freq_Value=64000000
 RCC.APB2TimFreq_Value=64000000
 RCC.CortexFreq_Value=64000000
 RCC.DFSDMFreq_Value=64000000
 RCC.FCLKCortexFreq_Value=64000000
 RCC.FamilyName=M
 RCC.HCLKFreq_Value=64000000
 RCC.HSE_VALUE=16000000
 RCC.HSI_VALUE=16000000
 RCC.I2C1Freq_Value=64000000
 RCC.I2C2Freq_Value=64000000
 RCC.I2C3Freq_Value=64000000
 RCC.IPParameters=ADCCLockSelection,ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PREFETCH_ENABLE,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value
 RCC.LPTIM1Freq_Value=64000000
 RCC.LPTIM2Freq_Value=64000000
 RCC.LPUART1Freq_Value=64000000
 RCC.LSCOPinFreq_Value=32000
 RCC.LSI_VALUE=32000
-RCC.MCO1PinFreq_Value=64000000
+SH.GPXTI0.0=GPIO_EXTI0
 USB_OTG_FS.VirtualMode=Device_Only
 VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_FS
 PC14-OSC32_IN\ (PC14).Locked=true
 TIM8.Prescaler=64-1
 PC4.Locked=true
 SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,BaudRatePrescaler,CLKPolarity
 PC5.Signal=COMP1_INP
 SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16
 PA1.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
 PC2.GPIO_Label=CHRG
 PA8.PinState=GPIO_PIN_SET
 PB15.Locked=true
 PB3\ (JTDO-TRACESWO).Locked=true
 RCC.PLLSAI1N=12
 PA3.Signal=S_TIM5_CH4
 PA2.Locked=true
 RCC.MSI_VALUE=4000000
 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
 PA14\ (JTCK-SWCLK).Mode=Serial_Wire
 PB8.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
 PB9.GPIO_Label=BUTTON_OK
 PA10.Mode=Asynchronous
 PC9.GPIO_Label=SD_CS
 ProjectManager.NoMain=false
 SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,BaudRatePrescaler,CLKPolarity,CLKPhase
 USB_DEVICE.VirtualModeFS=Cdc_FS
 NVIC.SavedSvcallIrqHandlerGenerated=true
 PC11.Signal=SPI3_MISO
 PC8.Signal=GPIO_Output
 PC4.Signal=GPIO_Output
 PC10.Mode=Full_Duplex_Master
 ProjectManager.DefaultFWLocation=false
 PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT
 PB12.Locked=true
 PA14\ (JTCK-SWCLK).GPIO_Label=TCK
 ProjectManager.DeletePrevious=true
 PB10.Locked=true
 RCC.VCOSAI2OutputFreq_Value=64000000
 boardIOC=true
 USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS
 RCC.FamilyName=M
 PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
 PB9.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
 PC8.GPIO_Label=DISPLAY_CS
 USART1.VirtualMode-Asynchronous=VM_ASYNC
 FREERTOS.configUSE_IDLE_HOOK=1
 PA9.Mode=Asynchronous
 PB4\ (NJTRST).GPIOParameters=GPIO_PuPd,GPIO_Label
 NVIC.TIM8_CC_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
 PB14.PinState=GPIO_PIN_SET
 ProjectManager.TargetToolchain=Makefile
 PB10.GPIO_Label=DISPLAY_RST
 PB7.GPIOParameters=GPIO_Label
 VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS
 PC5.GPIOParameters=GPIO_Label
 PC2.Locked=true
 ProjectManager.RegisterCallBack=
 PC15-OSC32_OUT\ (PC15).Locked=true
 RCC.USBFreq_Value=48000000
 TIM15.IPParameters=Channel-Output Compare1 CH1N,Channel-Output Compare2 CH2
 PB14.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
 PA1.Signal=GPXTI1
 PB1.Locked=true
 PH1-OSC_OUT\ (PH1).Locked=true
 board=NUCLEO-L476RG
 PC7.GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM
 RCC.VCOOutputFreq_Value=128000000
 NVIC.SavedSystickIrqHandlerGenerated=true
 RCC.APB2Freq_Value=64000000
 RCC.UART4Freq_Value=64000000
 SPI3.CalculateBaudRate=1000.0 KBits/s
 MxCube.Version=6.0.1
 PA13\ (JTMS-SWDIO).GPIO_Label=TMS
 PC13.GPIOParameters=GPIO_PuPd,GPIO_Label
 RCC.PLLSAI1QoutputFreq_Value=48000000
 RCC.ADCFreq_Value=64000000
 SPI3.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_64
 VP_ADC1_Vref_Input.Signal=ADC1_Vref_Input
 SH.S_TIM5_CH4.0=TIM5_CH4,PWM Generation4 CH4
 PC2.GPIO_PuPd=GPIO_PULLUP
 RCC.UART5Freq_Value=64000000
 PB15.GPIOParameters=GPIO_Label
 ADC1.NbrOfConversion=1
 PA15\ (JTDI).GPIO_Label=CC1101_CS
 RCC.IPParameters=ADCCLockSelection,ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PREFETCH_ENABLE,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value
 ProjectManager.AskForMigrate=true
 Mcu.Name=STM32L476R(C-E-G)Tx
 NVIC.SavedPendsvIrqHandlerGenerated=true
 PA2.Signal=GPIO_Output
 PB2.Locked=true
 Mcu.IP8=TIM5
 VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
 Mcu.IP9=TIM8
 Mcu.IP6=SPI3
 Mcu.IP7=SYS
 ProjectManager.CoupleFile=true
 NVIC.EXTI0_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
 RCC.SYSCLKFreq_VALUE=64000000
 PA1.Locked=true
 PA12.Mode=Device_Only
 SH.GPXTI4.0=GPIO_EXTI4
 RCC.PLLSAI2PoutputFreq_Value=9142857.142857144
 KeepUserPlacement=false
 TIM5.Prescaler=500 - 1
 PC5.GPIO_Label=RFID_RF_IN
 PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN
 SH.GPXTI9.ConfNb=1
 NVIC.EXTI9_5_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
 SH.GPXTI4.ConfNb=1
 PC6.GPIOParameters=GPIO_Label
 RCC.HSI_VALUE=16000000
 ADC1.NbrOfConversionFlag=1
 RCC.PLLM=2
 RCC.PLLN=16
 RCC.PLLPoutputFreq_Value=18285714.285714287
 RCC.PLLQoutputFreq_Value=64000000
 RCC.PLLRCLKFreq_Value=64000000
 RCC.PLLSAI1N=12
 RCC.PLLSAI1PoutputFreq_Value=13714285.714285715
 RCC.PLLSAI1QoutputFreq_Value=48000000
 RCC.PLLSAI1RoutputFreq_Value=48000000
 RCC.PLLSAI2PoutputFreq_Value=9142857.142857144
 RCC.PLLSAI2RoutputFreq_Value=32000000
 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
 RCC.PREFETCH_ENABLE=1
 RCC.PWRFreq_Value=64000000
 RCC.RNGFreq_Value=48000000
 RCC.SAI1Freq_Value=13714285.714285715
 RCC.SAI2Freq_Value=13714285.714285715
 RCC.SDMMCFreq_Value=48000000
 RCC.SWPMI1Freq_Value=64000000
 RCC.SYSCLKFreq_VALUE=64000000
 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
 RCC.UART4Freq_Value=64000000
 RCC.UART5Freq_Value=64000000
 RCC.USART1Freq_Value=64000000
 RCC.USART2Freq_Value=64000000
 RCC.USART3Freq_Value=64000000
 RCC.USBFreq_Value=48000000
 RCC.VCOInputFreq_Value=8000000
 RCC.VCOOutputFreq_Value=128000000
 RCC.VCOSAI1OutputFreq_Value=96000000
 RCC.VCOSAI2OutputFreq_Value=64000000
 SH.ADCx_IN4.0=ADC1_IN4,IN4-Single-Ended
 SH.ADCx_IN4.ConfNb=1
 SH.ADCx_IN5.0=ADC1_IN5,IN5-Single-Ended
 SH.ADCx_IN5.ConfNb=1
 SH.GPXTI0.0=GPIO_EXTI0
 SH.GPXTI0.ConfNb=1
 SH.GPXTI1.0=GPIO_EXTI1
 SH.GPXTI1.ConfNb=1
 SH.GPXTI13.0=GPIO_EXTI13
 SH.GPXTI13.ConfNb=1
 SH.GPXTI2.0=GPIO_EXTI2
 SH.GPXTI2.ConfNb=1
 SH.GPXTI4.0=GPIO_EXTI4
 SH.GPXTI4.ConfNb=1
 SH.GPXTI8.0=GPIO_EXTI8
 SH.GPXTI8.ConfNb=1
 SH.GPXTI9.0=GPIO_EXTI9
 SH.GPXTI9.ConfNb=1
 SH.S_TIM15_CH2.0=TIM15_CH2,Output Compare2 CH2
 SH.S_TIM15_CH2.ConfNb=1
 SH.S_TIM5_CH4.0=TIM5_CH4,PWM Generation4 CH4
 SH.S_TIM5_CH4.ConfNb=1
 SH.S_TIM8_CH2.0=TIM8_CH2,Input_Capture2_from_TI2
 SH.S_TIM8_CH2.ConfNb=1
 SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16
 SPI1.CLKPhase=SPI_PHASE_1EDGE
 SPI1.CLKPolarity=SPI_POLARITY_LOW
 SPI1.CalculateBaudRate=4.0 MBits/s
 SPI1.DataSize=SPI_DATASIZE_8BIT
 SPI1.Direction=SPI_DIRECTION_2LINES
 SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,BaudRatePrescaler,CLKPolarity,CLKPhase
 SPI1.Mode=SPI_MODE_MASTER
 SPI1.VirtualType=VM_MASTER
 SPI3.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_64
 SPI3.CLKPolarity=SPI_POLARITY_LOW
 SPI3.CalculateBaudRate=1000.0 KBits/s
 SPI3.DataSize=SPI_DATASIZE_8BIT
 SPI3.Direction=SPI_DIRECTION_2LINES
 SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,BaudRatePrescaler,CLKPolarity
 SPI3.Mode=SPI_MODE_MASTER
 SPI3.VirtualType=VM_MASTER
 TIM15.Channel-Output\ Compare1\ CH1N=TIM_CHANNEL_1
 TIM15.Channel-Output\ Compare2\ CH2=TIM_CHANNEL_2
 TIM15.IPParameters=Channel-Output Compare1 CH1N,Channel-Output Compare2 CH2
 TIM5.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
 TIM5.IPParameters=Prescaler,Period,Channel-PWM Generation4 CH4,Pulse-PWM Generation4 CH4
 TIM5.Period=291
 TIM5.Prescaler=500 - 1
 TIM5.Pulse-PWM\ Generation4\ CH4=145
 TIM8.Channel-Input_Capture2_from_TI2=TIM_CHANNEL_2
-TIM8.ICPolarity_CH2=TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+PB7.Locked=true
-TIM8.IPParameters=Channel-Input_Capture2_from_TI2,ICPolarity_CH2,Prescaler,Period
+PB8.Signal=GPXTI8
-TIM8.Period=32768-1
+PC8.Locked=true
-TIM8.Prescaler=64-1
+TIM5.Period=291
-USART1.IPParameters=VirtualMode-Asynchronous
+PC9.Signal=GPIO_Output
-USART1.VirtualMode-Asynchronous=VM_ASYNC
+PA15\ (JTDI).Locked=true
-USB_DEVICE.CLASS_NAME_FS=CDC
+RCC.APB1Freq_Value=64000000
 USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS
 USB_DEVICE.VirtualMode=Cdc
-USB_DEVICE.VirtualModeFS=Cdc_FS
+PB11.Locked=true
-USB_OTG_FS.IPParameters=VirtualMode
+ProjectManager.DeviceId=STM32L476RGTx
-USB_OTG_FS.VirtualMode=Device_Only
+SH.S_TIM8_CH2.ConfNb=1
-VP_ADC1_TempSens_Input.Mode=IN-TempSens
+PB12.Signal=GPIO_Analog
-VP_ADC1_TempSens_Input.Signal=ADC1_TempSens_Input
+ProjectManager.LibraryCopy=2
-VP_ADC1_Vref_Input.Mode=IN-Vrefint
+PB0.GPIO_PuPd=GPIO_PULLDOWN
-VP_ADC1_Vref_Input.Signal=ADC1_Vref_Input
+PA3.GPIO_Label=SPEAKER
-VP_COMP1_VS_VREFINT12.Mode=VREFINT_12
+PB1.GPIOParameters=GPIO_Speed,PinState,GPIO_Label,GPIO_ModeDefaultOutputPP
-VP_COMP1_VS_VREFINT12.Signal=COMP1_VS_VREFINT12
+PA7.Signal=GPIO_Analog
-VP_FREERTOS_VS_CMSIS_V1.Mode=CMSIS_V1
+PB4\ (NJTRST).Signal=GPXTI4
-VP_FREERTOS_VS_CMSIS_V1.Signal=FREERTOS_VS_CMSIS_V1
+PA6.Locked=true
 VP_SYS_VS_Systick.Mode=SysTick
 VP_SYS_VS_Systick.Signal=SYS_VS_Systick
 VP_TIM8_VS_ClockSourceINT.Mode=Internal
 VP_TIM8_VS_ClockSourceINT.Signal=TIM8_VS_ClockSourceINT
 VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS
 VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_FS
 board=NUCLEO-L476RG
 boardIOC=true
--- a/target_f2/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l476xx.s
+++ b/target_f2/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l476xx.s
@ -18,10 +18,10 @@
  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
  * the "License"; You may not use this file except in compliance with the
  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
  *
  ******************************************************************************
  */
@ -60,7 +60,10 @@ defined in linker script */
 	.weak	Reset_Handler
 	.type	Reset_Handler, %function
 Reset_Handler:
-  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+  ldr   sp, =_estack    /* Set stack pointer */
 /* Call the clock system initialization function.*/
    bl  SystemInit
 /* Copy the data segment initializers from flash to SRAM */
  movs	r1, #0
@ -90,8 +93,6 @@ LoopFillZerobss:
 	cmp	r2, r3
 	bcc	FillZerobss
 /* Call the clock system intitialization function.*/
    bl  SystemInit
 /* Call static constructors */
    bl __libc_init_array
 /* Call the application's entry point.*/
--- a/firmware/targets/f2/target.mk
+++ b/firmware/targets/f2/target.mk
@ -0,0 +1,81 @@
 TOOLCHAIN = arm
 BOOT_ADDRESS	= 0x08000000
 FW_ADDRESS		= 0x08008000
 OS_OFFSET		= 0x00008000
 FLASH_ADDRESS	= 0x08008000
 BOOT_CFLAGS		= -DBOOT_ADDRESS=$(BOOT_ADDRESS) -DFW_ADDRESS=$(FW_ADDRESS) -DOS_OFFSET=$(OS_OFFSET)
 MCU_FLAGS		= -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard
 CFLAGS			+= $(MCU_FLAGS) $(BOOT_CFLAGS) -DSTM32L476xx -Wall -fdata-sections -ffunction-sections
 LDFLAGS			+= $(MCU_FLAGS) -specs=nosys.specs -specs=nano.specs 
 CUBE_DIR		= ../lib/STM32CubeL4
 C_SOURCES		+= \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c \
 	$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c \
 	$(CUBE_DIR)/Middlewares/Third_Party/FreeRTOS/Source/croutine.c \
 	$(CUBE_DIR)/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \
 	$(CUBE_DIR)/Middlewares/Third_Party/FreeRTOS/Source/list.c \
 	$(CUBE_DIR)/Middlewares/Third_Party/FreeRTOS/Source/queue.c \
 	$(CUBE_DIR)/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c \
 	$(CUBE_DIR)/Middlewares/Third_Party/FreeRTOS/Source/tasks.c \
 	$(CUBE_DIR)/Middlewares/Third_Party/FreeRTOS/Source/timers.c \
 	$(CUBE_DIR)/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c \
 	$(CUBE_DIR)/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_1.c \
 	$(CUBE_DIR)/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c \
 	$(CUBE_DIR)/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \
 	$(CUBE_DIR)/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \
 	$(CUBE_DIR)/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c \
 	$(CUBE_DIR)/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c \
 	$(wildcard $(TARGET_DIR)/Src/*.c)
 ASM_SOURCES += $(TARGET_DIR)/startup_stm32l476xx.s
 # Common
 CFLAGS			+= \
 	-DUSE_HAL_DRIVER \
 	-DHAVE_FREERTOS \
 	-DBUTON_INVERT=false \
 	-DDEBUG_UART=huart1
 LDFLAGS			+= -T$(TARGET_DIR)/STM32L476RGTx_FLASH.ld
 CFLAGS += \
 	-I$(TARGET_DIR)/Inc \
 	-I$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Inc \
 	-I$(CUBE_DIR)/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy \
 	-I$(CUBE_DIR)/Middlewares/Third_Party/FreeRTOS/Source/include \
 	-I$(CUBE_DIR)/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 \
 	-I$(CUBE_DIR)/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F \
 	-I$(CUBE_DIR)/Middlewares/ST/STM32_USB_Device_Library/Core/Inc \
 	-I$(CUBE_DIR)/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc \
 	-I$(CUBE_DIR)/Drivers/CMSIS/Device/ST/STM32L4xx/Include \
 	-I$(CUBE_DIR)/Drivers/CMSIS/Include \
 	-I$(CUBE_DIR)/Drivers/CMSIS/Include
--- a/firmware/targets/local/Inc/cmsis_os.h
+++ b/firmware/targets/local/Inc/cmsis_os.h
@ -2,6 +2,7 @@
 #include "main.h"
 #include <stdbool.h>
 #include <pthread.h>
 void osDelay(uint32_t ms);
--- a/firmware/targets/local/Inc/flipper_hal.h
+++ b/firmware/targets/local/Inc/flipper_hal.h
@ -20,7 +20,7 @@ typedef struct {
 void app_gpio_init(GpioPin gpio, GpioMode mode);
-inline void app_gpio_write(GpioPin gpio, bool state) {
+static inline void app_gpio_write(GpioPin gpio, bool state) {
    if(gpio.pin != 0) {
        if(state) {
            printf("[GPIO] %s%d on\n", gpio.port, gpio.pin);
@ -32,7 +32,7 @@ inline void app_gpio_write(GpioPin gpio, bool state) {
    }
 }
-inline bool app_gpio_read(GpioPin gpio) {
+static inline bool app_gpio_read(GpioPin gpio) {
    // TODO emulate pin state?
    return false;
@ -48,15 +48,15 @@ void pwm_set(float value, float freq, TIM_HandleTypeDef* tim, uint32_t channel);
 extern TIM_HandleTypeDef htim8;
-inline void app_tim_ic_init(bool both) {
+static inline void app_tim_ic_init(bool both) {
    printf("[TIM] init\n");
 }
-inline void app_tim_pulse(uint32_t width) {
+static inline void app_tim_pulse(uint32_t width) {
    printf("[TIM] pulse %d\n", width);
 }
-inline void app_tim_stop() {
+static inline void app_tim_stop() {
    printf("[TIM] stop\n");
 }
--- a/firmware/targets/local/Inc/main.h
+++ b/firmware/targets/local/Inc/main.h
--- a/firmware/targets/local/Src/flipper_hal.c
+++ b/firmware/targets/local/Src/flipper_hal.c
--- a/firmware/targets/local/Src/lo_hal.c
+++ b/firmware/targets/local/Src/lo_hal.c
--- a/firmware/targets/local/Src/lo_os.c
+++ b/firmware/targets/local/Src/lo_os.c
--- a/firmware/targets/local/Src/main.c
+++ b/firmware/targets/local/Src/main.c
@ -5,10 +5,8 @@ Local fw build entry point.
 */
 void app();
 unsigned int add(unsigned int a, unsigned int b);
 int main() {
    add(2, 2);
    app();
    return 0;
--- a/firmware/targets/local/target.mk
+++ b/firmware/targets/local/target.mk
@ -0,0 +1,15 @@
 TOOLCHAIN = x86
 # Sources
 C_SOURCES += $(TARGET_DIR)/Src/main.c
 C_SOURCES += $(TARGET_DIR)/Src/flipper_hal.c
 C_SOURCES += $(TARGET_DIR)/Src/lo_os.c
 C_SOURCES += $(TARGET_DIR)/Src/lo_hal.c
 # CFLAGS += -DFURI_DEBUG
 CFLAGS += -I$(TARGET_DIR)/Inc
 CFLAGS += -Wall -fdata-sections -ffunction-sections -pthread
 LDFLAGS += -pthread
 run: all
 	$(OBJ_DIR)/$(PROJECT).elf
--- a/lib/STM32CubeL4
+++ b/lib/STM32CubeL4
@ -0,0 +1 @@
 Subproject commit d023c0d560ace11509f9b761c8913a9e48fcf194
--- a/lib/lib.mk
+++ b/lib/lib.mk
@ -0,0 +1,25 @@
 LIB_DIR			= $(PROJECT_ROOT)/lib
 CFLAGS			+= -I$(LIB_DIR)
 U8G2_DIR		= $(LIB_DIR)/u8g2
 CFLAGS			+= -I$(U8G2_DIR)
 C_SOURCES		+= $(U8G2_DIR)/u8x8_d_st7565.c
 C_SOURCES		+= $(U8G2_DIR)/u8g2_d_setup.c
 C_SOURCES		+= $(U8G2_DIR)/u8g2_intersection.c
 C_SOURCES		+= $(U8G2_DIR)/u8g2_setup.c
 C_SOURCES		+= $(U8G2_DIR)/u8g2_d_memory.c
 C_SOURCES		+= $(U8G2_DIR)/u8x8_cad.c
 C_SOURCES		+= $(U8G2_DIR)/u8x8_byte.c
 C_SOURCES		+= $(U8G2_DIR)/u8x8_gpio.c
 C_SOURCES		+= $(U8G2_DIR)/u8x8_display.c
 C_SOURCES		+= $(U8G2_DIR)/u8x8_setup.c
 C_SOURCES		+= $(U8G2_DIR)/u8g2_hvline.c
 C_SOURCES		+= $(U8G2_DIR)/u8g2_ll_hvline.c
 C_SOURCES		+= $(U8G2_DIR)/u8g2_circle.c
 C_SOURCES		+= $(U8G2_DIR)/u8g2_box.c
 C_SOURCES		+= $(U8G2_DIR)/u8g2_buffer.c
 C_SOURCES		+= $(U8G2_DIR)/u8g2_font.c
 C_SOURCES		+= $(U8G2_DIR)/u8g2_fonts.c
 C_SOURCES		+= $(U8G2_DIR)/u8x8_8x8.c
 C_SOURCES		+= $(U8G2_DIR)/u8g2_bitmap.c
--- a/make/base.mk
+++ b/make/base.mk
@ -0,0 +1,4 @@
 OBJ_DIR			= .obj
 ASM_SOURCES		= 
 C_SOURCES		= 
 CPP_SOURCES		= 
--- a/make/rules.mk
+++ b/make/rules.mk
@ -0,0 +1,79 @@
 OBJ_DIR := $(OBJ_DIR)/$(TARGET)
 # Include source folder paths to virtual paths
 VPATH = $(sort $(dir $(C_SOURCES)) $(dir $(ASM_SOURCES)) $(dir $(CPP_SOURCES)))
 # Gather object
 OBJECTS = $(addprefix $(OBJ_DIR)/, $(notdir $(C_SOURCES:.c=.o)))
 OBJECTS += $(addprefix $(OBJ_DIR)/, $(notdir $(ASM_SOURCES:.s=.o)))
 OBJECTS += $(addprefix $(OBJ_DIR)/, $(notdir $(CPP_SOURCES:.cpp=.o)))
 # Generate dependencies
 DEPS = $(OBJECTS:.o=.d)
 $(shell mkdir -p $(OBJ_DIR))
 all: $(OBJ_DIR)/$(PROJECT).elf $(OBJ_DIR)/$(PROJECT).hex $(OBJ_DIR)/$(PROJECT).bin
 $(OBJ_DIR)/$(PROJECT).elf: $(OBJECTS)
 	@echo "\tLD\t" $@
 	@$(CC) $(LDFLAGS) $(OBJECTS) -o $@
 	@$(SZ) $@
 $(OBJ_DIR)/$(PROJECT).hex: $(OBJ_DIR)/$(PROJECT).elf
 	@echo "\tHEX\t" $@
 	@$(HEX) $< $@
 $(OBJ_DIR)/$(PROJECT).bin: $(OBJ_DIR)/$(PROJECT).elf
 	@echo "\tBIN\t" $@
 	@$(BIN) $< $@
 $(OBJ_DIR)/%.o: %.c
 	@echo "\tCC\t" $@
 	@$(CC) $(CFLAGS) -c $< -o $@
 $(OBJ_DIR)/%.o: %.s
 	@echo "\tASM\t" $@
 	@$(AS) $(CFLAGS) -c $< -o $@
 $(OBJ_DIR)/%.o: %.cpp
 	@echo "\tCPP\t" $@
 	@$(CPP) $(CFLAGS) $(CPPFLAGS) -c $< -o $@
 $(OBJ_DIR)/flash: $(OBJ_DIR)/$(PROJECT).bin
 	st-flash --reset write $(OBJ_DIR)/$(PROJECT).bin $(FLASH_ADDRESS)
 	touch $@
 $(OBJ_DIR)/upload: $(OBJ_DIR)/$(PROJECT).bin
 	dfu-util -D $(OBJ_DIR)/$(PROJECT).bin -a 0 -s $(FLASH_ADDRESS)
 	touch $@
 flash: $(OBJ_DIR)/flash
 upload: $(OBJ_DIR)/upload
 debug: flash
 	set -m; st-util -n --semihosting & echo $$! > st-util.PID
 	arm-none-eabi-gdb -ex "target extended-remote 127.0.0.1:4242" $(OBJ_DIR)/$(PROJECT).elf; kill `cat st-util.PID`; rm st-util.PID
 clean:
 	@echo "\tCLEAN\t"
 	@$(RM) $(OBJ_DIR)/*
 .PHONY: check-and-reinit-submodules
 check-and-reinit-submodules:
 	@if git submodule status | egrep -q '^[-]|^[+]' ; then \
 		echo "INFO: Need to reinitialize git submodules"; \
 		git submodule update --init; \
 	fi
 z: clean
 	$(MAKE) all
 zz: clean
 	$(MAKE) flash
 zzz: clean
 	$(MAKE) debug
 -include $(DEPS)
--- a/make/toolchain.mk
+++ b/make/toolchain.mk
@ -0,0 +1,26 @@
 # Compiller 
 ifeq ($(TOOLCHAIN), arm)
 PREFIX = arm-none-eabi-
 ifdef GCC_PATH
 PREFIX = $(GCC_PATH)/$(PREFIX)
 endif
 endif
 CC	= $(PREFIX)gcc
 CPP	= $(PREFIX)g++
 AS	= $(PREFIX)gcc -x assembler-with-cpp
 CP	= $(PREFIX)objcopy
 SZ	= $(PREFIX)size
 HEX	= $(CP) -O ihex
 BIN	= $(CP) -O binary -S
 DEBUG ?= 1
 ifeq ($(DEBUG), 1)
 CFLAGS += -DDEBUG -g
 else
 CFLAGS += -DNDEBUG -Os
 endif
 CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
 CPPFLAGS = -fno-threadsafe-statics
 LDFLAGS	+= -Wl,-Map=$(OBJ_DIR)/$(PROJECT).map,--cref -Wl,--gc-sections
--- a/target_f1/.mxproject
+++ b/target_f1/.mxproject
--- a/target_f1/Drivers/CMSIS/Core/Include/cmsis_armcc.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/cmsis_armcc.h
@ -1,865 +0,0 @@
 /**************************************************************************//**
 * @file     cmsis_armcc.h
 * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
 * @version  V5.0.4
 * @date     10. January 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #ifndef __CMSIS_ARMCC_H
 #define __CMSIS_ARMCC_H
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
 #endif
 /* CMSIS compiler control architecture macros */
 #if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
  #define __ARM_ARCH_6M__           1
 #endif
 #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
  #define __ARM_ARCH_7M__           1
 #endif
 #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
  #define __ARM_ARCH_7EM__          1
 #endif
  /* __ARM_ARCH_8M_BASE__  not applicable */
  /* __ARM_ARCH_8M_MAIN__  not applicable */
 /* CMSIS compiler specific defines */
 #ifndef   __ASM
  #define __ASM                                  __asm
 #endif
 #ifndef   __INLINE
  #define __INLINE                               __inline
 #endif
 #ifndef   __STATIC_INLINE
  #define __STATIC_INLINE                        static __inline
 #endif
 #ifndef   __STATIC_FORCEINLINE                 
  #define __STATIC_FORCEINLINE                   static __forceinline
 #endif           
 #ifndef   __NO_RETURN
  #define __NO_RETURN                            __declspec(noreturn)
 #endif
 #ifndef   __USED
  #define __USED                                 __attribute__((used))
 #endif
 #ifndef   __WEAK
  #define __WEAK                                 __attribute__((weak))
 #endif
 #ifndef   __PACKED
  #define __PACKED                               __attribute__((packed))
 #endif
 #ifndef   __PACKED_STRUCT
  #define __PACKED_STRUCT                        __packed struct
 #endif
 #ifndef   __PACKED_UNION
  #define __PACKED_UNION                         __packed union
 #endif
 #ifndef   __UNALIGNED_UINT32        /* deprecated */
  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
 #endif
 #ifndef   __UNALIGNED_UINT16_WRITE
  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT16_READ
  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
 #endif
 #ifndef   __UNALIGNED_UINT32_WRITE
  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT32_READ
  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
 #endif
 #ifndef   __ALIGNED
  #define __ALIGNED(x)                           __attribute__((aligned(x)))
 #endif
 #ifndef   __RESTRICT
  #define __RESTRICT                             __restrict
 #endif
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  @{
 */
 /**
  \brief   Enable IRQ Interrupts
  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
 /* intrinsic void __enable_irq();     */
 /**
  \brief   Disable IRQ Interrupts
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
 /* intrinsic void __disable_irq();    */
 /**
  \brief   Get Control Register
  \details Returns the content of the Control Register.
  \return               Control Register value
 */
 __STATIC_INLINE uint32_t __get_CONTROL(void)
 {
  register uint32_t __regControl         __ASM("control");
  return(__regControl);
 }
 /**
  \brief   Set Control Register
  \details Writes the given value to the Control Register.
  \param [in]    control  Control Register value to set
 */
 __STATIC_INLINE void __set_CONTROL(uint32_t control)
 {
  register uint32_t __regControl         __ASM("control");
  __regControl = control;
 }
 /**
  \brief   Get IPSR Register
  \details Returns the content of the IPSR Register.
  \return               IPSR Register value
 */
 __STATIC_INLINE uint32_t __get_IPSR(void)
 {
  register uint32_t __regIPSR          __ASM("ipsr");
  return(__regIPSR);
 }
 /**
  \brief   Get APSR Register
  \details Returns the content of the APSR Register.
  \return               APSR Register value
 */
 __STATIC_INLINE uint32_t __get_APSR(void)
 {
  register uint32_t __regAPSR          __ASM("apsr");
  return(__regAPSR);
 }
 /**
  \brief   Get xPSR Register
  \details Returns the content of the xPSR Register.
  \return               xPSR Register value
 */
 __STATIC_INLINE uint32_t __get_xPSR(void)
 {
  register uint32_t __regXPSR          __ASM("xpsr");
  return(__regXPSR);
 }
 /**
  \brief   Get Process Stack Pointer
  \details Returns the current value of the Process Stack Pointer (PSP).
  \return               PSP Register value
 */
 __STATIC_INLINE uint32_t __get_PSP(void)
 {
  register uint32_t __regProcessStackPointer  __ASM("psp");
  return(__regProcessStackPointer);
 }
 /**
  \brief   Set Process Stack Pointer
  \details Assigns the given value to the Process Stack Pointer (PSP).
  \param [in]    topOfProcStack  Process Stack Pointer value to set
 */
 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
 {
  register uint32_t __regProcessStackPointer  __ASM("psp");
  __regProcessStackPointer = topOfProcStack;
 }
 /**
  \brief   Get Main Stack Pointer
  \details Returns the current value of the Main Stack Pointer (MSP).
  \return               MSP Register value
 */
 __STATIC_INLINE uint32_t __get_MSP(void)
 {
  register uint32_t __regMainStackPointer     __ASM("msp");
  return(__regMainStackPointer);
 }
 /**
  \brief   Set Main Stack Pointer
  \details Assigns the given value to the Main Stack Pointer (MSP).
  \param [in]    topOfMainStack  Main Stack Pointer value to set
 */
 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
 {
  register uint32_t __regMainStackPointer     __ASM("msp");
  __regMainStackPointer = topOfMainStack;
 }
 /**
  \brief   Get Priority Mask
  \details Returns the current state of the priority mask bit from the Priority Mask Register.
  \return               Priority Mask value
 */
 __STATIC_INLINE uint32_t __get_PRIMASK(void)
 {
  register uint32_t __regPriMask         __ASM("primask");
  return(__regPriMask);
 }
 /**
  \brief   Set Priority Mask
  \details Assigns the given value to the Priority Mask Register.
  \param [in]    priMask  Priority Mask
 */
 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
 {
  register uint32_t __regPriMask         __ASM("primask");
  __regPriMask = (priMask);
 }
 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
 /**
  \brief   Enable FIQ
  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
 #define __enable_fault_irq                __enable_fiq
 /**
  \brief   Disable FIQ
  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
 #define __disable_fault_irq               __disable_fiq
 /**
  \brief   Get Base Priority
  \details Returns the current value of the Base Priority register.
  \return               Base Priority register value
 */
 __STATIC_INLINE uint32_t  __get_BASEPRI(void)
 {
  register uint32_t __regBasePri         __ASM("basepri");
  return(__regBasePri);
 }
 /**
  \brief   Set Base Priority
  \details Assigns the given value to the Base Priority register.
  \param [in]    basePri  Base Priority value to set
 */
 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
 {
  register uint32_t __regBasePri         __ASM("basepri");
  __regBasePri = (basePri & 0xFFU);
 }
 /**
  \brief   Set Base Priority with condition
  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
           or the new value increases the BASEPRI priority level.
  \param [in]    basePri  Base Priority value to set
 */
 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
 {
  register uint32_t __regBasePriMax      __ASM("basepri_max");
  __regBasePriMax = (basePri & 0xFFU);
 }
 /**
  \brief   Get Fault Mask
  \details Returns the current value of the Fault Mask register.
  \return               Fault Mask register value
 */
 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
 {
  register uint32_t __regFaultMask       __ASM("faultmask");
  return(__regFaultMask);
 }
 /**
  \brief   Set Fault Mask
  \details Assigns the given value to the Fault Mask register.
  \param [in]    faultMask  Fault Mask value to set
 */
 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
  register uint32_t __regFaultMask       __ASM("faultmask");
  __regFaultMask = (faultMask & (uint32_t)1U);
 }
 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 /**
  \brief   Get FPSCR
  \details Returns the current value of the Floating Point Status/Control register.
  \return               Floating Point Status/Control register value
 */
 __STATIC_INLINE uint32_t __get_FPSCR(void)
 {
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
  register uint32_t __regfpscr         __ASM("fpscr");
  return(__regfpscr);
 #else
   return(0U);
 #endif
 }
 /**
  \brief   Set FPSCR
  \details Assigns the given value to the Floating Point Status/Control register.
  \param [in]    fpscr  Floating Point Status/Control value to set
 */
 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 {
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
  register uint32_t __regfpscr         __ASM("fpscr");
  __regfpscr = (fpscr);
 #else
  (void)fpscr;
 #endif
 }
 /*@} end of CMSIS_Core_RegAccFunctions */
 /* ##########################  Core Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
  Access to dedicated instructions
  @{
 */
 /**
  \brief   No Operation
  \details No Operation does nothing. This instruction can be used for code alignment purposes.
 */
 #define __NOP                             __nop
 /**
  \brief   Wait For Interrupt
  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
 */
 #define __WFI                             __wfi
 /**
  \brief   Wait For Event
  \details Wait For Event is a hint instruction that permits the processor to enter
           a low-power state until one of a number of events occurs.
 */
 #define __WFE                             __wfe
 /**
  \brief   Send Event
  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 */
 #define __SEV                             __sev
 /**
  \brief   Instruction Synchronization Barrier
  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
           so that all instructions following the ISB are fetched from cache or memory,
           after the instruction has been completed.
 */
 #define __ISB() do {\
                   __schedule_barrier();\
                   __isb(0xF);\
                   __schedule_barrier();\
                } while (0U)
 /**
  \brief   Data Synchronization Barrier
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
 #define __DSB() do {\
                   __schedule_barrier();\
                   __dsb(0xF);\
                   __schedule_barrier();\
                } while (0U)
 /**
  \brief   Data Memory Barrier
  \details Ensures the apparent order of the explicit memory operations before
           and after the instruction, without ensuring their completion.
 */
 #define __DMB() do {\
                   __schedule_barrier();\
                   __dmb(0xF);\
                   __schedule_barrier();\
                } while (0U)
 /**
  \brief   Reverse byte order (32 bit)
  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 #define __REV                             __rev
 /**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
 {
  rev16 r0, r0
  bx lr
 }
 #endif
 /**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
 {
  revsh r0, r0
  bx lr
 }
 #endif
 /**
  \brief   Rotate Right in unsigned value (32 bit)
  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
  \param [in]    op1  Value to rotate
  \param [in]    op2  Number of Bits to rotate
  \return               Rotated value
 */
 #define __ROR                             __ror
 /**
  \brief   Breakpoint
  \details Causes the processor to enter Debug state.
           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
  \param [in]    value  is ignored by the processor.
                 If required, a debugger can use it to store additional information about the breakpoint.
 */
 #define __BKPT(value)                       __breakpoint(value)
 /**
  \brief   Reverse bit order of value
  \details Reverses the bit order of the given value.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
  #define __RBIT                          __rbit
 #else
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 {
  uint32_t result;
  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
  result = value;                      /* r will be reversed bits of v; first get LSB of v */
  for (value >>= 1U; value != 0U; value >>= 1U)
  {
    result <<= 1U;
    result |= value & 1U;
    s--;
  }
  result <<= s;                        /* shift when v's highest bits are zero */
  return result;
 }
 #endif
 /**
  \brief   Count leading zeros
  \details Counts the number of leading zeros of a data value.
  \param [in]  value  Value to count the leading zeros
  \return             number of leading zeros in value
 */
 #define __CLZ                             __clz
 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
 /**
  \brief   LDR Exclusive (8 bit)
  \details Executes a exclusive LDR instruction for 8 bit value.
  \param [in]    ptr  Pointer to data
  \return             value of type uint8_t at (*ptr)
 */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
 #else
  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
 #endif
 /**
  \brief   LDR Exclusive (16 bit)
  \details Executes a exclusive LDR instruction for 16 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint16_t at (*ptr)
 */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
 #else
  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
 #endif
 /**
  \brief   LDR Exclusive (32 bit)
  \details Executes a exclusive LDR instruction for 32 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint32_t at (*ptr)
 */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
 #else
  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
 #endif
 /**
  \brief   STR Exclusive (8 bit)
  \details Executes a exclusive STR instruction for 8 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
 #else
  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 #endif
 /**
  \brief   STR Exclusive (16 bit)
  \details Executes a exclusive STR instruction for 16 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
 #else
  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 #endif
 /**
  \brief   STR Exclusive (32 bit)
  \details Executes a exclusive STR instruction for 32 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
 #else
  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 #endif
 /**
  \brief   Remove the exclusive lock
  \details Removes the exclusive lock which is created by LDREX.
 */
 #define __CLREX                           __clrex
 /**
  \brief   Signed Saturate
  \details Saturates a signed value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (1..32)
  \return             Saturated value
 */
 #define __SSAT                            __ssat
 /**
  \brief   Unsigned Saturate
  \details Saturates an unsigned value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (0..31)
  \return             Saturated value
 */
 #define __USAT                            __usat
 /**
  \brief   Rotate Right with Extend (32 bit)
  \details Moves each bit of a bitstring right by one bit.
           The carry input is shifted in at the left end of the bitstring.
  \param [in]    value  Value to rotate
  \return               Rotated value
 */
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
 {
  rrx r0, r0
  bx lr
 }
 #endif
 /**
  \brief   LDRT Unprivileged (8 bit)
  \details Executes a Unprivileged LDRT instruction for 8 bit value.
  \param [in]    ptr  Pointer to data
  \return             value of type uint8_t at (*ptr)
 */
 #define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
 /**
  \brief   LDRT Unprivileged (16 bit)
  \details Executes a Unprivileged LDRT instruction for 16 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint16_t at (*ptr)
 */
 #define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
 /**
  \brief   LDRT Unprivileged (32 bit)
  \details Executes a Unprivileged LDRT instruction for 32 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint32_t at (*ptr)
 */
 #define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
 /**
  \brief   STRT Unprivileged (8 bit)
  \details Executes a Unprivileged STRT instruction for 8 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
 #define __STRBT(value, ptr)               __strt(value, ptr)
 /**
  \brief   STRT Unprivileged (16 bit)
  \details Executes a Unprivileged STRT instruction for 16 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
 #define __STRHT(value, ptr)               __strt(value, ptr)
 /**
  \brief   STRT Unprivileged (32 bit)
  \details Executes a Unprivileged STRT instruction for 32 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
 */
 #define __STRT(value, ptr)                __strt(value, ptr)
 #else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 /**
  \brief   Signed Saturate
  \details Saturates a signed value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (1..32)
  \return             Saturated value
 */
 __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
 {
  if ((sat >= 1U) && (sat <= 32U))
  {
    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
    const int32_t min = -1 - max ;
    if (val > max)
    {
      return max;
    }
    else if (val < min)
    {
      return min;
    }
  }
  return val;
 }
 /**
  \brief   Unsigned Saturate
  \details Saturates an unsigned value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (0..31)
  \return             Saturated value
 */
 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
 {
  if (sat <= 31U)
  {
    const uint32_t max = ((1U << sat) - 1U);
    if (val > (int32_t)max)
    {
      return max;
    }
    else if (val < 0)
    {
      return 0U;
    }
  }
  return (uint32_t)val;
 }
 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 /* ###################  Compiler specific Intrinsics  ########################### */
 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
  Access to dedicated SIMD instructions
  @{
 */
 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
 #define __SADD8                           __sadd8
 #define __QADD8                           __qadd8
 #define __SHADD8                          __shadd8
 #define __UADD8                           __uadd8
 #define __UQADD8                          __uqadd8
 #define __UHADD8                          __uhadd8
 #define __SSUB8                           __ssub8
 #define __QSUB8                           __qsub8
 #define __SHSUB8                          __shsub8
 #define __USUB8                           __usub8
 #define __UQSUB8                          __uqsub8
 #define __UHSUB8                          __uhsub8
 #define __SADD16                          __sadd16
 #define __QADD16                          __qadd16
 #define __SHADD16                         __shadd16
 #define __UADD16                          __uadd16
 #define __UQADD16                         __uqadd16
 #define __UHADD16                         __uhadd16
 #define __SSUB16                          __ssub16
 #define __QSUB16                          __qsub16
 #define __SHSUB16                         __shsub16
 #define __USUB16                          __usub16
 #define __UQSUB16                         __uqsub16
 #define __UHSUB16                         __uhsub16
 #define __SASX                            __sasx
 #define __QASX                            __qasx
 #define __SHASX                           __shasx
 #define __UASX                            __uasx
 #define __UQASX                           __uqasx
 #define __UHASX                           __uhasx
 #define __SSAX                            __ssax
 #define __QSAX                            __qsax
 #define __SHSAX                           __shsax
 #define __USAX                            __usax
 #define __UQSAX                           __uqsax
 #define __UHSAX                           __uhsax
 #define __USAD8                           __usad8
 #define __USADA8                          __usada8
 #define __SSAT16                          __ssat16
 #define __USAT16                          __usat16
 #define __UXTB16                          __uxtb16
 #define __UXTAB16                         __uxtab16
 #define __SXTB16                          __sxtb16
 #define __SXTAB16                         __sxtab16
 #define __SMUAD                           __smuad
 #define __SMUADX                          __smuadx
 #define __SMLAD                           __smlad
 #define __SMLADX                          __smladx
 #define __SMLALD                          __smlald
 #define __SMLALDX                         __smlaldx
 #define __SMUSD                           __smusd
 #define __SMUSDX                          __smusdx
 #define __SMLSD                           __smlsd
 #define __SMLSDX                          __smlsdx
 #define __SMLSLD                          __smlsld
 #define __SMLSLDX                         __smlsldx
 #define __SEL                             __sel
 #define __QADD                            __qadd
 #define __QSUB                            __qsub
 #define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
 #define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
 #define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 /*@} end of group CMSIS_SIMD_intrinsics */
 #endif /* __CMSIS_ARMCC_H */
--- a/target_f1/Drivers/CMSIS/Core/Include/cmsis_armclang.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/cmsis_armclang.h
--- a/target_f1/Drivers/CMSIS/Core/Include/cmsis_compiler.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/cmsis_compiler.h
@ -1,266 +0,0 @@
 /**************************************************************************//**
 * @file     cmsis_compiler.h
 * @brief    CMSIS compiler generic header file
 * @version  V5.0.4
 * @date     10. January 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #ifndef __CMSIS_COMPILER_H
 #define __CMSIS_COMPILER_H
 #include <stdint.h>
 /*
 * Arm Compiler 4/5
 */
 #if   defined ( __CC_ARM )
  #include "cmsis_armcc.h"
 /*
 * Arm Compiler 6 (armclang)
 */
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #include "cmsis_armclang.h"
 /*
 * GNU Compiler
 */
 #elif defined ( __GNUC__ )
  #include "cmsis_gcc.h"
 /*
 * IAR Compiler
 */
 #elif defined ( __ICCARM__ )
  #include <cmsis_iccarm.h>
 /*
 * TI Arm Compiler
 */
 #elif defined ( __TI_ARM__ )
  #include <cmsis_ccs.h>
  #ifndef   __ASM
    #define __ASM                                  __asm
  #endif
  #ifndef   __INLINE
    #define __INLINE                               inline
  #endif
  #ifndef   __STATIC_INLINE
    #define __STATIC_INLINE                        static inline
  #endif
  #ifndef   __STATIC_FORCEINLINE
    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
  #endif
  #ifndef   __NO_RETURN
    #define __NO_RETURN                            __attribute__((noreturn))
  #endif
  #ifndef   __USED
    #define __USED                                 __attribute__((used))
  #endif
  #ifndef   __WEAK
    #define __WEAK                                 __attribute__((weak))
  #endif
  #ifndef   __PACKED
    #define __PACKED                               __attribute__((packed))
  #endif
  #ifndef   __PACKED_STRUCT
    #define __PACKED_STRUCT                        struct __attribute__((packed))
  #endif
  #ifndef   __PACKED_UNION
    #define __PACKED_UNION                         union __attribute__((packed))
  #endif
  #ifndef   __UNALIGNED_UINT32        /* deprecated */
    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  #endif
  #ifndef   __UNALIGNED_UINT16_WRITE
    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
  #endif
  #ifndef   __UNALIGNED_UINT16_READ
    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
  #endif
  #ifndef   __UNALIGNED_UINT32_WRITE
    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
  #endif
  #ifndef   __UNALIGNED_UINT32_READ
    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
  #endif
  #ifndef   __ALIGNED
    #define __ALIGNED(x)                           __attribute__((aligned(x)))
  #endif
  #ifndef   __RESTRICT
    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
    #define __RESTRICT
  #endif
 /*
 * TASKING Compiler
 */
 #elif defined ( __TASKING__ )
  /*
   * The CMSIS functions have been implemented as intrinsics in the compiler.
   * Please use "carm -?i" to get an up to date list of all intrinsics,
   * Including the CMSIS ones.
   */
  #ifndef   __ASM
    #define __ASM                                  __asm
  #endif
  #ifndef   __INLINE
    #define __INLINE                               inline
  #endif
  #ifndef   __STATIC_INLINE
    #define __STATIC_INLINE                        static inline
  #endif
  #ifndef   __STATIC_FORCEINLINE
    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
  #endif
  #ifndef   __NO_RETURN
    #define __NO_RETURN                            __attribute__((noreturn))
  #endif
  #ifndef   __USED
    #define __USED                                 __attribute__((used))
  #endif
  #ifndef   __WEAK
    #define __WEAK                                 __attribute__((weak))
  #endif
  #ifndef   __PACKED
    #define __PACKED                               __packed__
  #endif
  #ifndef   __PACKED_STRUCT
    #define __PACKED_STRUCT                        struct __packed__
  #endif
  #ifndef   __PACKED_UNION
    #define __PACKED_UNION                         union __packed__
  #endif
  #ifndef   __UNALIGNED_UINT32        /* deprecated */
    struct __packed__ T_UINT32 { uint32_t v; };
    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  #endif
  #ifndef   __UNALIGNED_UINT16_WRITE
    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
  #endif
  #ifndef   __UNALIGNED_UINT16_READ
    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
  #endif
  #ifndef   __UNALIGNED_UINT32_WRITE
    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
  #endif
  #ifndef   __UNALIGNED_UINT32_READ
    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
  #endif
  #ifndef   __ALIGNED
    #define __ALIGNED(x)              __align(x)
  #endif
  #ifndef   __RESTRICT
    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
    #define __RESTRICT
  #endif
 /*
 * COSMIC Compiler
 */
 #elif defined ( __CSMC__ )
   #include <cmsis_csm.h>
 #ifndef   __ASM
    #define __ASM                                  _asm
  #endif
  #ifndef   __INLINE
    #define __INLINE                               inline
  #endif
  #ifndef   __STATIC_INLINE
    #define __STATIC_INLINE                        static inline
  #endif
  #ifndef   __STATIC_FORCEINLINE
    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
  #endif
  #ifndef   __NO_RETURN
    // NO RETURN is automatically detected hence no warning here
    #define __NO_RETURN
  #endif
  #ifndef   __USED
    #warning No compiler specific solution for __USED. __USED is ignored.
    #define __USED
  #endif
  #ifndef   __WEAK
    #define __WEAK                                 __weak
  #endif
  #ifndef   __PACKED
    #define __PACKED                               @packed
  #endif
  #ifndef   __PACKED_STRUCT
    #define __PACKED_STRUCT                        @packed struct
  #endif
  #ifndef   __PACKED_UNION
    #define __PACKED_UNION                         @packed union
  #endif
  #ifndef   __UNALIGNED_UINT32        /* deprecated */
    @packed struct T_UINT32 { uint32_t v; };
    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  #endif
  #ifndef   __UNALIGNED_UINT16_WRITE
    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
  #endif
  #ifndef   __UNALIGNED_UINT16_READ
    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
  #endif
  #ifndef   __UNALIGNED_UINT32_WRITE
    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
  #endif
  #ifndef   __UNALIGNED_UINT32_READ
    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
  #endif
  #ifndef   __ALIGNED
    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
    #define __ALIGNED(x)
  #endif
  #ifndef   __RESTRICT
    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
    #define __RESTRICT
  #endif
 #else
  #error Unknown compiler.
 #endif
 #endif /* __CMSIS_COMPILER_H */
--- a/target_f1/Drivers/CMSIS/Core/Include/cmsis_gcc.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/cmsis_gcc.h
--- a/target_f1/Drivers/CMSIS/Core/Include/cmsis_iccarm.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/cmsis_iccarm.h
@ -1,935 +0,0 @@
 /**************************************************************************//**
 * @file     cmsis_iccarm.h
 * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
 * @version  V5.0.7
 * @date     19. June 2018
 ******************************************************************************/
 //------------------------------------------------------------------------------
 //
 // Copyright (c) 2017-2018 IAR Systems
 //
 // Licensed under the Apache License, Version 2.0 (the "License")
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //     http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
 //
 //------------------------------------------------------------------------------
 #ifndef __CMSIS_ICCARM_H__
 #define __CMSIS_ICCARM_H__
 #ifndef __ICCARM__
  #error This file should only be compiled by ICCARM
 #endif
 #pragma system_include
 #define __IAR_FT _Pragma("inline=forced") __intrinsic
 #if (__VER__ >= 8000000)
  #define __ICCARM_V8 1
 #else
  #define __ICCARM_V8 0
 #endif
 #ifndef __ALIGNED
  #if __ICCARM_V8
    #define __ALIGNED(x) __attribute__((aligned(x)))
  #elif (__VER__ >= 7080000)
    /* Needs IAR language extensions */
    #define __ALIGNED(x) __attribute__((aligned(x)))
  #else
    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
    #define __ALIGNED(x)
  #endif
 #endif
 /* Define compiler macros for CPU architecture, used in CMSIS 5.
 */
 #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
 /* Macros already defined */
 #else
  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
    #define __ARM_ARCH_8M_MAIN__ 1
  #elif defined(__ARM8M_BASELINE__)
    #define __ARM_ARCH_8M_BASE__ 1
  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
    #if __ARM_ARCH == 6
      #define __ARM_ARCH_6M__ 1
    #elif __ARM_ARCH == 7
      #if __ARM_FEATURE_DSP
        #define __ARM_ARCH_7EM__ 1
      #else
        #define __ARM_ARCH_7M__ 1
      #endif
    #endif /* __ARM_ARCH */
  #endif /* __ARM_ARCH_PROFILE == 'M' */
 #endif
 /* Alternativ core deduction for older ICCARM's */
 #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
    #define __ARM_ARCH_6M__ 1
  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
    #define __ARM_ARCH_7M__ 1
  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
    #define __ARM_ARCH_7EM__  1
  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
    #define __ARM_ARCH_8M_BASE__ 1
  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
    #define __ARM_ARCH_8M_MAIN__ 1
  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
    #define __ARM_ARCH_8M_MAIN__ 1
  #else
    #error "Unknown target."
  #endif
 #endif
 #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
  #define __IAR_M0_FAMILY  1
 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
  #define __IAR_M0_FAMILY  1
 #else
  #define __IAR_M0_FAMILY  0
 #endif
 #ifndef __ASM
  #define __ASM __asm
 #endif
 #ifndef __INLINE
  #define __INLINE inline
 #endif
 #ifndef   __NO_RETURN
  #if __ICCARM_V8
    #define __NO_RETURN __attribute__((__noreturn__))
  #else
    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
  #endif
 #endif
 #ifndef   __PACKED
  #if __ICCARM_V8
    #define __PACKED __attribute__((packed, aligned(1)))
  #else
    /* Needs IAR language extensions */
    #define __PACKED __packed
  #endif
 #endif
 #ifndef   __PACKED_STRUCT
  #if __ICCARM_V8
    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
  #else
    /* Needs IAR language extensions */
    #define __PACKED_STRUCT __packed struct
  #endif
 #endif
 #ifndef   __PACKED_UNION
  #if __ICCARM_V8
    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
  #else
    /* Needs IAR language extensions */
    #define __PACKED_UNION __packed union
  #endif
 #endif
 #ifndef   __RESTRICT
  #define __RESTRICT            __restrict
 #endif
 #ifndef   __STATIC_INLINE
  #define __STATIC_INLINE       static inline
 #endif
 #ifndef   __FORCEINLINE
  #define __FORCEINLINE         _Pragma("inline=forced")
 #endif
 #ifndef   __STATIC_FORCEINLINE
  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
 #endif
 #ifndef __UNALIGNED_UINT16_READ
 #pragma language=save
 #pragma language=extended
 __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
 {
  return *(__packed uint16_t*)(ptr);
 }
 #pragma language=restore
 #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
 #endif
 #ifndef __UNALIGNED_UINT16_WRITE
 #pragma language=save
 #pragma language=extended
 __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
 {
  *(__packed uint16_t*)(ptr) = val;;
 }
 #pragma language=restore
 #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
 #endif
 #ifndef __UNALIGNED_UINT32_READ
 #pragma language=save
 #pragma language=extended
 __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
 {
  return *(__packed uint32_t*)(ptr);
 }
 #pragma language=restore
 #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
 #endif
 #ifndef __UNALIGNED_UINT32_WRITE
 #pragma language=save
 #pragma language=extended
 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
 {
  *(__packed uint32_t*)(ptr) = val;;
 }
 #pragma language=restore
 #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
 #endif
 #ifndef __UNALIGNED_UINT32   /* deprecated */
 #pragma language=save
 #pragma language=extended
 __packed struct  __iar_u32 { uint32_t v; };
 #pragma language=restore
 #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
 #endif
 #ifndef   __USED
  #if __ICCARM_V8
    #define __USED __attribute__((used))
  #else
    #define __USED _Pragma("__root")
  #endif
 #endif
 #ifndef   __WEAK
  #if __ICCARM_V8
    #define __WEAK __attribute__((weak))
  #else
    #define __WEAK _Pragma("__weak")
  #endif
 #endif
 #ifndef __ICCARM_INTRINSICS_VERSION__
  #define __ICCARM_INTRINSICS_VERSION__  0
 #endif
 #if __ICCARM_INTRINSICS_VERSION__ == 2
  #if defined(__CLZ)
    #undef __CLZ
  #endif
  #if defined(__REVSH)
    #undef __REVSH
  #endif
  #if defined(__RBIT)
    #undef __RBIT
  #endif
  #if defined(__SSAT)
    #undef __SSAT
  #endif
  #if defined(__USAT)
    #undef __USAT
  #endif
  #include "iccarm_builtin.h"
  #define __disable_fault_irq __iar_builtin_disable_fiq
  #define __disable_irq       __iar_builtin_disable_interrupt
  #define __enable_fault_irq  __iar_builtin_enable_fiq
  #define __enable_irq        __iar_builtin_enable_interrupt
  #define __arm_rsr           __iar_builtin_rsr
  #define __arm_wsr           __iar_builtin_wsr
  #define __get_APSR()                (__arm_rsr("APSR"))
  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
  #else
    #define __get_FPSCR()             ( 0 )
    #define __set_FPSCR(VALUE)        ((void)VALUE)
  #endif
  #define __get_IPSR()                (__arm_rsr("IPSR"))
  #define __get_MSP()                 (__arm_rsr("MSP"))
  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
    // without main extensions, the non-secure MSPLIM is RAZ/WI
    #define __get_MSPLIM()            (0U)
  #else
    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
  #endif
  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
  #define __get_PSP()                 (__arm_rsr("PSP"))
  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
    // without main extensions, the non-secure PSPLIM is RAZ/WI
    #define __get_PSPLIM()            (0U)
  #else
    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
  #endif
  #define __get_xPSR()                (__arm_rsr("xPSR"))
  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
    // without main extensions, the non-secure MSPLIM is RAZ/WI
    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
  #else
    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
  #endif
  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
    // without main extensions, the non-secure PSPLIM is RAZ/WI
    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
  #else
    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
  #endif
  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
    // without main extensions, the non-secure PSPLIM is RAZ/WI
    #define __TZ_get_PSPLIM_NS()      (0U)
    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
  #else
    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
  #endif
  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
  #define __NOP     __iar_builtin_no_operation
  #define __CLZ     __iar_builtin_CLZ
  #define __CLREX   __iar_builtin_CLREX
  #define __DMB     __iar_builtin_DMB
  #define __DSB     __iar_builtin_DSB
  #define __ISB     __iar_builtin_ISB
  #define __LDREXB  __iar_builtin_LDREXB
  #define __LDREXH  __iar_builtin_LDREXH
  #define __LDREXW  __iar_builtin_LDREX
  #define __RBIT    __iar_builtin_RBIT
  #define __REV     __iar_builtin_REV
  #define __REV16   __iar_builtin_REV16
  __IAR_FT int16_t __REVSH(int16_t val)
  {
    return (int16_t) __iar_builtin_REVSH(val);
  }
  #define __ROR     __iar_builtin_ROR
  #define __RRX     __iar_builtin_RRX
  #define __SEV     __iar_builtin_SEV
  #if !__IAR_M0_FAMILY
    #define __SSAT    __iar_builtin_SSAT
  #endif
  #define __STREXB  __iar_builtin_STREXB
  #define __STREXH  __iar_builtin_STREXH
  #define __STREXW  __iar_builtin_STREX
  #if !__IAR_M0_FAMILY
    #define __USAT    __iar_builtin_USAT
  #endif
  #define __WFE     __iar_builtin_WFE
  #define __WFI     __iar_builtin_WFI
  #if __ARM_MEDIA__
    #define __SADD8   __iar_builtin_SADD8
    #define __QADD8   __iar_builtin_QADD8
    #define __SHADD8  __iar_builtin_SHADD8
    #define __UADD8   __iar_builtin_UADD8
    #define __UQADD8  __iar_builtin_UQADD8
    #define __UHADD8  __iar_builtin_UHADD8
    #define __SSUB8   __iar_builtin_SSUB8
    #define __QSUB8   __iar_builtin_QSUB8
    #define __SHSUB8  __iar_builtin_SHSUB8
    #define __USUB8   __iar_builtin_USUB8
    #define __UQSUB8  __iar_builtin_UQSUB8
    #define __UHSUB8  __iar_builtin_UHSUB8
    #define __SADD16  __iar_builtin_SADD16
    #define __QADD16  __iar_builtin_QADD16
    #define __SHADD16 __iar_builtin_SHADD16
    #define __UADD16  __iar_builtin_UADD16
    #define __UQADD16 __iar_builtin_UQADD16
    #define __UHADD16 __iar_builtin_UHADD16
    #define __SSUB16  __iar_builtin_SSUB16
    #define __QSUB16  __iar_builtin_QSUB16
    #define __SHSUB16 __iar_builtin_SHSUB16
    #define __USUB16  __iar_builtin_USUB16
    #define __UQSUB16 __iar_builtin_UQSUB16
    #define __UHSUB16 __iar_builtin_UHSUB16
    #define __SASX    __iar_builtin_SASX
    #define __QASX    __iar_builtin_QASX
    #define __SHASX   __iar_builtin_SHASX
    #define __UASX    __iar_builtin_UASX
    #define __UQASX   __iar_builtin_UQASX
    #define __UHASX   __iar_builtin_UHASX
    #define __SSAX    __iar_builtin_SSAX
    #define __QSAX    __iar_builtin_QSAX
    #define __SHSAX   __iar_builtin_SHSAX
    #define __USAX    __iar_builtin_USAX
    #define __UQSAX   __iar_builtin_UQSAX
    #define __UHSAX   __iar_builtin_UHSAX
    #define __USAD8   __iar_builtin_USAD8
    #define __USADA8  __iar_builtin_USADA8
    #define __SSAT16  __iar_builtin_SSAT16
    #define __USAT16  __iar_builtin_USAT16
    #define __UXTB16  __iar_builtin_UXTB16
    #define __UXTAB16 __iar_builtin_UXTAB16
    #define __SXTB16  __iar_builtin_SXTB16
    #define __SXTAB16 __iar_builtin_SXTAB16
    #define __SMUAD   __iar_builtin_SMUAD
    #define __SMUADX  __iar_builtin_SMUADX
    #define __SMMLA   __iar_builtin_SMMLA
    #define __SMLAD   __iar_builtin_SMLAD
    #define __SMLADX  __iar_builtin_SMLADX
    #define __SMLALD  __iar_builtin_SMLALD
    #define __SMLALDX __iar_builtin_SMLALDX
    #define __SMUSD   __iar_builtin_SMUSD
    #define __SMUSDX  __iar_builtin_SMUSDX
    #define __SMLSD   __iar_builtin_SMLSD
    #define __SMLSDX  __iar_builtin_SMLSDX
    #define __SMLSLD  __iar_builtin_SMLSLD
    #define __SMLSLDX __iar_builtin_SMLSLDX
    #define __SEL     __iar_builtin_SEL
    #define __QADD    __iar_builtin_QADD
    #define __QSUB    __iar_builtin_QSUB
    #define __PKHBT   __iar_builtin_PKHBT
    #define __PKHTB   __iar_builtin_PKHTB
  #endif
 #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
  #if __IAR_M0_FAMILY
   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
    #define __CLZ  __cmsis_iar_clz_not_active
    #define __SSAT __cmsis_iar_ssat_not_active
    #define __USAT __cmsis_iar_usat_not_active
    #define __RBIT __cmsis_iar_rbit_not_active
    #define __get_APSR  __cmsis_iar_get_APSR_not_active
  #endif
  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
  #endif
  #ifdef __INTRINSICS_INCLUDED
  #error intrinsics.h is already included previously!
  #endif
  #include <intrinsics.h>
  #if __IAR_M0_FAMILY
   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
    #undef __CLZ
    #undef __SSAT
    #undef __USAT
    #undef __RBIT
    #undef __get_APSR
    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
    {
      if (data == 0U) { return 32U; }
      uint32_t count = 0U;
      uint32_t mask = 0x80000000U;
      while ((data & mask) == 0U)
      {
        count += 1U;
        mask = mask >> 1U;
      }
      return count;
    }
    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
    {
      uint8_t sc = 31U;
      uint32_t r = v;
      for (v >>= 1U; v; v >>= 1U)
      {
        r <<= 1U;
        r |= v & 1U;
        sc--;
      }
      return (r << sc);
    }
    __STATIC_INLINE  uint32_t __get_APSR(void)
    {
      uint32_t res;
      __asm("MRS      %0,APSR" : "=r" (res));
      return res;
    }
  #endif
  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
    #undef __get_FPSCR
    #undef __set_FPSCR
    #define __get_FPSCR()       (0)
    #define __set_FPSCR(VALUE)  ((void)VALUE)
  #endif
  #pragma diag_suppress=Pe940
  #pragma diag_suppress=Pe177
  #define __enable_irq    __enable_interrupt
  #define __disable_irq   __disable_interrupt
  #define __NOP           __no_operation
  #define __get_xPSR      __get_PSR
  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
    {
      return __LDREX((unsigned long *)ptr);
    }
    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
    {
      return __STREX(value, (unsigned long *)ptr);
    }
  #endif
  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
  #if (__CORTEX_M >= 0x03)
    __IAR_FT uint32_t __RRX(uint32_t value)
    {
      uint32_t result;
      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
      return(result);
    }
    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
    {
      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
    }
    #define __enable_fault_irq  __enable_fiq
    #define __disable_fault_irq __disable_fiq
  #endif /* (__CORTEX_M >= 0x03) */
  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
  {
    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
  }
  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
   __IAR_FT uint32_t __get_MSPLIM(void)
    {
      uint32_t res;
    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
      // without main extensions, the non-secure MSPLIM is RAZ/WI
      res = 0U;
    #else
      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
    #endif
      return res;
    }
    __IAR_FT void   __set_MSPLIM(uint32_t value)
    {
    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
      // without main extensions, the non-secure MSPLIM is RAZ/WI
      (void)value;
    #else
      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
    #endif
    }
    __IAR_FT uint32_t __get_PSPLIM(void)
    {
      uint32_t res;
    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
      // without main extensions, the non-secure PSPLIM is RAZ/WI
      res = 0U;
    #else
      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
    #endif
      return res;
    }
    __IAR_FT void   __set_PSPLIM(uint32_t value)
    {
    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
      // without main extensions, the non-secure PSPLIM is RAZ/WI
      (void)value;
    #else
      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
    #endif
    }
    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
    {
      uint32_t res;
      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
      return res;
    }
    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
    {
      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
    }
    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
    {
      uint32_t res;
      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
      return res;
    }
    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
    {
      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
    }
    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
    {
      uint32_t res;
      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
      return res;
    }
    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
    {
      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
    }
    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
    {
      uint32_t res;
      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
      return res;
    }
    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
    {
      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
    }
    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
    {
      uint32_t res;
      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
      return res;
    }
    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
    {
      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
    }
    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
    {
      uint32_t res;
      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
      return res;
    }
    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
    {
      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
    }
    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
    {
      uint32_t res;
      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
      return res;
    }
    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
    {
      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
    }
    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
    {
      uint32_t res;
    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
      // without main extensions, the non-secure PSPLIM is RAZ/WI
      res = 0U;
    #else
      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
    #endif
      return res;
    }
    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
    {
    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
      // without main extensions, the non-secure PSPLIM is RAZ/WI
      (void)value;
    #else
      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
    #endif
    }
    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
    {
      uint32_t res;
      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
      return res;
    }
    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
    {
      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
    }
  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
 #endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
 #define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
 #if __IAR_M0_FAMILY
  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
  {
    if ((sat >= 1U) && (sat <= 32U))
    {
      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
      const int32_t min = -1 - max ;
      if (val > max)
      {
        return max;
      }
      else if (val < min)
      {
        return min;
      }
    }
    return val;
  }
  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
  {
    if (sat <= 31U)
    {
      const uint32_t max = ((1U << sat) - 1U);
      if (val > (int32_t)max)
      {
        return max;
      }
      else if (val < 0)
      {
        return 0U;
      }
    }
    return (uint32_t)val;
  }
 #endif
 #if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
  {
    uint32_t res;
    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
    return ((uint8_t)res);
  }
  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
  {
    uint32_t res;
    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
    return ((uint16_t)res);
  }
  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
  {
    uint32_t res;
    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
    return res;
  }
  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
  {
    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
  }
  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
  {
    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
  }
  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
  {
    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
  }
 #endif /* (__CORTEX_M >= 0x03) */
 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
  {
    uint32_t res;
    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
    return ((uint8_t)res);
  }
  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
  {
    uint32_t res;
    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
    return ((uint16_t)res);
  }
  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
  {
    uint32_t res;
    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
    return res;
  }
  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
  {
    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
  }
  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
  {
    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
  }
  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
  {
    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
  }
  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
  {
    uint32_t res;
    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
    return ((uint8_t)res);
  }
  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
  {
    uint32_t res;
    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
    return ((uint16_t)res);
  }
  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
  {
    uint32_t res;
    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
    return res;
  }
  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
  {
    uint32_t res;
    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
    return res;
  }
  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
  {
    uint32_t res;
    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
    return res;
  }
  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
  {
    uint32_t res;
    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
    return res;
  }
 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
 #undef __IAR_FT
 #undef __IAR_M0_FAMILY
 #undef __ICCARM_V8
 #pragma diag_default=Pe940
 #pragma diag_default=Pe177
 #endif /* __CMSIS_ICCARM_H__ */
--- a/target_f1/Drivers/CMSIS/Core/Include/cmsis_version.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/cmsis_version.h
@ -1,39 +0,0 @@
 /**************************************************************************//**
 * @file     cmsis_version.h
 * @brief    CMSIS Core(M) Version definitions
 * @version  V5.0.2
 * @date     19. April 2017
 ******************************************************************************/
 /*
 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #if   defined ( __ICCARM__ )
  #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
  #pragma clang system_header   /* treat file as system include file */
 #endif
 #ifndef __CMSIS_VERSION_H
 #define __CMSIS_VERSION_H
 /*  CMSIS Version definitions */
 #define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
 #define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
 #define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
 #endif
--- a/target_f1/Drivers/CMSIS/Core/Include/core_armv8mbl.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/core_armv8mbl.h
--- a/target_f1/Drivers/CMSIS/Core/Include/core_armv8mml.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/core_armv8mml.h
--- a/target_f1/Drivers/CMSIS/Core/Include/core_cm0.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/core_cm0.h
@ -1,949 +0,0 @@
 /**************************************************************************//**
 * @file     core_cm0.h
 * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
 * @version  V5.0.5
 * @date     28. May 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #if   defined ( __ICCARM__ )
  #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
  #pragma clang system_header   /* treat file as system include file */
 #endif
 #ifndef __CORE_CM0_H_GENERIC
 #define __CORE_CM0_H_GENERIC
 #include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 /**
  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  CMSIS violates the following MISRA-C:2004 rules:
   \li Required Rule 8.5, object/function definition in header file.<br>
     Function definitions in header files are used to allow 'inlining'.
   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
     Unions are used for effective representation of core registers.
   \li Advisory Rule 19.7, Function-like macro defined.<br>
     Function-like macros are used to allow more efficient code.
 */
 /*******************************************************************************
 *                 CMSIS definitions
 ******************************************************************************/
 /**
  \ingroup Cortex_M0
  @{
 */
 #include "cmsis_version.h"
 /*  CMSIS CM0 definitions */
 #define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
 #define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
 #define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
 #define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
 /** __FPU_USED indicates whether an FPU is used or not.
    This core does not support an FPU at all
 */
 #define __FPU_USED       0U
 #if defined ( __CC_ARM )
  #if defined __TARGET_FPU_VFP
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #if defined __ARM_PCS_VFP
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #elif defined ( __GNUC__ )
  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #elif defined ( __ICCARM__ )
  #if defined __ARMVFP__
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #elif defined ( __TI_ARM__ )
  #if defined __TI_VFP_SUPPORT__
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #elif defined ( __TASKING__ )
  #if defined __FPU_VFP__
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #elif defined ( __CSMC__ )
  #if ( __CSMC__ & 0x400U)
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #endif
 #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
 #ifdef __cplusplus
 }
 #endif
 #endif /* __CORE_CM0_H_GENERIC */
 #ifndef __CMSIS_GENERIC
 #ifndef __CORE_CM0_H_DEPENDANT
 #define __CORE_CM0_H_DEPENDANT
 #ifdef __cplusplus
 extern "C" {
 #endif
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
  #ifndef __CM0_REV
    #define __CM0_REV               0x0000U
    #warning "__CM0_REV not defined in device header file; using default!"
  #endif
  #ifndef __NVIC_PRIO_BITS
    #define __NVIC_PRIO_BITS          2U
    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
  #endif
  #ifndef __Vendor_SysTickConfig
    #define __Vendor_SysTickConfig    0U
    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
  #endif
 #endif
 /* IO definitions (access restrictions to peripheral registers) */
 /**
    \defgroup CMSIS_glob_defs CMSIS Global Defines
    <strong>IO Type Qualifiers</strong> are used
    \li to specify the access to peripheral variables.
    \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
  #define   __I     volatile             /*!< Defines 'read only' permissions */
 #else
  #define   __I     volatile const       /*!< Defines 'read only' permissions */
 #endif
 #define     __O     volatile             /*!< Defines 'write only' permissions */
 #define     __IO    volatile             /*!< Defines 'read / write' permissions */
 /* following defines should be used for structure members */
 #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
 #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
 #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 /*@} end of group Cortex_M0 */
 /*******************************************************************************
 *                 Register Abstraction
  Core Register contain:
  - Core Register
  - Core NVIC Register
  - Core SCB Register
  - Core SysTick Register
 ******************************************************************************/
 /**
  \defgroup CMSIS_core_register Defines and Type Definitions
  \brief Type definitions and defines for Cortex-M processor based devices.
 */
 /**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_CORE  Status and Control Registers
  \brief      Core Register type definitions.
  @{
 */
 /**
  \brief  Union type to access the Application Program Status Register (APSR).
 */
 typedef union
 {
  struct
  {
    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
  } b;                                   /*!< Structure used for bit  access */
  uint32_t w;                            /*!< Type      used for word access */
 } APSR_Type;
 /* APSR Register Definitions */
 #define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
 #define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
 #define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
 #define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
 /**
  \brief  Union type to access the Interrupt Program Status Register (IPSR).
 */
 typedef union
 {
  struct
  {
    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
  } b;                                   /*!< Structure used for bit  access */
  uint32_t w;                            /*!< Type      used for word access */
 } IPSR_Type;
 /* IPSR Register Definitions */
 #define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 /**
  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 */
 typedef union
 {
  struct
  {
    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
  } b;                                   /*!< Structure used for bit  access */
  uint32_t w;                            /*!< Type      used for word access */
 } xPSR_Type;
 /* xPSR Register Definitions */
 #define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
 #define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
 #define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
 #define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
 #define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 #define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 /**
  \brief  Union type to access the Control Registers (CONTROL).
 */
 typedef union
 {
  struct
  {
    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
  } b;                                   /*!< Structure used for bit  access */
  uint32_t w;                            /*!< Type      used for word access */
 } CONTROL_Type;
 /* CONTROL Register Definitions */
 #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
 /*@} end of group CMSIS_CORE */
 /**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
  \brief      Type definitions for the NVIC Registers
  @{
 */
 /**
  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 */
 typedef struct
 {
  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
        uint32_t RESERVED0[31U];
  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
        uint32_t RSERVED1[31U];
  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
        uint32_t RESERVED2[31U];
  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
        uint32_t RESERVED3[31U];
        uint32_t RESERVED4[64U];
  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
 }  NVIC_Type;
 /*@} end of group CMSIS_NVIC */
 /**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCB     System Control Block (SCB)
  \brief    Type definitions for the System Control Block Registers
  @{
 */
 /**
  \brief  Structure type to access the System Control Block (SCB).
 */
 typedef struct
 {
  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
        uint32_t RESERVED0;
  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
        uint32_t RESERVED1;
  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
 } SCB_Type;
 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
 /* SCB Interrupt Control State Register Definitions */
 #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 /* SCB System Control Register Definitions */
 #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 /* SCB Configuration Control Register Definitions */
 #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 /* SCB System Handler Control and State Register Definitions */
 #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 /*@} end of group CMSIS_SCB */
 /**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
  \brief    Type definitions for the System Timer Registers.
  @{
 */
 /**
  \brief  Structure type to access the System Timer (SysTick).
 */
 typedef struct
 {
  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 } SysTick_Type;
 /* SysTick Control / Status Register Definitions */
 #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
 /* SysTick Reload Register Definitions */
 #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
 /* SysTick Current Register Definitions */
 #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
 /* SysTick Calibration Register Definitions */
 #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
 /*@} end of group CMSIS_SysTick */
 /**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
            Therefore they are not covered by the Cortex-M0 header file.
  @{
 */
 /*@} end of group CMSIS_CoreDebug */
 /**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_bitfield     Core register bit field macros
  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
  @{
 */
 /**
  \brief   Mask and shift a bit field value for use in a register bit range.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
  \return           Masked and shifted value.
 */
 #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
 /**
  \brief     Mask and shift a register value to extract a bit filed value.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
  \return           Masked and shifted bit field value.
 */
 #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
 /*@} end of group CMSIS_core_bitfield */
 /**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_base     Core Definitions
  \brief      Definitions for base addresses, unions, and structures.
  @{
 */
 /* Memory mapping of Core Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
 /*@} */
 /*******************************************************************************
 *                Hardware Abstraction Layer
  Core Function Interface contains:
  - Core NVIC Functions
  - Core SysTick Functions
  - Core Register Access Functions
 ******************************************************************************/
 /**
  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 /* ##########################   NVIC functions  #################################### */
 /**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
  \brief    Functions that manage interrupts and exceptions via the NVIC.
  @{
 */
 #ifdef CMSIS_NVIC_VIRTUAL
  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
  #endif
  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
 #else
  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
 /*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
  #define NVIC_SetPriority            __NVIC_SetPriority
  #define NVIC_GetPriority            __NVIC_GetPriority
  #define NVIC_SystemReset            __NVIC_SystemReset
 #endif /* CMSIS_NVIC_VIRTUAL */
 #ifdef CMSIS_VECTAB_VIRTUAL
  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
  #endif
  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
 #else
  #define NVIC_SetVector              __NVIC_SetVector
  #define NVIC_GetVector              __NVIC_GetVector
 #endif  /* (CMSIS_VECTAB_VIRTUAL) */
 #define NVIC_USER_IRQ_OFFSET          16
 /* The following EXC_RETURN values are saved the LR on exception entry */
 #define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
 #define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
 #define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
 /* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
 #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
 #define __NVIC_SetPriorityGrouping(X) (void)(X)
 #define __NVIC_GetPriorityGrouping()  (0U)
 /**
  \brief   Enable Interrupt
  \details Enables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  }
 }
 /**
  \brief   Get Interrupt Enable status
  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \return             0  Interrupt is not enabled.
  \return             1  Interrupt is enabled.
  \note    IRQn must not be negative.
 */
 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
  }
  else
  {
    return(0U);
  }
 }
 /**
  \brief   Disable Interrupt
  \details Disables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    __DSB();
    __ISB();
  }
 }
 /**
  \brief   Get Pending Interrupt
  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
  \param [in]      IRQn  Device specific interrupt number.
  \return             0  Interrupt status is not pending.
  \return             1  Interrupt status is pending.
  \note    IRQn must not be negative.
 */
 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
  }
  else
  {
    return(0U);
  }
 }
 /**
  \brief   Set Pending Interrupt
  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  }
 }
 /**
  \brief   Clear Pending Interrupt
  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  }
 }
 /**
  \brief   Set Interrupt Priority
  \details Sets the priority of a device specific interrupt or a processor exception.
           The interrupt number can be positive to specify a device specific interrupt,
           or negative to specify a processor exception.
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  }
  else
  {
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  }
 }
 /**
  \brief   Get Interrupt Priority
  \details Reads the priority of a device specific interrupt or a processor exception.
           The interrupt number can be positive to specify a device specific interrupt,
           or negative to specify a processor exception.
  \param [in]   IRQn  Interrupt number.
  \return             Interrupt Priority.
                      Value is aligned automatically to the implemented priority bits of the microcontroller.
 */
 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  }
  else
  {
    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  }
 }
 /**
  \brief   Encode Priority
  \details Encodes the priority for an interrupt with the given priority group,
           preemptive priority value, and subpriority value.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]     PriorityGroup  Used priority group.
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
         );
 }
 /**
  \brief   Decode Priority
  \details Decodes an interrupt priority value with a given priority group to
           preemptive priority value and subpriority value.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
  \param [in]     PriorityGroup  Used priority group.
  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
  \param [out]     pSubPriority  Subpriority value (starting from 0).
 */
 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
 {
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
 }
 /**
  \brief   Set Interrupt Vector
  \details Sets an interrupt vector in SRAM based interrupt vector table.
           The interrupt number can be positive to specify a device specific interrupt,
           or negative to specify a processor exception.
           Address 0 must be mapped to SRAM.
  \param [in]   IRQn      Interrupt number
  \param [in]   vector    Address of interrupt handler function
 */
 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
 {
  uint32_t *vectors = (uint32_t *)0x0U;
  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
 }
 /**
  \brief   Get Interrupt Vector
  \details Reads an interrupt vector from interrupt vector table.
           The interrupt number can be positive to specify a device specific interrupt,
           or negative to specify a processor exception.
  \param [in]   IRQn      Interrupt number.
  \return                 Address of interrupt handler function
 */
 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
 {
  uint32_t *vectors = (uint32_t *)0x0U;
  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
 }
 /**
  \brief   System Reset
  \details Initiates a system reset request to reset the MCU.
 */
 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 {
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                 SCB_AIRCR_SYSRESETREQ_Msk);
  __DSB();                                                          /* Ensure completion of memory access */
  for(;;)                                                           /* wait until reset */
  {
    __NOP();
  }
 }
 /*@} end of CMSIS_Core_NVICFunctions */
 /* ##########################  FPU functions  #################################### */
 /**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_FpuFunctions FPU Functions
  \brief    Function that provides FPU type.
  @{
 */
 /**
  \brief   get FPU type
  \details returns the FPU type
  \returns
   - \b  0: No FPU
   - \b  1: Single precision FPU
   - \b  2: Double + Single precision FPU
 */
 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
 {
    return 0U;           /* No FPU */
 }
 /*@} end of CMSIS_Core_FpuFunctions */
 /* ##################################    SysTick function  ############################################ */
 /**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
  \brief    Functions that configure the System.
  @{
 */
 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
 /**
  \brief   System Tick Configuration
  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
           Counter is in free running mode to generate periodic interrupts.
  \param [in]  ticks  Number of ticks between two interrupts.
  \return          0  Function succeeded.
  \return          1  Function failed.
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
  {
    return (1UL);                                                   /* Reload value impossible */
  }
  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 }
 #endif
 /*@} end of CMSIS_Core_SysTickFunctions */
 #ifdef __cplusplus
 }
 #endif
 #endif /* __CORE_CM0_H_DEPENDANT */
 #endif /* __CMSIS_GENERIC */
--- a/target_f1/Drivers/CMSIS/Core/Include/core_cm0plus.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/core_cm0plus.h
--- a/target_f1/Drivers/CMSIS/Core/Include/core_cm1.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/core_cm1.h
@ -1,976 +0,0 @@
 /**************************************************************************//**
 * @file     core_cm1.h
 * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
 * @version  V1.0.0
 * @date     23. July 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #if   defined ( __ICCARM__ )
  #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
  #pragma clang system_header   /* treat file as system include file */
 #endif
 #ifndef __CORE_CM1_H_GENERIC
 #define __CORE_CM1_H_GENERIC
 #include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 /**
  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  CMSIS violates the following MISRA-C:2004 rules:
   \li Required Rule 8.5, object/function definition in header file.<br>
     Function definitions in header files are used to allow 'inlining'.
   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
     Unions are used for effective representation of core registers.
   \li Advisory Rule 19.7, Function-like macro defined.<br>
     Function-like macros are used to allow more efficient code.
 */
 /*******************************************************************************
 *                 CMSIS definitions
 ******************************************************************************/
 /**
  \ingroup Cortex_M1
  @{
 */
 #include "cmsis_version.h"
 /*  CMSIS CM1 definitions */
 #define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
 #define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
 #define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
 #define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
 /** __FPU_USED indicates whether an FPU is used or not.
    This core does not support an FPU at all
 */
 #define __FPU_USED       0U
 #if defined ( __CC_ARM )
  #if defined __TARGET_FPU_VFP
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #if defined __ARM_PCS_VFP
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #elif defined ( __GNUC__ )
  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #elif defined ( __ICCARM__ )
  #if defined __ARMVFP__
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #elif defined ( __TI_ARM__ )
  #if defined __TI_VFP_SUPPORT__
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #elif defined ( __TASKING__ )
  #if defined __FPU_VFP__
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #elif defined ( __CSMC__ )
  #if ( __CSMC__ & 0x400U)
    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  #endif
 #endif
 #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
 #ifdef __cplusplus
 }
 #endif
 #endif /* __CORE_CM1_H_GENERIC */
 #ifndef __CMSIS_GENERIC
 #ifndef __CORE_CM1_H_DEPENDANT
 #define __CORE_CM1_H_DEPENDANT
 #ifdef __cplusplus
 extern "C" {
 #endif
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
  #ifndef __CM1_REV
    #define __CM1_REV               0x0100U
    #warning "__CM1_REV not defined in device header file; using default!"
  #endif
  #ifndef __NVIC_PRIO_BITS
    #define __NVIC_PRIO_BITS          2U
    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
  #endif
  #ifndef __Vendor_SysTickConfig
    #define __Vendor_SysTickConfig    0U
    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
  #endif
 #endif
 /* IO definitions (access restrictions to peripheral registers) */
 /**
    \defgroup CMSIS_glob_defs CMSIS Global Defines
    <strong>IO Type Qualifiers</strong> are used
    \li to specify the access to peripheral variables.
    \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
  #define   __I     volatile             /*!< Defines 'read only' permissions */
 #else
  #define   __I     volatile const       /*!< Defines 'read only' permissions */
 #endif
 #define     __O     volatile             /*!< Defines 'write only' permissions */
 #define     __IO    volatile             /*!< Defines 'read / write' permissions */
 /* following defines should be used for structure members */
 #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
 #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
 #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 /*@} end of group Cortex_M1 */
 /*******************************************************************************
 *                 Register Abstraction
  Core Register contain:
  - Core Register
  - Core NVIC Register
  - Core SCB Register
  - Core SysTick Register
 ******************************************************************************/
 /**
  \defgroup CMSIS_core_register Defines and Type Definitions
  \brief Type definitions and defines for Cortex-M processor based devices.
 */
 /**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_CORE  Status and Control Registers
  \brief      Core Register type definitions.
  @{
 */
 /**
  \brief  Union type to access the Application Program Status Register (APSR).
 */
 typedef union
 {
  struct
  {
    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
  } b;                                   /*!< Structure used for bit  access */
  uint32_t w;                            /*!< Type      used for word access */
 } APSR_Type;
 /* APSR Register Definitions */
 #define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
 #define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
 #define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
 #define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
 /**
  \brief  Union type to access the Interrupt Program Status Register (IPSR).
 */
 typedef union
 {
  struct
  {
    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
  } b;                                   /*!< Structure used for bit  access */
  uint32_t w;                            /*!< Type      used for word access */
 } IPSR_Type;
 /* IPSR Register Definitions */
 #define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
 /**
  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 */
 typedef union
 {
  struct
  {
    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
  } b;                                   /*!< Structure used for bit  access */
  uint32_t w;                            /*!< Type      used for word access */
 } xPSR_Type;
 /* xPSR Register Definitions */
 #define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
 #define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
 #define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
 #define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
 #define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
 #define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
 /**
  \brief  Union type to access the Control Registers (CONTROL).
 */
 typedef union
 {
  struct
  {
    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
  } b;                                   /*!< Structure used for bit  access */
  uint32_t w;                            /*!< Type      used for word access */
 } CONTROL_Type;
 /* CONTROL Register Definitions */
 #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
 /*@} end of group CMSIS_CORE */
 /**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
  \brief      Type definitions for the NVIC Registers
  @{
 */
 /**
  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 */
 typedef struct
 {
  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
        uint32_t RESERVED0[31U];
  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
        uint32_t RSERVED1[31U];
  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
        uint32_t RESERVED2[31U];
  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
        uint32_t RESERVED3[31U];
        uint32_t RESERVED4[64U];
  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
 }  NVIC_Type;
 /*@} end of group CMSIS_NVIC */
 /**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCB     System Control Block (SCB)
  \brief    Type definitions for the System Control Block Registers
  @{
 */
 /**
  \brief  Structure type to access the System Control Block (SCB).
 */
 typedef struct
 {
  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
        uint32_t RESERVED0;
  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
        uint32_t RESERVED1;
  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
 } SCB_Type;
 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
 #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
 #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
 #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
 #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
 /* SCB Interrupt Control State Register Definitions */
 #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
 #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
 #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
 #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
 #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
 #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
 #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
 #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
 #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
 #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
 #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
 #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 /* SCB System Control Register Definitions */
 #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
 #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
 #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
 /* SCB Configuration Control Register Definitions */
 #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
 #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
 /* SCB System Handler Control and State Register Definitions */
 #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
 /*@} end of group CMSIS_SCB */
 /**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
  \brief    Type definitions for the System Control and ID Register not in the SCB
  @{
 */
 /**
  \brief  Structure type to access the System Control and ID Register not in the SCB.
 */
 typedef struct
 {
        uint32_t RESERVED0[2U];
  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
 } SCnSCB_Type;
 /* Auxiliary Control Register Definitions */
 #define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
 #define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
 #define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
 #define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
 /*@} end of group CMSIS_SCnotSCB */
 /**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
  \brief    Type definitions for the System Timer Registers.
  @{
 */
 /**
  \brief  Structure type to access the System Timer (SysTick).
 */
 typedef struct
 {
  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 } SysTick_Type;
 /* SysTick Control / Status Register Definitions */
 #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
 #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
 #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
 #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
 /* SysTick Reload Register Definitions */
 #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
 /* SysTick Current Register Definitions */
 #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
 /* SysTick Calibration Register Definitions */
 #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
 #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
 #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
 /*@} end of group CMSIS_SysTick */
 /**
  \ingroup  CMSIS_core_register
  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
            Therefore they are not covered by the Cortex-M1 header file.
  @{
 */
 /*@} end of group CMSIS_CoreDebug */
 /**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_bitfield     Core register bit field macros
  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
  @{
 */
 /**
  \brief   Mask and shift a bit field value for use in a register bit range.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
  \return           Masked and shifted value.
 */
 #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
 /**
  \brief     Mask and shift a register value to extract a bit filed value.
  \param[in] field  Name of the register bit field.
  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
  \return           Masked and shifted bit field value.
 */
 #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
 /*@} end of group CMSIS_core_bitfield */
 /**
  \ingroup    CMSIS_core_register
  \defgroup   CMSIS_core_base     Core Definitions
  \brief      Definitions for base addresses, unions, and structures.
  @{
 */
 /* Memory mapping of Core Hardware */
 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
 /*@} */
 /*******************************************************************************
 *                Hardware Abstraction Layer
  Core Function Interface contains:
  - Core NVIC Functions
  - Core SysTick Functions
  - Core Register Access Functions
 ******************************************************************************/
 /**
  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 /* ##########################   NVIC functions  #################################### */
 /**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
  \brief    Functions that manage interrupts and exceptions via the NVIC.
  @{
 */
 #ifdef CMSIS_NVIC_VIRTUAL
  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
  #endif
  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
 #else
  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
 /*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
  #define NVIC_SetPriority            __NVIC_SetPriority
  #define NVIC_GetPriority            __NVIC_GetPriority
  #define NVIC_SystemReset            __NVIC_SystemReset
 #endif /* CMSIS_NVIC_VIRTUAL */
 #ifdef CMSIS_VECTAB_VIRTUAL
  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
  #endif
  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
 #else
  #define NVIC_SetVector              __NVIC_SetVector
  #define NVIC_GetVector              __NVIC_GetVector
 #endif  /* (CMSIS_VECTAB_VIRTUAL) */
 #define NVIC_USER_IRQ_OFFSET          16
 /* The following EXC_RETURN values are saved the LR on exception entry */
 #define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
 #define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
 #define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
 /* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
 #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
 #define __NVIC_SetPriorityGrouping(X) (void)(X)
 #define __NVIC_GetPriorityGrouping()  (0U)
 /**
  \brief   Enable Interrupt
  \details Enables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  }
 }
 /**
  \brief   Get Interrupt Enable status
  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \return             0  Interrupt is not enabled.
  \return             1  Interrupt is enabled.
  \note    IRQn must not be negative.
 */
 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
  }
  else
  {
    return(0U);
  }
 }
 /**
  \brief   Disable Interrupt
  \details Disables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    __DSB();
    __ISB();
  }
 }
 /**
  \brief   Get Pending Interrupt
  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
  \param [in]      IRQn  Device specific interrupt number.
  \return             0  Interrupt status is not pending.
  \return             1  Interrupt status is pending.
  \note    IRQn must not be negative.
 */
 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
  }
  else
  {
    return(0U);
  }
 }
 /**
  \brief   Set Pending Interrupt
  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  }
 }
 /**
  \brief   Clear Pending Interrupt
  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  }
 }
 /**
  \brief   Set Interrupt Priority
  \details Sets the priority of a device specific interrupt or a processor exception.
           The interrupt number can be positive to specify a device specific interrupt,
           or negative to specify a processor exception.
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  }
  else
  {
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  }
 }
 /**
  \brief   Get Interrupt Priority
  \details Reads the priority of a device specific interrupt or a processor exception.
           The interrupt number can be positive to specify a device specific interrupt,
           or negative to specify a processor exception.
  \param [in]   IRQn  Interrupt number.
  \return             Interrupt Priority.
                      Value is aligned automatically to the implemented priority bits of the microcontroller.
 */
 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 {
  if ((int32_t)(IRQn) >= 0)
  {
    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  }
  else
  {
    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
  }
 }
 /**
  \brief   Encode Priority
  \details Encodes the priority for an interrupt with the given priority group,
           preemptive priority value, and subpriority value.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]     PriorityGroup  Used priority group.
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
         );
 }
 /**
  \brief   Decode Priority
  \details Decodes an interrupt priority value with a given priority group to
           preemptive priority value and subpriority value.
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
  \param [in]     PriorityGroup  Used priority group.
  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
  \param [out]     pSubPriority  Subpriority value (starting from 0).
 */
 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
 {
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;
  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
 }
 /**
  \brief   Set Interrupt Vector
  \details Sets an interrupt vector in SRAM based interrupt vector table.
           The interrupt number can be positive to specify a device specific interrupt,
           or negative to specify a processor exception.
           Address 0 must be mapped to SRAM.
  \param [in]   IRQn      Interrupt number
  \param [in]   vector    Address of interrupt handler function
 */
 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
 {
  uint32_t *vectors = (uint32_t *)0x0U;
  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
 }
 /**
  \brief   Get Interrupt Vector
  \details Reads an interrupt vector from interrupt vector table.
           The interrupt number can be positive to specify a device specific interrupt,
           or negative to specify a processor exception.
  \param [in]   IRQn      Interrupt number.
  \return                 Address of interrupt handler function
 */
 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
 {
  uint32_t *vectors = (uint32_t *)0x0U;
  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
 }
 /**
  \brief   System Reset
  \details Initiates a system reset request to reset the MCU.
 */
 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 {
  __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                       buffered write are completed before reset */
  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                 SCB_AIRCR_SYSRESETREQ_Msk);
  __DSB();                                                          /* Ensure completion of memory access */
  for(;;)                                                           /* wait until reset */
  {
    __NOP();
  }
 }
 /*@} end of CMSIS_Core_NVICFunctions */
 /* ##########################  FPU functions  #################################### */
 /**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_FpuFunctions FPU Functions
  \brief    Function that provides FPU type.
  @{
 */
 /**
  \brief   get FPU type
  \details returns the FPU type
  \returns
   - \b  0: No FPU
   - \b  1: Single precision FPU
   - \b  2: Double + Single precision FPU
 */
 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
 {
    return 0U;           /* No FPU */
 }
 /*@} end of CMSIS_Core_FpuFunctions */
 /* ##################################    SysTick function  ############################################ */
 /**
  \ingroup  CMSIS_Core_FunctionInterface
  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
  \brief    Functions that configure the System.
  @{
 */
 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
 /**
  \brief   System Tick Configuration
  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
           Counter is in free running mode to generate periodic interrupts.
  \param [in]  ticks  Number of ticks between two interrupts.
  \return          0  Function succeeded.
  \return          1  Function failed.
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
  {
    return (1UL);                                                   /* Reload value impossible */
  }
  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 }
 #endif
 /*@} end of CMSIS_Core_SysTickFunctions */
 #ifdef __cplusplus
 }
 #endif
 #endif /* __CORE_CM1_H_DEPENDANT */
 #endif /* __CMSIS_GENERIC */
--- a/target_f1/Drivers/CMSIS/Core/Include/core_cm23.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/core_cm23.h
--- a/target_f1/Drivers/CMSIS/Core/Include/core_cm3.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/core_cm3.h
--- a/target_f1/Drivers/CMSIS/Core/Include/core_cm33.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/core_cm33.h
--- a/target_f1/Drivers/CMSIS/Core/Include/core_cm4.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/core_cm4.h
--- a/target_f1/Drivers/CMSIS/Core/Include/core_cm7.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/core_cm7.h
--- a/target_f1/Drivers/CMSIS/Core/Include/core_sc000.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/core_sc000.h
--- a/target_f1/Drivers/CMSIS/Core/Include/core_sc300.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/core_sc300.h
--- a/target_f1/Drivers/CMSIS/Core/Include/mpu_armv7.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/mpu_armv7.h
@ -1,270 +0,0 @@
 /******************************************************************************
 * @file     mpu_armv7.h
 * @brief    CMSIS MPU API for Armv7-M MPU
 * @version  V5.0.4
 * @date     10. January 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #if   defined ( __ICCARM__ )
  #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
  #pragma clang system_header    /* treat file as system include file */
 #endif
 #ifndef ARM_MPU_ARMV7_H
 #define ARM_MPU_ARMV7_H
 #define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
 #define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
 #define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
 #define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
 #define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
 #define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
 #define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
 #define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
 #define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
 #define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
 #define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
 #define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
 #define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
 #define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
 #define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
 #define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
 #define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
 #define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
 #define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
 #define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
 #define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
 #define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
 #define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
 #define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
 #define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
 #define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
 #define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
 #define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
 #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
 #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
 #define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
 #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
 #define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
 #define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
 /** MPU Region Base Address Register Value
 *
 * \param Region The region to be configured, number 0 to 15.
 * \param BaseAddress The base address for the region.
 */
 #define ARM_MPU_RBAR(Region, BaseAddress) \
  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
   ((Region) & MPU_RBAR_REGION_Msk)    |  \
   (MPU_RBAR_VALID_Msk))
 /**
 * MPU Memory Access Attributes
 * 
 * \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
 * \param IsShareable       Region is shareable between multiple bus masters.
 * \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
 * \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
 */  
 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
 /**
 * MPU Region Attribute and Size Register Value
 * 
 * \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
 * \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
 * \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
 * \param SubRegionDisable  Sub-region disable field.
 * \param Size              Region size of the region to be configured, for example 4K, 8K.
 */
 #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
 /**
 * MPU Region Attribute and Size Register Value
 * 
 * \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
 * \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
 * \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
 * \param IsShareable       Region is shareable between multiple bus masters.
 * \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
 * \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
 * \param SubRegionDisable  Sub-region disable field.
 * \param Size              Region size of the region to be configured, for example 4K, 8K.
 */                         
 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
 /**
 * MPU Memory Access Attribute for strongly ordered memory.
 *  - TEX: 000b
 *  - Shareable
 *  - Non-cacheable
 *  - Non-bufferable
 */ 
 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
 /**
 * MPU Memory Access Attribute for device memory.
 *  - TEX: 000b (if non-shareable) or 010b (if shareable)
 *  - Shareable or non-shareable
 *  - Non-cacheable
 *  - Bufferable (if shareable) or non-bufferable (if non-shareable)
 *
 * \param IsShareable Configures the device memory as shareable or non-shareable.
 */ 
 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
 /**
 * MPU Memory Access Attribute for normal memory.
 *  - TEX: 1BBb (reflecting outer cacheability rules)
 *  - Shareable or non-shareable
 *  - Cacheable or non-cacheable (reflecting inner cacheability rules)
 *  - Bufferable or non-bufferable (reflecting inner cacheability rules)
 *
 * \param OuterCp Configures the outer cache policy.
 * \param InnerCp Configures the inner cache policy.
 * \param IsShareable Configures the memory as shareable or non-shareable.
 */ 
 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
 /**
 * MPU Memory Access Attribute non-cacheable policy.
 */
 #define ARM_MPU_CACHEP_NOCACHE 0U
 /**
 * MPU Memory Access Attribute write-back, write and read allocate policy.
 */
 #define ARM_MPU_CACHEP_WB_WRA 1U
 /**
 * MPU Memory Access Attribute write-through, no write allocate policy.
 */
 #define ARM_MPU_CACHEP_WT_NWA 2U
 /**
 * MPU Memory Access Attribute write-back, no write allocate policy.
 */
 #define ARM_MPU_CACHEP_WB_NWA 3U
 /**
 * Struct for a single MPU Region
 */
 typedef struct {
  uint32_t RBAR; //!< The region base address register value (RBAR)
  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
 } ARM_MPU_Region_t;
 /** Enable the MPU.
 * \param MPU_Control Default access permissions for unconfigured regions.
 */
 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
 {
  __DSB();
  __ISB();
  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
 }
 /** Disable the MPU.
 */
 __STATIC_INLINE void ARM_MPU_Disable(void)
 {
  __DSB();
  __ISB();
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
 }
 /** Clear and disable the given MPU region.
 * \param rnr Region number to be cleared.
 */
 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
 {
  MPU->RNR = rnr;
  MPU->RASR = 0U;
 }
 /** Configure an MPU region.
 * \param rbar Value for RBAR register.
 * \param rsar Value for RSAR register.
 */   
 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
 {
  MPU->RBAR = rbar;
  MPU->RASR = rasr;
 }
 /** Configure the given MPU region.
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rsar Value for RSAR register.
 */   
 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
 {
  MPU->RNR = rnr;
  MPU->RBAR = rbar;
  MPU->RASR = rasr;
 }
 /** Memcopy with strictly ordered memory access, e.g. for register targets.
 * \param dst Destination data is copied to.
 * \param src Source data is copied from.
 * \param len Amount of data words to be copied.
 */
 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
 {
  uint32_t i;
  for (i = 0U; i < len; ++i) 
  {
    dst[i] = src[i];
  }
 }
 /** Load the given number of MPU regions from a table.
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
 {
  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
  while (cnt > MPU_TYPE_RALIASES) {
    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
    table += MPU_TYPE_RALIASES;
    cnt -= MPU_TYPE_RALIASES;
  }
  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
 }
 #endif
--- a/target_f1/Drivers/CMSIS/Core/Include/mpu_armv8.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/mpu_armv8.h
@ -1,333 +0,0 @@
 /******************************************************************************
 * @file     mpu_armv8.h
 * @brief    CMSIS MPU API for Armv8-M MPU
 * @version  V5.0.4
 * @date     10. January 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #if   defined ( __ICCARM__ )
  #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
  #pragma clang system_header    /* treat file as system include file */
 #endif
 #ifndef ARM_MPU_ARMV8_H
 #define ARM_MPU_ARMV8_H
 /** \brief Attribute for device memory (outer only) */
 #define ARM_MPU_ATTR_DEVICE                           ( 0U )
 /** \brief Attribute for non-cacheable, normal memory */
 #define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
 /** \brief Attribute for normal memory (outer and inner)
 * \param NT Non-Transient: Set to 1 for non-transient data.
 * \param WB Write-Back: Set to 1 to use write-back update policy.
 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
 */
 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
 #define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
 #define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
 #define ARM_MPU_ATTR_DEVICE_GRE    (3U)
 /** \brief Memory Attribute
 * \param O Outer memory attributes
 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
 */
 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
 /** \brief Normal memory non-shareable  */
 #define ARM_MPU_SH_NON   (0U)
 /** \brief Normal memory outer shareable  */
 #define ARM_MPU_SH_OUTER (2U)
 /** \brief Normal memory inner shareable  */
 #define ARM_MPU_SH_INNER (3U)
 /** \brief Memory access permissions
 * \param RO Read-Only: Set to 1 for read-only memory.
 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
 */
 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
 /** \brief Region Base Address Register value
 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
 * \param SH Defines the Shareability domain for this memory region.
 * \param RO Read-Only: Set to 1 for a read-only memory region.
 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
 */
 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
  ((BASE & MPU_RBAR_BASE_Msk) | \
  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
 /** \brief Region Limit Address Register value
 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
 * \param IDX The attribute index to be associated with this memory region.
 */
 #define ARM_MPU_RLAR(LIMIT, IDX) \
  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
  (MPU_RLAR_EN_Msk))
 /**
 * Struct for a single MPU Region
 */
 typedef struct {
  uint32_t RBAR;                   /*!< Region Base Address Register value */
  uint32_t RLAR;                   /*!< Region Limit Address Register value */
 } ARM_MPU_Region_t;
 /** Enable the MPU.
 * \param MPU_Control Default access permissions for unconfigured regions.
 */
 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
 {
  __DSB();
  __ISB();
  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
 }
 /** Disable the MPU.
 */
 __STATIC_INLINE void ARM_MPU_Disable(void)
 {
  __DSB();
  __ISB();
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
 }
 #ifdef MPU_NS
 /** Enable the Non-secure MPU.
 * \param MPU_Control Default access permissions for unconfigured regions.
 */
 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
 {
  __DSB();
  __ISB();
  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
 }
 /** Disable the Non-secure MPU.
 */
 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
 {
  __DSB();
  __ISB();
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
 }
 #endif
 /** Set the memory attribute encoding to the given MPU.
 * \param mpu Pointer to the MPU to be configured.
 * \param idx The attribute index to be set [0-7]
 * \param attr The attribute value to be set.
 */
 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
 {
  const uint8_t reg = idx / 4U;
  const uint32_t pos = ((idx % 4U) * 8U);
  const uint32_t mask = 0xFFU << pos;
  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
    return; // invalid index
  }
  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
 }
 /** Set the memory attribute encoding.
 * \param idx The attribute index to be set [0-7]
 * \param attr The attribute value to be set.
 */
 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
 {
  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
 }
 #ifdef MPU_NS
 /** Set the memory attribute encoding to the Non-secure MPU.
 * \param idx The attribute index to be set [0-7]
 * \param attr The attribute value to be set.
 */
 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
 {
  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
 }
 #endif
 /** Clear and disable the given MPU region of the given MPU.
 * \param mpu Pointer to MPU to be used.
 * \param rnr Region number to be cleared.
 */
 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
 {
  mpu->RNR = rnr;
  mpu->RLAR = 0U;
 }
 /** Clear and disable the given MPU region.
 * \param rnr Region number to be cleared.
 */
 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
 {
  ARM_MPU_ClrRegionEx(MPU, rnr);
 }
 #ifdef MPU_NS
 /** Clear and disable the given Non-secure MPU region.
 * \param rnr Region number to be cleared.
 */
 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
 {  
  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
 }
 #endif
 /** Configure the given MPU region of the given MPU.
 * \param mpu Pointer to MPU to be used.
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rlar Value for RLAR register.
 */   
 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
 {
  mpu->RNR = rnr;
  mpu->RBAR = rbar;
  mpu->RLAR = rlar;
 }
 /** Configure the given MPU region.
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rlar Value for RLAR register.
 */   
 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
 {
  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
 }
 #ifdef MPU_NS
 /** Configure the given Non-secure MPU region.
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rlar Value for RLAR register.
 */   
 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
 {
  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
 }
 #endif
 /** Memcopy with strictly ordered memory access, e.g. for register targets.
 * \param dst Destination data is copied to.
 * \param src Source data is copied from.
 * \param len Amount of data words to be copied.
 */
 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
 {
  uint32_t i;
  for (i = 0U; i < len; ++i) 
  {
    dst[i] = src[i];
  }
 }
 /** Load the given number of MPU regions from a table to the given MPU.
 * \param mpu Pointer to the MPU registers to be used.
 * \param rnr First region number to be configured.
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
 {
  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
  if (cnt == 1U) {
    mpu->RNR = rnr;
    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
  } else {
    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
    mpu->RNR = rnrBase;
    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
      table += c;
      cnt -= c;
      rnrOffset = 0U;
      rnrBase += MPU_TYPE_RALIASES;
      mpu->RNR = rnrBase;
    }
    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
  }
 }
 /** Load the given number of MPU regions from a table.
 * \param rnr First region number to be configured.
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
 {
  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
 }
 #ifdef MPU_NS
 /** Load the given number of MPU regions from a table to the Non-secure MPU.
 * \param rnr First region number to be configured.
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
 {
  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
 }
 #endif
 #endif
--- a/target_f1/Drivers/CMSIS/Core/Include/tz_context.h
+++ b/target_f1/Drivers/CMSIS/Core/Include/tz_context.h
@ -1,70 +0,0 @@
 /******************************************************************************
 * @file     tz_context.h
 * @brief    Context Management for Armv8-M TrustZone
 * @version  V1.0.1
 * @date     10. January 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #if   defined ( __ICCARM__ )
  #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
  #pragma clang system_header   /* treat file as system include file */
 #endif
 #ifndef TZ_CONTEXT_H
 #define TZ_CONTEXT_H
 #include <stdint.h>
 #ifndef TZ_MODULEID_T
 #define TZ_MODULEID_T
 /// \details Data type that identifies secure software modules called by a process.
 typedef uint32_t TZ_ModuleId_t;
 #endif
 /// \details TZ Memory ID identifies an allocated memory slot.
 typedef uint32_t TZ_MemoryId_t;
 /// Initialize secure context memory system
 /// \return execution status (1: success, 0: error)
 uint32_t TZ_InitContextSystem_S (void);
 /// Allocate context memory for calling secure software modules in TrustZone
 /// \param[in]  module   identifies software modules called from non-secure mode
 /// \return value != 0 id TrustZone memory slot identifier
 /// \return value 0    no memory available or internal error
 TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
 /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
 /// \param[in]  id  TrustZone memory slot identifier
 /// \return execution status (1: success, 0: error)
 uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
 /// Load secure context (called on RTOS thread context switch)
 /// \param[in]  id  TrustZone memory slot identifier
 /// \return execution status (1: success, 0: error)
 uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
 /// Store secure context (called on RTOS thread context switch)
 /// \param[in]  id  TrustZone memory slot identifier
 /// \return execution status (1: success, 0: error)
 uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
 #endif  // TZ_CONTEXT_H
--- a/target_f1/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c
+++ b/target_f1/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c
@ -1,58 +0,0 @@
 /******************************************************************************
 * @file     main_s.c
 * @brief    Code template for secure main function
 * @version  V1.1.1
 * @date     10. January 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 /* Use CMSE intrinsics */
 #include <arm_cmse.h>
 #include "RTE_Components.h"
 #include CMSIS_device_header
 /* TZ_START_NS: Start address of non-secure application */
 #ifndef TZ_START_NS
 #define TZ_START_NS (0x200000U)
 #endif
 /* typedef for non-secure callback functions */
 typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
 /* Secure main() */
 int main(void) {
  funcptr_void NonSecure_ResetHandler;
  /* Add user setup code for secure part here*/
  /* Set non-secure main stack (MSP_NS) */
  __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
  /* Get non-secure reset handler */
  NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
  /* Start non-secure state software application */
  NonSecure_ResetHandler();
  /* Non-secure software does not return, this code is not executed */
  while (1) {
    __NOP();
  }
 }
--- a/target_f1/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c
+++ b/target_f1/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c
@ -1,200 +0,0 @@
 /******************************************************************************
 * @file     tz_context.c
 * @brief    Context Management for Armv8-M TrustZone - Sample implementation
 * @version  V1.1.1
 * @date     10. January 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2016-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #include "RTE_Components.h"
 #include CMSIS_device_header
 #include "tz_context.h"
 /// Number of process slots (threads may call secure library code)
 #ifndef TZ_PROCESS_STACK_SLOTS
 #define TZ_PROCESS_STACK_SLOTS     8U
 #endif
 /// Stack size of the secure library code
 #ifndef TZ_PROCESS_STACK_SIZE
 #define TZ_PROCESS_STACK_SIZE      256U
 #endif
 typedef struct {
  uint32_t sp_top;      // stack space top
  uint32_t sp_limit;    // stack space limit
  uint32_t sp;          // current stack pointer
 } stack_info_t;
 static stack_info_t ProcessStackInfo  [TZ_PROCESS_STACK_SLOTS];
 static uint64_t     ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
 static uint32_t     ProcessStackFreeSlot = 0xFFFFFFFFU;
 /// Initialize secure context memory system
 /// \return execution status (1: success, 0: error)
 __attribute__((cmse_nonsecure_entry))
 uint32_t TZ_InitContextSystem_S (void) {
  uint32_t n;
  if (__get_IPSR() == 0U) {
    return 0U;  // Thread Mode
  }
  for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
    ProcessStackInfo[n].sp = 0U;
    ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
    ProcessStackInfo[n].sp_top   = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
    *((uint32_t *)ProcessStackMemory[n]) = n + 1U;
  }
  *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
  ProcessStackFreeSlot = 0U;
  // Default process stack pointer and stack limit
  __set_PSPLIM((uint32_t)ProcessStackMemory);
  __set_PSP   ((uint32_t)ProcessStackMemory);
  // Privileged Thread Mode using PSP
  __set_CONTROL(0x02U);
  return 1U;    // Success
 }
 /// Allocate context memory for calling secure software modules in TrustZone
 /// \param[in]  module   identifies software modules called from non-secure mode
 /// \return value != 0 id TrustZone memory slot identifier
 /// \return value 0    no memory available or internal error
 __attribute__((cmse_nonsecure_entry))
 TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
  uint32_t slot;
  (void)module; // Ignore (fixed Stack size)
  if (__get_IPSR() == 0U) {
    return 0U;  // Thread Mode
  }
  if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
    return 0U;  // No slot available
  }
  slot = ProcessStackFreeSlot;
  ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
  ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
  return (slot + 1U);
 }
 /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
 /// \param[in]  id  TrustZone memory slot identifier
 /// \return execution status (1: success, 0: error)
 __attribute__((cmse_nonsecure_entry))
 uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
  uint32_t slot;
  if (__get_IPSR() == 0U) {
    return 0U;  // Thread Mode
  }
  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
    return 0U;  // Invalid ID
  }
  slot = id - 1U;
  if (ProcessStackInfo[slot].sp == 0U) {
    return 0U;  // Inactive slot
  }
  ProcessStackInfo[slot].sp = 0U;
  *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
  ProcessStackFreeSlot = slot;
  return 1U;    // Success
 }
 /// Load secure context (called on RTOS thread context switch)
 /// \param[in]  id  TrustZone memory slot identifier
 /// \return execution status (1: success, 0: error)
 __attribute__((cmse_nonsecure_entry))
 uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
  uint32_t slot;
  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
    return 0U;  // Thread Mode or using Main Stack for threads
  }
  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
    return 0U;  // Invalid ID
  }
  slot = id - 1U;
  if (ProcessStackInfo[slot].sp == 0U) {
    return 0U;  // Inactive slot
  }
  // Setup process stack pointer and stack limit
  __set_PSPLIM(ProcessStackInfo[slot].sp_limit);
  __set_PSP   (ProcessStackInfo[slot].sp);
  return 1U;    // Success
 }
 /// Store secure context (called on RTOS thread context switch)
 /// \param[in]  id  TrustZone memory slot identifier
 /// \return execution status (1: success, 0: error)
 __attribute__((cmse_nonsecure_entry))
 uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
  uint32_t slot;
  uint32_t sp;
  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
    return 0U;  // Thread Mode or using Main Stack for threads
  }
  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
    return 0U;  // Invalid ID
  }
  slot = id - 1U;
  if (ProcessStackInfo[slot].sp == 0U) {
    return 0U;  // Inactive slot
  }
  sp = __get_PSP();
  if ((sp < ProcessStackInfo[slot].sp_limit) ||
      (sp > ProcessStackInfo[slot].sp_top)) {
    return 0U;  // SP out of range
  }
  ProcessStackInfo[slot].sp = sp;
  // Default process stack pointer and stack limit
  __set_PSPLIM((uint32_t)ProcessStackMemory);
  __set_PSP   ((uint32_t)ProcessStackMemory);
  return 1U;    // Success
 }
--- a/target_f1/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h
+++ b/target_f1/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h
@ -1,544 +0,0 @@
 /**************************************************************************//**
 * @file     cmsis_armcc.h
 * @brief    CMSIS compiler specific macros, functions, instructions
 * @version  V1.0.2
 * @date     10. January 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #ifndef __CMSIS_ARMCC_H
 #define __CMSIS_ARMCC_H
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
 #endif
 /* CMSIS compiler control architecture macros */
 #if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A  == 1))
  #define __ARM_ARCH_7A__           1
 #endif
 /* CMSIS compiler specific defines */
 #ifndef   __ASM
  #define __ASM                                  __asm
 #endif
 #ifndef   __INLINE
  #define __INLINE                               __inline
 #endif
 #ifndef   __FORCEINLINE
  #define __FORCEINLINE                          __forceinline
 #endif
 #ifndef   __STATIC_INLINE
  #define __STATIC_INLINE                        static __inline
 #endif
 #ifndef   __STATIC_FORCEINLINE
  #define __STATIC_FORCEINLINE                   static __forceinline
 #endif
 #ifndef   __NO_RETURN
  #define __NO_RETURN                            __declspec(noreturn)
 #endif
 #ifndef   CMSIS_DEPRECATED
  #define CMSIS_DEPRECATED                       __attribute__((deprecated))
 #endif
 #ifndef   __USED
  #define __USED                                 __attribute__((used))
 #endif
 #ifndef   __WEAK
  #define __WEAK                                 __attribute__((weak))
 #endif
 #ifndef   __PACKED
  #define __PACKED                               __attribute__((packed))
 #endif
 #ifndef   __PACKED_STRUCT
  #define __PACKED_STRUCT                        __packed struct
 #endif
 #ifndef   __UNALIGNED_UINT16_WRITE
  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT16_READ
  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
 #endif
 #ifndef   __UNALIGNED_UINT32_WRITE
  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT32_READ
  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
 #endif
 #ifndef   __ALIGNED
  #define __ALIGNED(x)                           __attribute__((aligned(x)))
 #endif
 #ifndef   __PACKED
  #define __PACKED                               __attribute__((packed))
 #endif
 /* ##########################  Core Instruction Access  ######################### */
 /**
  \brief   No Operation
 */
 #define __NOP                             __nop
 /**
  \brief   Wait For Interrupt
 */
 #define __WFI                             __wfi
 /**
  \brief   Wait For Event
 */
 #define __WFE                             __wfe
 /**
  \brief   Send Event
 */
 #define __SEV                             __sev
 /**
  \brief   Instruction Synchronization Barrier
 */
 #define __ISB() do {\
                   __schedule_barrier();\
                   __isb(0xF);\
                   __schedule_barrier();\
                } while (0U)
 /**
  \brief   Data Synchronization Barrier
 */
 #define __DSB() do {\
                   __schedule_barrier();\
                   __dsb(0xF);\
                   __schedule_barrier();\
                } while (0U)
 /**
  \brief   Data Memory Barrier
 */
 #define __DMB() do {\
                   __schedule_barrier();\
                   __dmb(0xF);\
                   __schedule_barrier();\
                } while (0U)
 /**
  \brief   Reverse byte order (32 bit)
  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 #define __REV                             __rev
 /**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
 {
  rev16 r0, r0
  bx lr
 }
 #endif
 /**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
 {
  revsh r0, r0
  bx lr
 }
 #endif
 /**
  \brief   Rotate Right in unsigned value (32 bit)
  \param [in]    op1  Value to rotate
  \param [in]    op2  Number of Bits to rotate
  \return               Rotated value
 */
 #define __ROR                             __ror
 /**
  \brief   Breakpoint
  \param [in]    value  is ignored by the processor.
                 If required, a debugger can use it to store additional information about the breakpoint.
 */
 #define __BKPT(value)                     __breakpoint(value)
 /**
  \brief   Reverse bit order of value
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 #define __RBIT                            __rbit
 /**
  \brief   Count leading zeros
  \param [in]  value  Value to count the leading zeros
  \return             number of leading zeros in value
 */
 #define __CLZ                             __clz
 /**
  \brief   LDR Exclusive (8 bit)
  \details Executes a exclusive LDR instruction for 8 bit value.
  \param [in]    ptr  Pointer to data
  \return             value of type uint8_t at (*ptr)
 */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
 #else
  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
 #endif
 /**
  \brief   LDR Exclusive (16 bit)
  \details Executes a exclusive LDR instruction for 16 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint16_t at (*ptr)
 */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
 #else
  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
 #endif
 /**
  \brief   LDR Exclusive (32 bit)
  \details Executes a exclusive LDR instruction for 32 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint32_t at (*ptr)
 */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
 #else
  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
 #endif
 /**
  \brief   STR Exclusive (8 bit)
  \details Executes a exclusive STR instruction for 8 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
 #else
  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 #endif
 /**
  \brief   STR Exclusive (16 bit)
  \details Executes a exclusive STR instruction for 16 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
 #else
  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 #endif
 /**
  \brief   STR Exclusive (32 bit)
  \details Executes a exclusive STR instruction for 32 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
 #else
  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
 #endif
 /**
  \brief   Remove the exclusive lock
  \details Removes the exclusive lock which is created by LDREX.
 */
 #define __CLREX                           __clrex
 /**
  \brief   Signed Saturate
  \details Saturates a signed value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (1..32)
  \return             Saturated value
 */
 #define __SSAT                            __ssat
 /**
  \brief   Unsigned Saturate
  \details Saturates an unsigned value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (0..31)
  \return             Saturated value
 */
 #define __USAT                            __usat
 /* ###########################  Core Function Access  ########################### */
 /**
  \brief   Get FPSCR (Floating Point Status/Control)
  \return               Floating Point Status/Control register value
 */
 __STATIC_INLINE uint32_t __get_FPSCR(void)
 {
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
  register uint32_t __regfpscr         __ASM("fpscr");
  return(__regfpscr);
 #else
   return(0U);
 #endif
 }
 /**
  \brief   Set FPSCR (Floating Point Status/Control)
  \param [in]    fpscr  Floating Point Status/Control value to set
 */
 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 {
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
  register uint32_t __regfpscr         __ASM("fpscr");
  __regfpscr = (fpscr);
 #else
  (void)fpscr;
 #endif
 }
 /** \brief  Get CPSR (Current Program Status Register)
    \return               CPSR Register value
 */
 __STATIC_INLINE uint32_t __get_CPSR(void)
 {
  register uint32_t __regCPSR          __ASM("cpsr");
  return(__regCPSR);
 }
 /** \brief  Set CPSR (Current Program Status Register)
    \param [in]    cpsr  CPSR value to set
 */
 __STATIC_INLINE void __set_CPSR(uint32_t cpsr)
 {
  register uint32_t __regCPSR          __ASM("cpsr");
  __regCPSR = cpsr;
 }
 /** \brief  Get Mode
    \return                Processor Mode
 */
 __STATIC_INLINE uint32_t __get_mode(void)
 {
  return (__get_CPSR() & 0x1FU);
 }
 /** \brief  Set Mode
    \param [in]    mode  Mode value to set
 */
 __STATIC_INLINE __ASM void __set_mode(uint32_t mode)
 {
  MOV  r1, lr
  MSR  CPSR_C, r0
  BX   r1
 }
 /** \brief  Get Stack Pointer
    \return Stack Pointer
 */
 __STATIC_INLINE __ASM uint32_t __get_SP(void)
 {
  MOV  r0, sp
  BX   lr
 }
 /** \brief  Set Stack Pointer
    \param [in]    stack  Stack Pointer value to set
 */
 __STATIC_INLINE __ASM void __set_SP(uint32_t stack)
 {
  MOV  sp, r0
  BX   lr
 }
 /** \brief  Get USR/SYS Stack Pointer
    \return USR/SYSStack Pointer
 */
 __STATIC_INLINE __ASM uint32_t __get_SP_usr(void)
 {
  ARM
  PRESERVE8
  MRS     R1, CPSR
  CPS     #0x1F       ;no effect in USR mode
  MOV     R0, SP
  MSR     CPSR_c, R1  ;no effect in USR mode
  ISB
  BX      LR
 }
 /** \brief  Set USR/SYS Stack Pointer
    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
 */
 __STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)
 {
  ARM
  PRESERVE8
  MRS     R1, CPSR
  CPS     #0x1F       ;no effect in USR mode
  MOV     SP, R0
  MSR     CPSR_c, R1  ;no effect in USR mode
  ISB
  BX      LR
 }
 /** \brief  Get FPEXC (Floating Point Exception Control Register)
    \return               Floating Point Exception Control Register value
 */
 __STATIC_INLINE uint32_t __get_FPEXC(void)
 {
 #if (__FPU_PRESENT == 1)
  register uint32_t __regfpexc         __ASM("fpexc");
  return(__regfpexc);
 #else
  return(0);
 #endif
 }
 /** \brief  Set FPEXC (Floating Point Exception Control Register)
    \param [in]    fpexc  Floating Point Exception Control value to set
 */
 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
 {
 #if (__FPU_PRESENT == 1)
  register uint32_t __regfpexc         __ASM("fpexc");
  __regfpexc = (fpexc);
 #endif
 }
 /*
 * Include common core functions to access Coprocessor 15 registers
 */
 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
 #define __get_CP64(cp, op1, Rt, CRm) \
  do { \
    uint32_t ltmp, htmp; \
    __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
    (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \
  } while(0)
 #define __set_CP64(cp, op1, Rt, CRm) \
  do { \
    const uint64_t tmp = (Rt); \
    const uint32_t ltmp = (uint32_t)(tmp); \
    const uint32_t htmp = (uint32_t)(tmp >> 32U); \
    __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
  } while(0)
 #include "cmsis_cp15.h"
 /** \brief  Enable Floating Point Unit
  Critical section, called from undef handler, so systick is disabled
 */
 __STATIC_INLINE __ASM void __FPU_Enable(void)
 {
        ARM
        //Permit access to VFP/NEON, registers by modifying CPACR
        MRC     p15,0,R1,c1,c0,2
        ORR     R1,R1,#0x00F00000
        MCR     p15,0,R1,c1,c0,2
        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
        ISB
        //Enable VFP/NEON
        VMRS    R1,FPEXC
        ORR     R1,R1,#0x40000000
        VMSR    FPEXC,R1
        //Initialise VFP/NEON registers to 0
        MOV     R2,#0
        //Initialise D16 registers to 0
        VMOV    D0, R2,R2
        VMOV    D1, R2,R2
        VMOV    D2, R2,R2
        VMOV    D3, R2,R2
        VMOV    D4, R2,R2
        VMOV    D5, R2,R2
        VMOV    D6, R2,R2
        VMOV    D7, R2,R2
        VMOV    D8, R2,R2
        VMOV    D9, R2,R2
        VMOV    D10,R2,R2
        VMOV    D11,R2,R2
        VMOV    D12,R2,R2
        VMOV    D13,R2,R2
        VMOV    D14,R2,R2
        VMOV    D15,R2,R2
  IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
        //Initialise D32 registers to 0
        VMOV    D16,R2,R2
        VMOV    D17,R2,R2
        VMOV    D18,R2,R2
        VMOV    D19,R2,R2
        VMOV    D20,R2,R2
        VMOV    D21,R2,R2
        VMOV    D22,R2,R2
        VMOV    D23,R2,R2
        VMOV    D24,R2,R2
        VMOV    D25,R2,R2
        VMOV    D26,R2,R2
        VMOV    D27,R2,R2
        VMOV    D28,R2,R2
        VMOV    D29,R2,R2
        VMOV    D30,R2,R2
        VMOV    D31,R2,R2
  ENDIF
        //Initialise FPSCR to a known state
        VMRS    R2,FPSCR
        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
        AND     R2,R2,R3
        VMSR    FPSCR,R2
        BX      LR
 }
 #endif /* __CMSIS_ARMCC_H */
--- a/target_f1/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h
+++ b/target_f1/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h
@ -1,503 +0,0 @@
 /**************************************************************************//**
 * @file     cmsis_armclang.h
 * @brief    CMSIS compiler specific macros, functions, instructions
 * @version  V1.0.2
 * @date     10. January 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #ifndef __CMSIS_ARMCLANG_H
 #define __CMSIS_ARMCLANG_H
 #pragma clang system_header   /* treat file as system include file */
 #ifndef __ARM_COMPAT_H
 #include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
 #endif
 /* CMSIS compiler specific defines */
 #ifndef   __ASM
  #define __ASM                                  __asm
 #endif
 #ifndef   __INLINE
  #define __INLINE                               __inline
 #endif
 #ifndef   __FORCEINLINE
  #define __FORCEINLINE                          __attribute__((always_inline))
 #endif
 #ifndef   __STATIC_INLINE
  #define __STATIC_INLINE                        static __inline
 #endif
 #ifndef   __STATIC_FORCEINLINE
  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
 #endif
 #ifndef   __NO_RETURN
  #define __NO_RETURN                            __attribute__((__noreturn__))
 #endif
 #ifndef   CMSIS_DEPRECATED
  #define CMSIS_DEPRECATED                       __attribute__((deprecated))
 #endif
 #ifndef   __USED
  #define __USED                                 __attribute__((used))
 #endif
 #ifndef   __WEAK
  #define __WEAK                                 __attribute__((weak))
 #endif
 #ifndef   __PACKED
  #define __PACKED                               __attribute__((packed, aligned(1)))
 #endif
 #ifndef   __PACKED_STRUCT
  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
 #endif
 #ifndef   __UNALIGNED_UINT16_WRITE
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wpacked"
 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  #pragma clang diagnostic pop
  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT16_READ
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wpacked"
 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  #pragma clang diagnostic pop
  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
 #endif
 #ifndef   __UNALIGNED_UINT32_WRITE
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wpacked"
 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  #pragma clang diagnostic pop
  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT32_READ
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wpacked"
  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
  #pragma clang diagnostic pop
  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
 #endif
 #ifndef   __ALIGNED
  #define __ALIGNED(x)                           __attribute__((aligned(x)))
 #endif
 #ifndef   __PACKED
  #define __PACKED                               __attribute__((packed))
 #endif
 /* ##########################  Core Instruction Access  ######################### */
 /**
  \brief   No Operation
 */
 #define __NOP                             __builtin_arm_nop
 /**
  \brief   Wait For Interrupt
 */
 #define __WFI                             __builtin_arm_wfi
 /**
  \brief   Wait For Event
 */
 #define __WFE                             __builtin_arm_wfe
 /**
  \brief   Send Event
 */
 #define __SEV                             __builtin_arm_sev
 /**
  \brief   Instruction Synchronization Barrier
 */
 #define __ISB() do {\
                   __schedule_barrier();\
                   __builtin_arm_isb(0xF);\
                   __schedule_barrier();\
                } while (0U)
 /**
  \brief   Data Synchronization Barrier
 */
 #define __DSB() do {\
                   __schedule_barrier();\
                   __builtin_arm_dsb(0xF);\
                   __schedule_barrier();\
                } while (0U)
 /**
  \brief   Data Memory Barrier
 */
 #define __DMB() do {\
                   __schedule_barrier();\
                   __builtin_arm_dmb(0xF);\
                   __schedule_barrier();\
                } while (0U)
 /**
  \brief   Reverse byte order (32 bit)
  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 #define __REV(value)   __builtin_bswap32(value)
 /**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 #define __REV16(value) __ROR(__REV(value), 16)
 /**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 #define __REVSH(value) (int16_t)__builtin_bswap16(value)
 /**
  \brief   Rotate Right in unsigned value (32 bit)
  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
  \param [in]    op1  Value to rotate
  \param [in]    op2  Number of Bits to rotate
  \return               Rotated value
 */
 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 {
  op2 %= 32U;
  if (op2 == 0U)
  {
    return op1;
  }
  return (op1 >> op2) | (op1 << (32U - op2));
 }
 /**
  \brief   Breakpoint
  \param [in]    value  is ignored by the processor.
                 If required, a debugger can use it to store additional information about the breakpoint.
 */
 #define __BKPT(value)   __ASM volatile ("bkpt "#value)
 /**
  \brief   Reverse bit order of value
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 #define __RBIT          __builtin_arm_rbit
 /**
  \brief   Count leading zeros
  \param [in]  value  Value to count the leading zeros
  \return             number of leading zeros in value
 */
 #define __CLZ           (uint8_t)__builtin_clz
 /**
  \brief   LDR Exclusive (8 bit)
  \details Executes a exclusive LDR instruction for 8 bit value.
  \param [in]    ptr  Pointer to data
  \return             value of type uint8_t at (*ptr)
 */
 #define __LDREXB        (uint8_t)__builtin_arm_ldrex
 /**
  \brief   LDR Exclusive (16 bit)
  \details Executes a exclusive LDR instruction for 16 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint16_t at (*ptr)
 */
 #define __LDREXH        (uint16_t)__builtin_arm_ldrex
 /**
  \brief   LDR Exclusive (32 bit)
  \details Executes a exclusive LDR instruction for 32 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint32_t at (*ptr)
 */
 #define __LDREXW        (uint32_t)__builtin_arm_ldrex
 /**
  \brief   STR Exclusive (8 bit)
  \details Executes a exclusive STR instruction for 8 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
 #define __STREXB        (uint32_t)__builtin_arm_strex
 /**
  \brief   STR Exclusive (16 bit)
  \details Executes a exclusive STR instruction for 16 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
 #define __STREXH        (uint32_t)__builtin_arm_strex
 /**
  \brief   STR Exclusive (32 bit)
  \details Executes a exclusive STR instruction for 32 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
 #define __STREXW        (uint32_t)__builtin_arm_strex
 /**
  \brief   Remove the exclusive lock
  \details Removes the exclusive lock which is created by LDREX.
 */
 #define __CLREX             __builtin_arm_clrex
 /**
  \brief   Signed Saturate
  \details Saturates a signed value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (1..32)
  \return             Saturated value
 */
 #define __SSAT             __builtin_arm_ssat
 /**
  \brief   Unsigned Saturate
  \details Saturates an unsigned value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (0..31)
  \return             Saturated value
 */
 #define __USAT             __builtin_arm_usat
 /* ###########################  Core Function Access  ########################### */
 /**
  \brief   Get FPSCR
  \details Returns the current value of the Floating Point Status/Control register.
  \return               Floating Point Status/Control register value
 */
 #define __get_FPSCR      __builtin_arm_get_fpscr
 /**
  \brief   Set FPSCR
  \details Assigns the given value to the Floating Point Status/Control register.
  \param [in]    fpscr  Floating Point Status/Control value to set
 */
 #define __set_FPSCR      __builtin_arm_set_fpscr
 /** \brief  Get CPSR Register
    \return               CPSR Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_CPSR(void)
 {
  uint32_t result;
  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
  return(result);
 }
 /** \brief  Set CPSR Register
    \param [in]    cpsr  CPSR value to set
 */
 __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
 {
 __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
 }
 /** \brief  Get Mode
    \return                Processor Mode
 */
 __STATIC_FORCEINLINE uint32_t __get_mode(void)
 {
 	return (__get_CPSR() & 0x1FU);
 }
 /** \brief  Set Mode
    \param [in]    mode  Mode value to set
 */
 __STATIC_FORCEINLINE void __set_mode(uint32_t mode)
 {
  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
 }
 /** \brief  Get Stack Pointer
    \return Stack Pointer value
 */
 __STATIC_FORCEINLINE uint32_t __get_SP()
 {
  uint32_t result;
  __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
  return result;
 }
 /** \brief  Set Stack Pointer
    \param [in]    stack  Stack Pointer value to set
 */
 __STATIC_FORCEINLINE void __set_SP(uint32_t stack)
 {
  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
 }
 /** \brief  Get USR/SYS Stack Pointer
    \return USR/SYS Stack Pointer value
 */
 __STATIC_FORCEINLINE uint32_t __get_SP_usr()
 {
  uint32_t cpsr;
  uint32_t result;
  __ASM volatile(
    "MRS     %0, cpsr   \n"
    "CPS     #0x1F      \n" // no effect in USR mode
    "MOV     %1, sp     \n"
    "MSR     cpsr_c, %2 \n" // no effect in USR mode
    "ISB" :  "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
   );
  return result;
 }
 /** \brief  Set USR/SYS Stack Pointer
    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
 */
 __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
 {
  uint32_t cpsr;
  __ASM volatile(
    "MRS     %0, cpsr   \n"
    "CPS     #0x1F      \n" // no effect in USR mode
    "MOV     sp, %1     \n"
    "MSR     cpsr_c, %2 \n" // no effect in USR mode
    "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
   );
 }
 /** \brief  Get FPEXC
    \return               Floating Point Exception Control register value
 */
 __STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
 {
 #if (__FPU_PRESENT == 1)
  uint32_t result;
  __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
  return(result);
 #else
  return(0);
 #endif
 }
 /** \brief  Set FPEXC
    \param [in]    fpexc  Floating Point Exception Control value to set
 */
 __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
 {
 #if (__FPU_PRESENT == 1)
  __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
 #endif
 }
 /*
 * Include common core functions to access Coprocessor 15 registers
 */
 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
 #define __get_CP64(cp, op1, Rt, CRm)         __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
 #define __set_CP64(cp, op1, Rt, CRm)         __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
 #include "cmsis_cp15.h"
 /** \brief  Enable Floating Point Unit
  Critical section, called from undef handler, so systick is disabled
 */
 __STATIC_INLINE void __FPU_Enable(void)
 {
  __ASM volatile(
    //Permit access to VFP/NEON, registers by modifying CPACR
    "        MRC     p15,0,R1,c1,c0,2  \n"
    "        ORR     R1,R1,#0x00F00000 \n"
    "        MCR     p15,0,R1,c1,c0,2  \n"
    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
    "        ISB                       \n"
    //Enable VFP/NEON
    "        VMRS    R1,FPEXC          \n"
    "        ORR     R1,R1,#0x40000000 \n"
    "        VMSR    FPEXC,R1          \n"
    //Initialise VFP/NEON registers to 0
    "        MOV     R2,#0             \n"
    //Initialise D16 registers to 0
    "        VMOV    D0, R2,R2         \n"
    "        VMOV    D1, R2,R2         \n"
    "        VMOV    D2, R2,R2         \n"
    "        VMOV    D3, R2,R2         \n"
    "        VMOV    D4, R2,R2         \n"
    "        VMOV    D5, R2,R2         \n"
    "        VMOV    D6, R2,R2         \n"
    "        VMOV    D7, R2,R2         \n"
    "        VMOV    D8, R2,R2         \n"
    "        VMOV    D9, R2,R2         \n"
    "        VMOV    D10,R2,R2         \n"
    "        VMOV    D11,R2,R2         \n"
    "        VMOV    D12,R2,R2         \n"
    "        VMOV    D13,R2,R2         \n"
    "        VMOV    D14,R2,R2         \n"
    "        VMOV    D15,R2,R2         \n"
 #if __ARM_NEON == 1
    //Initialise D32 registers to 0
    "        VMOV    D16,R2,R2         \n"
    "        VMOV    D17,R2,R2         \n"
    "        VMOV    D18,R2,R2         \n"
    "        VMOV    D19,R2,R2         \n"
    "        VMOV    D20,R2,R2         \n"
    "        VMOV    D21,R2,R2         \n"
    "        VMOV    D22,R2,R2         \n"
    "        VMOV    D23,R2,R2         \n"
    "        VMOV    D24,R2,R2         \n"
    "        VMOV    D25,R2,R2         \n"
    "        VMOV    D26,R2,R2         \n"
    "        VMOV    D27,R2,R2         \n"
    "        VMOV    D28,R2,R2         \n"
    "        VMOV    D29,R2,R2         \n"
    "        VMOV    D30,R2,R2         \n"
    "        VMOV    D31,R2,R2         \n"
 #endif
    //Initialise FPSCR to a known state
    "        VMRS    R2,FPSCR          \n"
    "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
    "        AND     R2,R2,R3          \n"
    "        VMSR    FPSCR,R2            "
  );
 }
 #endif /* __CMSIS_ARMCLANG_H */
--- a/target_f1/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h
+++ b/target_f1/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h
@ -1,201 +0,0 @@
 /**************************************************************************//**
 * @file     cmsis_compiler.h
 * @brief    CMSIS compiler specific macros, functions, instructions
 * @version  V1.0.2
 * @date     10. January 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #ifndef __CMSIS_COMPILER_H
 #define __CMSIS_COMPILER_H
 #include <stdint.h>
 /*
 * Arm Compiler 4/5
 */
 #if   defined ( __CC_ARM )
  #include "cmsis_armcc.h"
 /*
 * Arm Compiler 6 (armclang)
 */
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #include "cmsis_armclang.h"
 /*
 * GNU Compiler
 */
 #elif defined ( __GNUC__ )
  #include "cmsis_gcc.h"
 /*
 * IAR Compiler
 */
 #elif defined ( __ICCARM__ )
  #include "cmsis_iccarm.h"
 /*
 * TI Arm Compiler
 */
 #elif defined ( __TI_ARM__ )
  #include <cmsis_ccs.h>
  #ifndef   __ASM
    #define __ASM                     __asm
  #endif
  #ifndef   __INLINE
    #define __INLINE                  inline
  #endif
  #ifndef   __STATIC_INLINE
    #define __STATIC_INLINE           static inline
  #endif
  #ifndef   __STATIC_INLINE
    #define __STATIC_INLINE           static inline
  #endif
  #ifndef   __STATIC_FORCEINLINE
    #define __STATIC_FORCEINLINE      __STATIC_INLINE
  #endif
  #ifndef   __NO_RETURN
    #define __NO_RETURN               __attribute__((noreturn))
  #endif
  #ifndef   CMSIS_DEPRECATED
    #define CMSIS_DEPRECATED          __attribute__((deprecated))
  #endif
  #ifndef   __USED
    #define __USED                    __attribute__((used))
  #endif
  #ifndef   __WEAK
    #define __WEAK                    __attribute__((weak))
  #endif
  #ifndef   __UNALIGNED_UINT32
    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
  #endif
  #ifndef   __ALIGNED
    #define __ALIGNED(x)              __attribute__((aligned(x)))
  #endif
  #ifndef   __PACKED
    #define __PACKED                  __attribute__((packed))
  #endif
 /*
 * TASKING Compiler
 */
 #elif defined ( __TASKING__ )
  /*
   * The CMSIS functions have been implemented as intrinsics in the compiler.
   * Please use "carm -?i" to get an up to date list of all intrinsics,
   * Including the CMSIS ones.
   */
  #ifndef   __ASM
    #define __ASM                     __asm
  #endif
  #ifndef   __INLINE
    #define __INLINE                  inline
  #endif
  #ifndef   __STATIC_INLINE
    #define __STATIC_INLINE           static inline
  #endif
  #ifndef   __STATIC_FORCEINLINE
    #define __STATIC_FORCEINLINE      __STATIC_INLINE
  #endif
  #ifndef   __NO_RETURN
    #define __NO_RETURN               __attribute__((noreturn))
  #endif
  #ifndef   CMSIS_DEPRECATED
    #define CMSIS_DEPRECATED          __attribute__((deprecated))
  #endif
  #ifndef   __USED
    #define __USED                    __attribute__((used))
  #endif
  #ifndef   __WEAK
    #define __WEAK                    __attribute__((weak))
  #endif
  #ifndef   __UNALIGNED_UINT32
    struct __packed__ T_UINT32 { uint32_t v; };
    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
  #endif
  #ifndef   __ALIGNED
    #define __ALIGNED(x)              __align(x)
  #endif
  #ifndef   __PACKED
    #define __PACKED                  __packed__
  #endif
 /*
 * COSMIC Compiler
 */
 #elif defined ( __CSMC__ )
   #include <cmsis_csm.h>
 #ifndef   __ASM
    #define __ASM                     _asm
  #endif
  #ifndef   __INLINE
    #define __INLINE                  inline
  #endif
  #ifndef   __STATIC_INLINE
    #define __STATIC_INLINE           static inline
  #endif
  #ifndef   __STATIC_FORCEINLINE
    #define __STATIC_FORCEINLINE      __STATIC_INLINE
  #endif
  #ifndef   __NO_RETURN
    // NO RETURN is automatically detected hence no warning here
    #define __NO_RETURN
  #endif
  #ifndef   __USED
    #warning No compiler specific solution for __USED. __USED is ignored.
    #define __USED
  #endif
  #ifndef   CMSIS_DEPRECATED
    #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored.
    #define CMSIS_DEPRECATED
  #endif
  #ifndef   __WEAK
    #define __WEAK                    __weak
  #endif
  #ifndef   __UNALIGNED_UINT32
    @packed struct T_UINT32 { uint32_t v; };
    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
  #endif
  #ifndef   __ALIGNED
    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
    #define __ALIGNED(x)
  #endif
  #ifndef   __PACKED
    #define __PACKED                  @packed
  #endif
 #else
  #error Unknown compiler.
 #endif
 #endif /* __CMSIS_COMPILER_H */
--- a/target_f1/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h
+++ b/target_f1/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h
@ -1,514 +0,0 @@
 /**************************************************************************//**
 * @file     cmsis_cp15.h
 * @brief    CMSIS compiler specific macros, functions, instructions
 * @version  V1.0.1
 * @date     07. Sep 2017
 ******************************************************************************/
 /*
 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #if   defined ( __ICCARM__ )
  #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
  #pragma clang system_header   /* treat file as system include file */
 #endif
 #ifndef __CMSIS_CP15_H
 #define __CMSIS_CP15_H
 /** \brief  Get ACTLR
    \return               Auxiliary Control register value
 */
 __STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 1, 0, 1);
  return(result);
 }
 /** \brief  Set ACTLR
    \param [in]    actlr  Auxiliary Control value to set
 */
 __STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
 {
  __set_CP(15, 0, actlr, 1, 0, 1);
 }
 /** \brief  Get CPACR
    \return               Coprocessor Access Control register value
 */
 __STATIC_FORCEINLINE uint32_t __get_CPACR(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 1, 0, 2);
  return result;
 }
 /** \brief  Set CPACR
    \param [in]    cpacr  Coprocessor Access Control value to set
 */
 __STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
 {
  __set_CP(15, 0, cpacr, 1, 0, 2);
 }
 /** \brief  Get DFSR
    \return               Data Fault Status Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_DFSR(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 5, 0, 0);
  return result;
 }
 /** \brief  Set DFSR
    \param [in]    dfsr  Data Fault Status value to set
 */
 __STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
 {
  __set_CP(15, 0, dfsr, 5, 0, 0);
 }
 /** \brief  Get IFSR
    \return               Instruction Fault Status Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_IFSR(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 5, 0, 1);
  return result;
 }
 /** \brief  Set IFSR
    \param [in]    ifsr  Instruction Fault Status value to set
 */
 __STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
 {
  __set_CP(15, 0, ifsr, 5, 0, 1);
 }
 /** \brief  Get ISR
    \return               Interrupt Status Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_ISR(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 12, 1, 0);
  return result;
 }
 /** \brief  Get CBAR
    \return               Configuration Base Address register value
 */
 __STATIC_FORCEINLINE uint32_t __get_CBAR(void)
 {
  uint32_t result;
  __get_CP(15, 4, result, 15, 0, 0);
  return result;
 }
 /** \brief  Get TTBR0
    This function returns the value of the Translation Table Base Register 0.
    \return               Translation Table Base Register 0 value
 */
 __STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 2, 0, 0);
  return result;
 }
 /** \brief  Set TTBR0
    This function assigns the given value to the Translation Table Base Register 0.
    \param [in]    ttbr0  Translation Table Base Register 0 value to set
 */
 __STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
 {
  __set_CP(15, 0, ttbr0, 2, 0, 0);
 }
 /** \brief  Get DACR
    This function returns the value of the Domain Access Control Register.
    \return               Domain Access Control Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_DACR(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 3, 0, 0);
  return result;
 }
 /** \brief  Set DACR
    This function assigns the given value to the Domain Access Control Register.
    \param [in]    dacr   Domain Access Control Register value to set
 */
 __STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
 {
  __set_CP(15, 0, dacr, 3, 0, 0);
 }
 /** \brief  Set SCTLR
    This function assigns the given value to the System Control Register.
    \param [in]    sctlr  System Control Register value to set
 */
 __STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
 {
  __set_CP(15, 0, sctlr, 1, 0, 0);
 }
 /** \brief  Get SCTLR
    \return               System Control Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 1, 0, 0);
  return result;
 }
 /** \brief  Set ACTRL
    \param [in]    actrl  Auxiliary Control Register value to set
 */
 __STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)
 {
  __set_CP(15, 0, actrl, 1, 0, 1);
 }
 /** \brief  Get ACTRL
    \return               Auxiliary Control Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_ACTRL(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 1, 0, 1);
  return result;
 }
 /** \brief  Get MPIDR
    This function returns the value of the Multiprocessor Affinity Register.
    \return               Multiprocessor Affinity Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 0, 0, 5);
  return result;
 }
 /** \brief  Get VBAR
    This function returns the value of the Vector Base Address Register.
    \return               Vector Base Address Register
 */
 __STATIC_FORCEINLINE uint32_t __get_VBAR(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 12, 0, 0);
  return result;
 }
 /** \brief  Set VBAR
    This function assigns the given value to the Vector Base Address Register.
    \param [in]    vbar  Vector Base Address Register value to set
 */
 __STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
 {
  __set_CP(15, 0, vbar, 12, 0, 0);
 }
 /** \brief  Get MVBAR
    This function returns the value of the Monitor Vector Base Address Register.
    \return               Monitor Vector Base Address Register
 */
 __STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 12, 0, 1);
  return result;
 }
 /** \brief  Set MVBAR
    This function assigns the given value to the Monitor Vector Base Address Register.
    \param [in]    mvbar  Monitor Vector Base Address Register value to set
 */
 __STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
 {
  __set_CP(15, 0, mvbar, 12, 0, 1);
 }
 #if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
    defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
    defined(DOXYGEN)
 /** \brief  Set CNTFRQ
  This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
  \param [in]    value  CNTFRQ Register value to set
 */
 __STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
 {
  __set_CP(15, 0, value, 14, 0, 0);
 }
 /** \brief  Get CNTFRQ
    This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
    \return               CNTFRQ Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 14, 0 , 0);
  return result;
 }
 /** \brief  Set CNTP_TVAL
  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
  \param [in]    value  CNTP_TVAL Register value to set
 */
 __STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
 {
  __set_CP(15, 0, value, 14, 2, 0);
 }
 /** \brief  Get CNTP_TVAL
    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
    \return               CNTP_TVAL Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 14, 2, 0);
  return result;
 }
 /** \brief  Get CNTPCT
    This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
    \return               CNTPCT Register value
 */
 __STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
 {
  uint64_t result;
  __get_CP64(15, 0, result, 14);
  return result;
 }
 /** \brief  Set CNTP_CVAL
  This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
  \param [in]    value  CNTP_CVAL Register value to set
 */
 __STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
 {
  __set_CP64(15, 2, value, 14);
 }
 /** \brief  Get CNTP_CVAL
    This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
    \return               CNTP_CVAL Register value
 */
 __STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
 {
  uint64_t result;
  __get_CP64(15, 2, result, 14);
  return result;
 }
 /** \brief  Set CNTP_CTL
  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
  \param [in]    value  CNTP_CTL Register value to set
 */
 __STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
 {
  __set_CP(15, 0, value, 14, 2, 1);
 }
 /** \brief  Get CNTP_CTL register
    \return               CNTP_CTL Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
 {
  uint32_t result;
  __get_CP(15, 0, result, 14, 2, 1);
  return result;
 }
 #endif
 /** \brief  Set TLBIALL
  TLB Invalidate All
 */
 __STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
 {
  __set_CP(15, 0, value, 8, 7, 0);
 }
 /** \brief  Set BPIALL.
  Branch Predictor Invalidate All
 */
 __STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
 {
  __set_CP(15, 0, value, 7, 5, 6);
 }
 /** \brief  Set ICIALLU
  Instruction Cache Invalidate All
 */
 __STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
 {
  __set_CP(15, 0, value, 7, 5, 0);
 }
 /** \brief  Set DCCMVAC
  Data cache clean
 */
 __STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
 {
  __set_CP(15, 0, value, 7, 10, 1);
 }
 /** \brief  Set DCIMVAC
  Data cache invalidate
 */
 __STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
 {
  __set_CP(15, 0, value, 7, 6, 1);
 }
 /** \brief  Set DCCIMVAC
  Data cache clean and invalidate
 */
 __STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
 {
  __set_CP(15, 0, value, 7, 14, 1);
 }
 /** \brief  Set CSSELR
 */
 __STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
 {
 //  __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
  __set_CP(15, 2, value, 0, 0, 0);
 }
 /** \brief  Get CSSELR
    \return CSSELR Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
 {
  uint32_t result;
 //  __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
  __get_CP(15, 2, result, 0, 0, 0);
  return result;
 }
 /** \brief  Set CCSIDR
    \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
 */
 CMSIS_DEPRECATED
 __STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
 {
  __set_CSSELR(value);
 }
 /** \brief  Get CCSIDR
    \return CCSIDR Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
 {
  uint32_t result;
 //  __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
  __get_CP(15, 1, result, 0, 0, 0);
  return result;
 }
 /** \brief  Get CLIDR
    \return CLIDR Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
 {
  uint32_t result;
 //  __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
  __get_CP(15, 1, result, 0, 0, 1);
  return result;
 }
 /** \brief  Set DCISW
 */
 __STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
 {
 //  __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
  __set_CP(15, 0, value, 7, 6, 2);
 }
 /** \brief  Set DCCSW
 */
 __STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
 {
 //  __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
  __set_CP(15, 0, value, 7, 10, 2);
 }
 /** \brief  Set DCCISW
 */
 __STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
 {
 //  __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
  __set_CP(15, 0, value, 7, 14, 2);
 }
 #endif
--- a/target_f1/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h
+++ b/target_f1/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h
@ -1,679 +0,0 @@
 /**************************************************************************//**
 * @file     cmsis_gcc.h
 * @brief    CMSIS compiler specific macros, functions, instructions
 * @version  V1.0.2
 * @date     09. April 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 #ifndef __CMSIS_GCC_H
 #define __CMSIS_GCC_H
 /* ignore some GCC warnings */
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Wsign-conversion"
 #pragma GCC diagnostic ignored "-Wconversion"
 #pragma GCC diagnostic ignored "-Wunused-parameter"
 /* Fallback for __has_builtin */
 #ifndef __has_builtin
  #define __has_builtin(x) (0)
 #endif
 /* CMSIS compiler specific defines */
 #ifndef   __ASM
  #define __ASM                                  asm
 #endif
 #ifndef   __INLINE
  #define __INLINE                               inline
 #endif
 #ifndef   __FORCEINLINE
  #define __FORCEINLINE                          __attribute__((always_inline))
 #endif
 #ifndef   __STATIC_INLINE
  #define __STATIC_INLINE                        static inline
 #endif
 #ifndef   __STATIC_FORCEINLINE
  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
 #endif
 #ifndef   __NO_RETURN
  #define __NO_RETURN                            __attribute__((__noreturn__))
 #endif
 #ifndef   CMSIS_DEPRECATED
 #define  CMSIS_DEPRECATED                       __attribute__((deprecated))
 #endif
 #ifndef   __USED
  #define __USED                                 __attribute__((used))
 #endif
 #ifndef   __WEAK
  #define __WEAK                                 __attribute__((weak))
 #endif
 #ifndef   __PACKED
  #define __PACKED                               __attribute__((packed, aligned(1)))
 #endif
 #ifndef   __PACKED_STRUCT
  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
 #endif
 #ifndef   __UNALIGNED_UINT16_WRITE
  #pragma GCC diagnostic push
  #pragma GCC diagnostic ignored "-Wpacked"
 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  #pragma GCC diagnostic pop
  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT16_READ
  #pragma GCC diagnostic push
  #pragma GCC diagnostic ignored "-Wpacked"
 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  #pragma GCC diagnostic pop
  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
 #endif
 #ifndef   __UNALIGNED_UINT32_WRITE
  #pragma GCC diagnostic push
  #pragma GCC diagnostic ignored "-Wpacked"
 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  #pragma GCC diagnostic pop
  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
 #endif
 #ifndef   __UNALIGNED_UINT32_READ
  #pragma GCC diagnostic push
  #pragma GCC diagnostic ignored "-Wpacked"
  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
  #pragma GCC diagnostic pop
  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
 #endif
 #ifndef   __ALIGNED
  #define __ALIGNED(x)                           __attribute__((aligned(x)))
 #endif
 /* ##########################  Core Instruction Access  ######################### */
 /**
  \brief   No Operation
 */
 #define __NOP()                             __ASM volatile ("nop")
 /**
  \brief   Wait For Interrupt
 */
 #define __WFI()                             __ASM volatile ("wfi")
 /**
  \brief   Wait For Event
 */
 #define __WFE()                             __ASM volatile ("wfe")
 /**
  \brief   Send Event
 */
 #define __SEV()                             __ASM volatile ("sev")
 /**
  \brief   Instruction Synchronization Barrier
  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
           so that all instructions following the ISB are fetched from cache or memory,
           after the instruction has been completed.
 */
 __STATIC_FORCEINLINE  void __ISB(void)
 {
  __ASM volatile ("isb 0xF":::"memory");
 }
 /**
  \brief   Data Synchronization Barrier
  \details Acts as a special kind of Data Memory Barrier.
           It completes when all explicit memory accesses before this instruction complete.
 */
 __STATIC_FORCEINLINE  void __DSB(void)
 {
  __ASM volatile ("dsb 0xF":::"memory");
 }
 /**
  \brief   Data Memory Barrier
  \details Ensures the apparent order of the explicit memory operations before
           and after the instruction, without ensuring their completion.
 */
 __STATIC_FORCEINLINE  void __DMB(void)
 {
  __ASM volatile ("dmb 0xF":::"memory");
 }
 /**
  \brief   Reverse byte order (32 bit)
  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 __STATIC_FORCEINLINE  uint32_t __REV(uint32_t value)
 {
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
  return __builtin_bswap32(value);
 #else
  uint32_t result;
  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
  return result;
 #endif
 }
 /**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
 {
  uint32_t result;
  __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
  return result;
 }
 #endif
 /**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 __STATIC_FORCEINLINE  int16_t __REVSH(int16_t value)
 {
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
  return (int16_t)__builtin_bswap16(value);
 #else
  int16_t result;
  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
  return result;
 #endif
 }
 /**
  \brief   Rotate Right in unsigned value (32 bit)
  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
  \param [in]    op1  Value to rotate
  \param [in]    op2  Number of Bits to rotate
  \return               Rotated value
 */
 __STATIC_FORCEINLINE  uint32_t __ROR(uint32_t op1, uint32_t op2)
 {
  op2 %= 32U;
  if (op2 == 0U) {
    return op1;
  }
  return (op1 >> op2) | (op1 << (32U - op2));
 }
 /**
  \brief   Breakpoint
  \param [in]    value  is ignored by the processor.
                 If required, a debugger can use it to store additional information about the breakpoint.
 */
 #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
 /**
  \brief   Reverse bit order of value
  \details Reverses the bit order of the given value.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
 __STATIC_FORCEINLINE  uint32_t __RBIT(uint32_t value)
 {
  uint32_t result;
 #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 #else
  int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
  result = value;                      /* r will be reversed bits of v; first get LSB of v */
  for (value >>= 1U; value; value >>= 1U)
  {
    result <<= 1U;
    result |= value & 1U;
    s--;
  }
  result <<= s;                        /* shift when v's highest bits are zero */
 #endif
  return result;
 }
 /**
  \brief   Count leading zeros
  \param [in]  value  Value to count the leading zeros
  \return             number of leading zeros in value
 */
 #define __CLZ                             (uint8_t)__builtin_clz
 /**
  \brief   LDR Exclusive (8 bit)
  \details Executes a exclusive LDR instruction for 8 bit value.
  \param [in]    ptr  Pointer to data
  \return             value of type uint8_t at (*ptr)
 */
 __STATIC_FORCEINLINE  uint8_t __LDREXB(volatile uint8_t *addr)
 {
    uint32_t result;
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
 #else
    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
       accepted by assembler. So has to use following less efficient pattern.
    */
   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 #endif
   return ((uint8_t) result);    /* Add explicit type cast here */
 }
 /**
  \brief   LDR Exclusive (16 bit)
  \details Executes a exclusive LDR instruction for 16 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint16_t at (*ptr)
 */
 __STATIC_FORCEINLINE  uint16_t __LDREXH(volatile uint16_t *addr)
 {
    uint32_t result;
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
 #else
    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
       accepted by assembler. So has to use following less efficient pattern.
    */
   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 #endif
   return ((uint16_t) result);    /* Add explicit type cast here */
 }
 /**
  \brief   LDR Exclusive (32 bit)
  \details Executes a exclusive LDR instruction for 32 bit values.
  \param [in]    ptr  Pointer to data
  \return        value of type uint32_t at (*ptr)
 */
 __STATIC_FORCEINLINE  uint32_t __LDREXW(volatile uint32_t *addr)
 {
    uint32_t result;
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
   return(result);
 }
 /**
  \brief   STR Exclusive (8 bit)
  \details Executes a exclusive STR instruction for 8 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
 __STATIC_FORCEINLINE  uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
 {
   uint32_t result;
   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
   return(result);
 }
 /**
  \brief   STR Exclusive (16 bit)
  \details Executes a exclusive STR instruction for 16 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
 __STATIC_FORCEINLINE  uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
 {
   uint32_t result;
   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
   return(result);
 }
 /**
  \brief   STR Exclusive (32 bit)
  \details Executes a exclusive STR instruction for 32 bit values.
  \param [in]  value  Value to store
  \param [in]    ptr  Pointer to location
  \return          0  Function succeeded
  \return          1  Function failed
 */
 __STATIC_FORCEINLINE  uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
 {
   uint32_t result;
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
   return(result);
 }
 /**
  \brief   Remove the exclusive lock
  \details Removes the exclusive lock which is created by LDREX.
 */
 __STATIC_FORCEINLINE  void __CLREX(void)
 {
  __ASM volatile ("clrex" ::: "memory");
 }
 /**
  \brief   Signed Saturate
  \details Saturates a signed value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (1..32)
  \return             Saturated value
 */
 #define __SSAT(ARG1,ARG2) \
 __extension__ \
 ({                          \
  int32_t __RES, __ARG1 = (ARG1); \
  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
  __RES; \
 })
 /**
  \brief   Unsigned Saturate
  \details Saturates an unsigned value.
  \param [in]  value  Value to be saturated
  \param [in]    sat  Bit position to saturate to (0..31)
  \return             Saturated value
 */
 #define __USAT(ARG1,ARG2) \
 __extension__ \
 ({                          \
  uint32_t __RES, __ARG1 = (ARG1); \
  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
  __RES; \
 })
 /* ###########################  Core Function Access  ########################### */
 /**
  \brief   Enable IRQ Interrupts
  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
 __STATIC_FORCEINLINE void __enable_irq(void)
 {
  __ASM volatile ("cpsie i" : : : "memory");
 }
 /**
  \brief   Disable IRQ Interrupts
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
  Can only be executed in Privileged modes.
 */
 __STATIC_FORCEINLINE  void __disable_irq(void)
 {
  __ASM volatile ("cpsid i" : : : "memory");
 }
 /**
  \brief   Get FPSCR
  \details Returns the current value of the Floating Point Status/Control register.
  \return Floating Point Status/Control register value
 */
 __STATIC_FORCEINLINE  uint32_t __get_FPSCR(void)
 {
  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
  #if __has_builtin(__builtin_arm_get_fpscr) 
  // Re-enable using built-in when GCC has been fixed
  // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
    return __builtin_arm_get_fpscr();
  #else
    uint32_t result;
    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
    return(result);
  #endif
  #else
    return(0U);
  #endif
 }
 /**
  \brief   Set FPSCR
  \details Assigns the given value to the Floating Point Status/Control register.
  \param [in] fpscr  Floating Point Status/Control value to set
 */
 __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
 {
  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
  #if __has_builtin(__builtin_arm_set_fpscr)
  // Re-enable using built-in when GCC has been fixed
  // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
    __builtin_arm_set_fpscr(fpscr);
  #else
    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
  #endif
  #else
    (void)fpscr;
  #endif
 }
 /** \brief  Get CPSR Register
    \return               CPSR Register value
 */
 __STATIC_FORCEINLINE uint32_t __get_CPSR(void)
 {
  uint32_t result;
  __ASM volatile("MRS %0, cpsr" : "=r" (result) );
  return(result);
 }
 /** \brief  Set CPSR Register
    \param [in]    cpsr  CPSR value to set
 */
 __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
 {
 __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
 }
 /** \brief  Get Mode
    \return                Processor Mode
 */
 __STATIC_FORCEINLINE uint32_t __get_mode(void)
 {
    return (__get_CPSR() & 0x1FU);
 }
 /** \brief  Set Mode
    \param [in]    mode  Mode value to set
 */
 __STATIC_FORCEINLINE void __set_mode(uint32_t mode)
 {
  __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
 }
 /** \brief  Get Stack Pointer
    \return Stack Pointer value
 */
 __STATIC_FORCEINLINE uint32_t __get_SP(void)
 {
  uint32_t result;
  __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
  return result;
 }
 /** \brief  Set Stack Pointer
    \param [in]    stack  Stack Pointer value to set
 */
 __STATIC_FORCEINLINE void __set_SP(uint32_t stack)
 {
  __ASM volatile("MOV  sp, %0" : : "r" (stack) : "memory");
 }
 /** \brief  Get USR/SYS Stack Pointer
    \return USR/SYS Stack Pointer value
 */
 __STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
 {
  uint32_t cpsr = __get_CPSR();
  uint32_t result;
  __ASM volatile(
    "CPS     #0x1F  \n"
    "MOV     %0, sp   " : "=r"(result) : : "memory"
   );
  __set_CPSR(cpsr);
  __ISB();
  return result;
 }
 /** \brief  Set USR/SYS Stack Pointer
    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
 */
 __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
 {
  uint32_t cpsr = __get_CPSR();
  __ASM volatile(
    "CPS     #0x1F  \n"
    "MOV     sp, %0   " : : "r" (topOfProcStack) : "memory"
   );
  __set_CPSR(cpsr);
  __ISB();
 }
 /** \brief  Get FPEXC
    \return               Floating Point Exception Control register value
 */
 __STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
 {
 #if (__FPU_PRESENT == 1)
  uint32_t result;
  __ASM volatile("VMRS %0, fpexc" : "=r" (result) );
  return(result);
 #else
  return(0);
 #endif
 }
 /** \brief  Set FPEXC
    \param [in]    fpexc  Floating Point Exception Control value to set
 */
 __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
 {
 #if (__FPU_PRESENT == 1)
  __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
 #endif
 }
 /*
 * Include common core functions to access Coprocessor 15 registers
 */
 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
 #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
 #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
 #include "cmsis_cp15.h"
 /** \brief  Enable Floating Point Unit
  Critical section, called from undef handler, so systick is disabled
 */
 __STATIC_INLINE void __FPU_Enable(void)
 {
  __ASM volatile(
    //Permit access to VFP/NEON, registers by modifying CPACR
    "        MRC     p15,0,R1,c1,c0,2  \n"
    "        ORR     R1,R1,#0x00F00000 \n"
    "        MCR     p15,0,R1,c1,c0,2  \n"
    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
    "        ISB                       \n"
    //Enable VFP/NEON
    "        VMRS    R1,FPEXC          \n"
    "        ORR     R1,R1,#0x40000000 \n"
    "        VMSR    FPEXC,R1          \n"
    //Initialise VFP/NEON registers to 0
    "        MOV     R2,#0             \n"
    //Initialise D16 registers to 0
    "        VMOV    D0, R2,R2         \n"
    "        VMOV    D1, R2,R2         \n"
    "        VMOV    D2, R2,R2         \n"
    "        VMOV    D3, R2,R2         \n"
    "        VMOV    D4, R2,R2         \n"
    "        VMOV    D5, R2,R2         \n"
    "        VMOV    D6, R2,R2         \n"
    "        VMOV    D7, R2,R2         \n"
    "        VMOV    D8, R2,R2         \n"
    "        VMOV    D9, R2,R2         \n"
    "        VMOV    D10,R2,R2         \n"
    "        VMOV    D11,R2,R2         \n"
    "        VMOV    D12,R2,R2         \n"
    "        VMOV    D13,R2,R2         \n"
    "        VMOV    D14,R2,R2         \n"
    "        VMOV    D15,R2,R2         \n"
 #if (defined(__ARM_NEON) && (__ARM_NEON == 1))
    //Initialise D32 registers to 0
    "        VMOV    D16,R2,R2         \n"
    "        VMOV    D17,R2,R2         \n"
    "        VMOV    D18,R2,R2         \n"
    "        VMOV    D19,R2,R2         \n"
    "        VMOV    D20,R2,R2         \n"
    "        VMOV    D21,R2,R2         \n"
    "        VMOV    D22,R2,R2         \n"
    "        VMOV    D23,R2,R2         \n"
    "        VMOV    D24,R2,R2         \n"
    "        VMOV    D25,R2,R2         \n"
    "        VMOV    D26,R2,R2         \n"
    "        VMOV    D27,R2,R2         \n"
    "        VMOV    D28,R2,R2         \n"
    "        VMOV    D29,R2,R2         \n"
    "        VMOV    D30,R2,R2         \n"
    "        VMOV    D31,R2,R2         \n"
 #endif
    //Initialise FPSCR to a known state
    "        VMRS    R2,FPSCR          \n"
    "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
    "        AND     R2,R2,R3          \n"
    "        VMSR    FPSCR,R2            "
  );
 }
 #pragma GCC diagnostic pop
 #endif /* __CMSIS_GCC_H */
--- a/target_f1/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h
+++ b/target_f1/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h
@ -1,559 +0,0 @@
 /**************************************************************************//**
 * @file     cmsis_iccarm.h
 * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
 * @version  V5.0.6
 * @date     02. March 2018
 ******************************************************************************/
 //------------------------------------------------------------------------------
 //
 // Copyright (c) 2017-2018 IAR Systems
 //
 // Licensed under the Apache License, Version 2.0 (the "License")
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //     http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
 //
 //------------------------------------------------------------------------------
 #ifndef __CMSIS_ICCARM_H__
 #define __CMSIS_ICCARM_H__
 #ifndef __ICCARM__
  #error This file should only be compiled by ICCARM
 #endif
 #pragma system_include
 #define __IAR_FT _Pragma("inline=forced") __intrinsic
 #if (__VER__ >= 8000000)
  #define __ICCARM_V8 1
 #else
  #define __ICCARM_V8 0
 #endif
 #pragma language=extended
 #ifndef __ALIGNED
  #if __ICCARM_V8
    #define __ALIGNED(x) __attribute__((aligned(x)))
  #elif (__VER__ >= 7080000)
    /* Needs IAR language extensions */
    #define __ALIGNED(x) __attribute__((aligned(x)))
  #else
    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
    #define __ALIGNED(x)
  #endif
 #endif
 /* Define compiler macros for CPU architecture, used in CMSIS 5.
 */
 #if __ARM_ARCH_7A__
 /* Macro already defined */
 #else
  #if defined(__ARM7A__)
    #define __ARM_ARCH_7A__ 1
  #endif
 #endif
 #ifndef __ASM
  #define __ASM __asm
 #endif
 #ifndef __INLINE
  #define __INLINE inline
 #endif
 #ifndef   __NO_RETURN
  #if __ICCARM_V8
    #define __NO_RETURN __attribute__((__noreturn__))
  #else
    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
  #endif
 #endif
 #ifndef   __PACKED
  /* Needs IAR language extensions */
  #if __ICCARM_V8
    #define __PACKED __attribute__((packed, aligned(1)))
  #else
    #define __PACKED __packed
  #endif
 #endif
 #ifndef   __PACKED_STRUCT
  /* Needs IAR language extensions */
  #if __ICCARM_V8
    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
  #else
    #define __PACKED_STRUCT __packed struct
  #endif
 #endif
 #ifndef   __PACKED_UNION
  /* Needs IAR language extensions */
  #if __ICCARM_V8
    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
  #else
    #define __PACKED_UNION __packed union
  #endif
 #endif
 #ifndef   __RESTRICT
  #define __RESTRICT            __restrict
 #endif
 #ifndef   __STATIC_INLINE
  #define __STATIC_INLINE       static inline
 #endif
 #ifndef   __FORCEINLINE
  #define __FORCEINLINE         _Pragma("inline=forced")
 #endif
 #ifndef   __STATIC_FORCEINLINE
  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
 #endif
 #ifndef   CMSIS_DEPRECATED
  #define CMSIS_DEPRECATED      __attribute__((deprecated))
 #endif
 #ifndef __UNALIGNED_UINT16_READ
  #pragma language=save
  #pragma language=extended
  __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
  {
    return *(__packed uint16_t*)(ptr);
  }
  #pragma language=restore
  #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
 #endif
 #ifndef __UNALIGNED_UINT16_WRITE
  #pragma language=save
  #pragma language=extended
  __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
  {
    *(__packed uint16_t*)(ptr) = val;;
  }
  #pragma language=restore
  #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
 #endif
 #ifndef __UNALIGNED_UINT32_READ
  #pragma language=save
  #pragma language=extended
  __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
  {
    return *(__packed uint32_t*)(ptr);
  }
  #pragma language=restore
  #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
 #endif
 #ifndef __UNALIGNED_UINT32_WRITE
  #pragma language=save
  #pragma language=extended
  __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
  {
    *(__packed uint32_t*)(ptr) = val;;
  }
  #pragma language=restore
  #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
 #endif
 #if 0
 #ifndef __UNALIGNED_UINT32   /* deprecated */
  #pragma language=save
  #pragma language=extended
  __packed struct  __iar_u32 { uint32_t v; };
  #pragma language=restore
  #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
 #endif
 #endif
 #ifndef   __USED
  #if __ICCARM_V8
    #define __USED __attribute__((used))
  #else
    #define __USED _Pragma("__root")
  #endif
 #endif
 #ifndef   __WEAK
  #if __ICCARM_V8
    #define __WEAK __attribute__((weak))
  #else
    #define __WEAK _Pragma("__weak")
  #endif
 #endif
 #ifndef __ICCARM_INTRINSICS_VERSION__
  #define __ICCARM_INTRINSICS_VERSION__  0
 #endif
 #if __ICCARM_INTRINSICS_VERSION__ == 2
  #if defined(__CLZ)
    #undef __CLZ
  #endif
  #if defined(__REVSH)
    #undef __REVSH
  #endif
  #if defined(__RBIT)
    #undef __RBIT
  #endif
  #if defined(__SSAT)
    #undef __SSAT
  #endif
  #if defined(__USAT)
    #undef __USAT
  #endif
  #include "iccarm_builtin.h"
  #define __enable_irq        __iar_builtin_enable_interrupt
  #define __disable_irq       __iar_builtin_disable_interrupt
  #define __enable_fault_irq    __iar_builtin_enable_fiq
  #define __disable_fault_irq   __iar_builtin_disable_fiq
  #define __arm_rsr           __iar_builtin_rsr
  #define __arm_wsr           __iar_builtin_wsr
  #if __FPU_PRESENT
    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
  #else
    #define __get_FPSCR()             ( 0 )
  #endif
  #define __set_FPSCR(VALUE)          (__arm_wsr("FPSCR", VALUE))
  #define __get_CPSR()                (__arm_rsr("CPSR"))
  #define __get_mode()                (__get_CPSR() & 0x1FU)
  #define __set_CPSR(VALUE)           (__arm_wsr("CPSR", (VALUE)))
  #define __set_mode(VALUE)           (__arm_wsr("CPSR_c", (VALUE)))
  #define __get_FPEXC()       (__arm_rsr("FPEXC"))
  #define __set_FPEXC(VALUE)    (__arm_wsr("FPEXC", VALUE))
  #define __get_CP(cp, op1, RT, CRn, CRm, op2) \
    ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
  #define __set_CP(cp, op1, RT, CRn, CRm, op2) \
    (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
  #define __get_CP64(cp, op1, Rt, CRm) \
    __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
  #define __set_CP64(cp, op1, Rt, CRm) \
    __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
  #include "cmsis_cp15.h"
  #define __NOP     __iar_builtin_no_operation
  #define __CLZ     __iar_builtin_CLZ
  #define __CLREX   __iar_builtin_CLREX
  #define __DMB     __iar_builtin_DMB
  #define __DSB     __iar_builtin_DSB
  #define __ISB     __iar_builtin_ISB
  #define __LDREXB  __iar_builtin_LDREXB
  #define __LDREXH  __iar_builtin_LDREXH
  #define __LDREXW  __iar_builtin_LDREX
  #define __RBIT    __iar_builtin_RBIT
  #define __REV     __iar_builtin_REV
  #define __REV16   __iar_builtin_REV16
  __IAR_FT int16_t __REVSH(int16_t val)
  {
    return (int16_t) __iar_builtin_REVSH(val);
  }
  #define __ROR     __iar_builtin_ROR
  #define __RRX     __iar_builtin_RRX
  #define __SEV     __iar_builtin_SEV
  #define __SSAT    __iar_builtin_SSAT
  #define __STREXB  __iar_builtin_STREXB
  #define __STREXH  __iar_builtin_STREXH
  #define __STREXW  __iar_builtin_STREX
  #define __USAT    __iar_builtin_USAT
  #define __WFE     __iar_builtin_WFE
  #define __WFI     __iar_builtin_WFI
  #define __SADD8   __iar_builtin_SADD8
  #define __QADD8   __iar_builtin_QADD8
  #define __SHADD8  __iar_builtin_SHADD8
  #define __UADD8   __iar_builtin_UADD8
  #define __UQADD8  __iar_builtin_UQADD8
  #define __UHADD8  __iar_builtin_UHADD8
  #define __SSUB8   __iar_builtin_SSUB8
  #define __QSUB8   __iar_builtin_QSUB8
  #define __SHSUB8  __iar_builtin_SHSUB8
  #define __USUB8   __iar_builtin_USUB8
  #define __UQSUB8  __iar_builtin_UQSUB8
  #define __UHSUB8  __iar_builtin_UHSUB8
  #define __SADD16  __iar_builtin_SADD16
  #define __QADD16  __iar_builtin_QADD16
  #define __SHADD16 __iar_builtin_SHADD16
  #define __UADD16  __iar_builtin_UADD16
  #define __UQADD16 __iar_builtin_UQADD16
  #define __UHADD16 __iar_builtin_UHADD16
  #define __SSUB16  __iar_builtin_SSUB16
  #define __QSUB16  __iar_builtin_QSUB16
  #define __SHSUB16 __iar_builtin_SHSUB16
  #define __USUB16  __iar_builtin_USUB16
  #define __UQSUB16 __iar_builtin_UQSUB16
  #define __UHSUB16 __iar_builtin_UHSUB16
  #define __SASX    __iar_builtin_SASX
  #define __QASX    __iar_builtin_QASX
  #define __SHASX   __iar_builtin_SHASX
  #define __UASX    __iar_builtin_UASX
  #define __UQASX   __iar_builtin_UQASX
  #define __UHASX   __iar_builtin_UHASX
  #define __SSAX    __iar_builtin_SSAX
  #define __QSAX    __iar_builtin_QSAX
  #define __SHSAX   __iar_builtin_SHSAX
  #define __USAX    __iar_builtin_USAX
  #define __UQSAX   __iar_builtin_UQSAX
  #define __UHSAX   __iar_builtin_UHSAX
  #define __USAD8   __iar_builtin_USAD8
  #define __USADA8  __iar_builtin_USADA8
  #define __SSAT16  __iar_builtin_SSAT16
  #define __USAT16  __iar_builtin_USAT16
  #define __UXTB16  __iar_builtin_UXTB16
  #define __UXTAB16 __iar_builtin_UXTAB16
  #define __SXTB16  __iar_builtin_SXTB16
  #define __SXTAB16 __iar_builtin_SXTAB16
  #define __SMUAD   __iar_builtin_SMUAD
  #define __SMUADX  __iar_builtin_SMUADX
  #define __SMMLA   __iar_builtin_SMMLA
  #define __SMLAD   __iar_builtin_SMLAD
  #define __SMLADX  __iar_builtin_SMLADX
  #define __SMLALD  __iar_builtin_SMLALD
  #define __SMLALDX __iar_builtin_SMLALDX
  #define __SMUSD   __iar_builtin_SMUSD
  #define __SMUSDX  __iar_builtin_SMUSDX
  #define __SMLSD   __iar_builtin_SMLSD
  #define __SMLSDX  __iar_builtin_SMLSDX
  #define __SMLSLD  __iar_builtin_SMLSLD
  #define __SMLSLDX __iar_builtin_SMLSLDX
  #define __SEL     __iar_builtin_SEL
  #define __QADD    __iar_builtin_QADD
  #define __QSUB    __iar_builtin_QSUB
  #define __PKHBT   __iar_builtin_PKHBT
  #define __PKHTB   __iar_builtin_PKHTB
 #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
  #if !__FPU_PRESENT
  #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
  #endif
  #ifdef __INTRINSICS_INCLUDED
  #error intrinsics.h is already included previously!
  #endif
  #include <intrinsics.h>
  #if !__FPU_PRESENT
  #define __get_FPSCR() (0)
  #endif
  #pragma diag_suppress=Pe940
  #pragma diag_suppress=Pe177
  #define __enable_irq        __enable_interrupt
  #define __disable_irq       __disable_interrupt
  #define __enable_fault_irq    __enable_fiq
  #define __disable_fault_irq   __disable_fiq
  #define __NOP               __no_operation
  #define __get_xPSR          __get_PSR
  __IAR_FT void __set_mode(uint32_t mode)
  {
    __ASM volatile("MSR  cpsr_c, %0" : : "r" (mode) : "memory");
  }
  __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
  {
    return __LDREX((unsigned long *)ptr);
  }
  __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
  {
    return __STREX(value, (unsigned long *)ptr);
  }
  __IAR_FT uint32_t __RRX(uint32_t value)
  {
    uint32_t result;
    __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
    return(result);
  }
  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
  {
    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
  }
  __IAR_FT uint32_t __get_FPEXC(void)
  {
  #if (__FPU_PRESENT == 1)
    uint32_t result;
    __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
    return(result);
  #else
    return(0);
  #endif
  }
  __IAR_FT void __set_FPEXC(uint32_t fpexc)
  {
  #if (__FPU_PRESENT == 1)
    __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
  #endif
  }
  #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \
    __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
  #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
    __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
  #define __get_CP64(cp, op1, Rt, CRm) \
    __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
  #define __set_CP64(cp, op1, Rt, CRm) \
    __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
  #include "cmsis_cp15.h"
 #endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
 #define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
 __IAR_FT uint32_t __get_SP_usr(void)
 {
  uint32_t cpsr;
  uint32_t result;
  __ASM volatile(
    "MRS     %0, cpsr   \n"
    "CPS     #0x1F      \n" // no effect in USR mode
    "MOV     %1, sp     \n"
    "MSR     cpsr_c, %2 \n" // no effect in USR mode
    "ISB" :  "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
   );
  return result;
 }
 __IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
 {
  uint32_t cpsr;
  __ASM volatile(
    "MRS     %0, cpsr   \n"
    "CPS     #0x1F      \n" // no effect in USR mode
    "MOV     sp, %1     \n"
    "MSR     cpsr_c, %2 \n" // no effect in USR mode
    "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
   );
 }
 #define __get_mode()                (__get_CPSR() & 0x1FU)
 __STATIC_INLINE
 void __FPU_Enable(void)
 {
  __ASM volatile(
    //Permit access to VFP/NEON, registers by modifying CPACR
    "        MRC     p15,0,R1,c1,c0,2  \n"
    "        ORR     R1,R1,#0x00F00000 \n"
    "        MCR     p15,0,R1,c1,c0,2  \n"
    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
    "        ISB                       \n"
    //Enable VFP/NEON
    "        VMRS    R1,FPEXC          \n"
    "        ORR     R1,R1,#0x40000000 \n"
    "        VMSR    FPEXC,R1          \n"
    //Initialise VFP/NEON registers to 0
    "        MOV     R2,#0             \n"
    //Initialise D16 registers to 0
    "        VMOV    D0, R2,R2         \n"
    "        VMOV    D1, R2,R2         \n"
    "        VMOV    D2, R2,R2         \n"
    "        VMOV    D3, R2,R2         \n"
    "        VMOV    D4, R2,R2         \n"
    "        VMOV    D5, R2,R2         \n"
    "        VMOV    D6, R2,R2         \n"
    "        VMOV    D7, R2,R2         \n"
    "        VMOV    D8, R2,R2         \n"
    "        VMOV    D9, R2,R2         \n"
    "        VMOV    D10,R2,R2         \n"
    "        VMOV    D11,R2,R2         \n"
    "        VMOV    D12,R2,R2         \n"
    "        VMOV    D13,R2,R2         \n"
    "        VMOV    D14,R2,R2         \n"
    "        VMOV    D15,R2,R2         \n"
 #ifdef __ARM_ADVANCED_SIMD__
    //Initialise D32 registers to 0
    "        VMOV    D16,R2,R2         \n"
    "        VMOV    D17,R2,R2         \n"
    "        VMOV    D18,R2,R2         \n"
    "        VMOV    D19,R2,R2         \n"
    "        VMOV    D20,R2,R2         \n"
    "        VMOV    D21,R2,R2         \n"
    "        VMOV    D22,R2,R2         \n"
    "        VMOV    D23,R2,R2         \n"
    "        VMOV    D24,R2,R2         \n"
    "        VMOV    D25,R2,R2         \n"
    "        VMOV    D26,R2,R2         \n"
    "        VMOV    D27,R2,R2         \n"
    "        VMOV    D28,R2,R2         \n"
    "        VMOV    D29,R2,R2         \n"
    "        VMOV    D30,R2,R2         \n"
    "        VMOV    D31,R2,R2         \n"
 #endif
    //Initialise FPSCR to a known state
    "        VMRS    R2,FPSCR          \n"
    "        MOV32   R3,#0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
    "        AND     R2,R2,R3          \n"
    "        VMSR    FPSCR,R2          \n");
 }
 #undef __IAR_FT
 #undef __ICCARM_V8
 #pragma diag_default=Pe940
 #pragma diag_default=Pe177
 #endif /* __CMSIS_ICCARM_H__ */
--- a/target_f1/Drivers/CMSIS/Core_A/Include/core_ca.h
+++ b/target_f1/Drivers/CMSIS/Core_A/Include/core_ca.h
--- a/Show More
+++ b/Show More
		`@ -0,0 +1 @@`
							`Subproject commit d023c0d560ace11509f9b761c8913a9e48fcf194`