[FL-3375] SubGhz: add CC1101 module external (#2747)
* SubGhz: add CC1101 Ext driver * SubGhz: move TIM2 -> TIM17 use cc1101_ext * FuriHal: SPI move channel DMA 3,4 -> 6.7 * Documentation: fix font * SubGhz: add work with SubGhz devices by link to device * SubGhz: add support switching external/internal cc1101 "subghz chat" * SubGhz: add support switching external/internal cc1101 "subghz tx" and "subghz rx" * SubGhz: add "Radio Settings" scene * SubGhz: add icon * SubGhz: add supported CC1101 external module in SubGhz app * SubGhz: fix check frequency supported radio device * SubGhz: fix clang-formatted * Sughz: move dirver CC1101_Ext to lib , compile cmd ./fbt launch_app APPSRC=radio_device_cc1101_ext * SubGhz: fix CLI * SubGhz: fix PVS * SubGhz: delete comments * SubGhz: fix unit_test * Format sources * Update api symbols and drivers targets * Drivers: find proper place for target option * SubGhz: external device connected method naming * Format sources * SubGhz: fix module selection menu, when external is not connected * SubGhz: fix furi_assert(device); * SubGhz: fix split h and c * SubGhz: furi_hal_subghz remove preset load function by name * SubGhz: deleted comments * Format Sources * SubGhz: add some consts and fix unit tests * Sync API Symbols Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com>
This commit is contained in:
Skorpionm
co-authored by
Aleksandr Kutuzov
Aleksandr Kutuzov
parent
6d9de25494
commit
8c93695d01
@@ -0,0 +1,431 @@
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#include "cc1101_configs.h"
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#include <cc1101_regs.h>
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const uint8_t subghz_device_cc1101_preset_ook_270khz_async_regs[] = {
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// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
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/* GPIO GD0 */
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CC1101_IOCFG0,
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0x0D, // GD0 as async serial data output/input
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/* FIFO and internals */
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CC1101_FIFOTHR,
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0x47, // The only important bit is ADC_RETENTION, FIFO Tx=33 Rx=32
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/* Packet engine */
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CC1101_PKTCTRL0,
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0x32, // Async, continious, no whitening
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/* Frequency Synthesizer Control */
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CC1101_FSCTRL1,
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0x06, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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// Modem Configuration
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CC1101_MDMCFG0,
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0x00, // Channel spacing is 25kHz
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CC1101_MDMCFG1,
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0x00, // Channel spacing is 25kHz
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CC1101_MDMCFG2,
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0x30, // Format ASK/OOK, No preamble/sync
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CC1101_MDMCFG3,
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0x32, // Data rate is 3.79372 kBaud
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CC1101_MDMCFG4,
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0x67, // Rx BW filter is 270.833333kHz
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/* Main Radio Control State Machine */
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CC1101_MCSM0,
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0x18, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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CC1101_FOCCFG,
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0x18, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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CC1101_AGCCTRL0,
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0x40, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
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CC1101_AGCCTRL1,
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0x00, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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CC1101_AGCCTRL2,
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0x03, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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/* Wake on radio and timeouts control */
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CC1101_WORCTRL,
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0xFB, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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CC1101_FREND0,
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0x11, // Adjusts current TX LO buffer + high is PATABLE[1]
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CC1101_FREND1,
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0xB6, //
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/* End load reg */
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0,
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0,
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//ook_async_patable[8]
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0x00,
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0xC0, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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};
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const uint8_t subghz_device_cc1101_preset_ook_650khz_async_regs[] = {
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// https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz-group/sub-1-ghz/f/sub-1-ghz-forum/382066/cc1101---don-t-know-the-correct-registers-configuration
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/* GPIO GD0 */
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CC1101_IOCFG0,
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0x0D, // GD0 as async serial data output/input
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/* FIFO and internals */
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CC1101_FIFOTHR,
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0x07, // The only important bit is ADC_RETENTION
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/* Packet engine */
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CC1101_PKTCTRL0,
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0x32, // Async, continious, no whitening
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/* Frequency Synthesizer Control */
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CC1101_FSCTRL1,
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0x06, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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// Modem Configuration
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CC1101_MDMCFG0,
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0x00, // Channel spacing is 25kHz
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CC1101_MDMCFG1,
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0x00, // Channel spacing is 25kHz
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CC1101_MDMCFG2,
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0x30, // Format ASK/OOK, No preamble/sync
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CC1101_MDMCFG3,
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0x32, // Data rate is 3.79372 kBaud
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CC1101_MDMCFG4,
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0x17, // Rx BW filter is 650.000kHz
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/* Main Radio Control State Machine */
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CC1101_MCSM0,
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0x18, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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CC1101_FOCCFG,
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0x18, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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// CC1101_AGCTRL0,0x40, // 01 - Low hysteresis, small asymmetric dead zone, medium gain; 00 - 8 samples agc; 00 - Normal AGC, 00 - 4dB boundary
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// CC1101_AGCTRL1,0x00, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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// CC1101_AGCCTRL2, 0x03, // 00 - DVGA all; 000 - MAX LNA+LNA2; 011 - MAIN_TARGET 24 dB
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//MAGN_TARGET for RX filter BW =< 100 kHz is 0x3. For higher RX filter BW's MAGN_TARGET is 0x7.
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CC1101_AGCCTRL0,
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0x91, // 10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
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CC1101_AGCCTRL1,
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0x0, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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CC1101_AGCCTRL2,
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0x07, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
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/* Wake on radio and timeouts control */
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CC1101_WORCTRL,
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0xFB, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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CC1101_FREND0,
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0x11, // Adjusts current TX LO buffer + high is PATABLE[1]
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CC1101_FREND1,
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0xB6, //
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/* End load reg */
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0,
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0,
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//ook_async_patable[8]
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0x00,
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0xC0, // 12dBm 0xC0, 10dBm 0xC5, 7dBm 0xCD, 5dBm 0x86, 0dBm 0x50, -6dBm 0x37, -10dBm 0x26, -15dBm 0x1D, -20dBm 0x17, -30dBm 0x03
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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};
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const uint8_t subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs[] = {
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/* GPIO GD0 */
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CC1101_IOCFG0,
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0x0D, // GD0 as async serial data output/input
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/* Frequency Synthesizer Control */
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CC1101_FSCTRL1,
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0x06, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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/* Packet engine */
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CC1101_PKTCTRL0,
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0x32, // Async, continious, no whitening
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CC1101_PKTCTRL1,
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0x04,
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// // Modem Configuration
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CC1101_MDMCFG0,
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0x00,
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CC1101_MDMCFG1,
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0x02,
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CC1101_MDMCFG2,
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0x04, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
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CC1101_MDMCFG3,
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0x83, // Data rate is 4.79794 kBaud
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CC1101_MDMCFG4,
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0x67, //Rx BW filter is 270.833333 kHz
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CC1101_DEVIATN,
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0x04, //Deviation 2.380371 kHz
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/* Main Radio Control State Machine */
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CC1101_MCSM0,
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0x18, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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CC1101_FOCCFG,
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0x16, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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CC1101_AGCCTRL0,
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0x91, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
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CC1101_AGCCTRL1,
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0x00, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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CC1101_AGCCTRL2,
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0x07, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
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/* Wake on radio and timeouts control */
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CC1101_WORCTRL,
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0xFB, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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CC1101_FREND0,
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0x10, // Adjusts current TX LO buffer
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CC1101_FREND1,
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0x56,
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/* End load reg */
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0,
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0,
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// 2fsk_async_patable[8]
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0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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};
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const uint8_t subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs[] = {
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/* GPIO GD0 */
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CC1101_IOCFG0,
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0x0D, // GD0 as async serial data output/input
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/* Frequency Synthesizer Control */
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CC1101_FSCTRL1,
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0x06, // IF = (26*10^6) / (2^10) * 0x06 = 152343.75Hz
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/* Packet engine */
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CC1101_PKTCTRL0,
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0x32, // Async, continious, no whitening
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CC1101_PKTCTRL1,
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0x04,
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// // Modem Configuration
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CC1101_MDMCFG0,
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0x00,
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CC1101_MDMCFG1,
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0x02,
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CC1101_MDMCFG2,
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0x04, // Format 2-FSK/FM, No preamble/sync, Disable (current optimized)
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CC1101_MDMCFG3,
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0x83, // Data rate is 4.79794 kBaud
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CC1101_MDMCFG4,
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0x67, //Rx BW filter is 270.833333 kHz
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CC1101_DEVIATN,
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0x47, //Deviation 47.60742 kHz
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/* Main Radio Control State Machine */
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CC1101_MCSM0,
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0x18, // Autocalibrate on idle-to-rx/tx, PO_TIMEOUT is 64 cycles(149-155us)
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/* Frequency Offset Compensation Configuration */
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CC1101_FOCCFG,
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0x16, // no frequency offset compensation, POST_K same as PRE_K, PRE_K is 4K, GATE is off
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/* Automatic Gain Control */
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CC1101_AGCCTRL0,
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0x91, //10 - Medium hysteresis, medium asymmetric dead zone, medium gain ; 01 - 16 samples agc; 00 - Normal AGC, 01 - 8dB boundary
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CC1101_AGCCTRL1,
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0x00, // 0; 0 - LNA 2 gain is decreased to minimum before decreasing LNA gain; 00 - Relative carrier sense threshold disabled; 0000 - RSSI to MAIN_TARGET
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CC1101_AGCCTRL2,
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0x07, // 00 - DVGA all; 000 - MAX LNA+LNA2; 111 - MAIN_TARGET 42 dB
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/* Wake on radio and timeouts control */
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CC1101_WORCTRL,
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0xFB, // WOR_RES is 2^15 periods (0.91 - 0.94 s) 16.5 - 17.2 hours
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/* Frontend configuration */
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CC1101_FREND0,
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0x10, // Adjusts current TX LO buffer
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CC1101_FREND1,
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0x56,
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/* End load reg */
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0,
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0,
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// 2fsk_async_patable[8]
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0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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};
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const uint8_t subghz_device_cc1101_preset_msk_99_97kb_async_regs[] = {
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/* GPIO GD0 */
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CC1101_IOCFG0,
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0x06,
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CC1101_FIFOTHR,
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0x07, // The only important bit is ADC_RETENTION
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CC1101_SYNC1,
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0x46,
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CC1101_SYNC0,
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0x4C,
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CC1101_ADDR,
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0x00,
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CC1101_PKTLEN,
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0x00,
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CC1101_CHANNR,
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0x00,
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CC1101_PKTCTRL0,
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0x05,
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CC1101_FSCTRL0,
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0x23,
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CC1101_FSCTRL1,
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0x06,
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CC1101_MDMCFG0,
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0xF8,
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CC1101_MDMCFG1,
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0x22,
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CC1101_MDMCFG2,
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0x72,
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CC1101_MDMCFG3,
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0xF8,
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CC1101_MDMCFG4,
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0x5B,
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CC1101_DEVIATN,
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0x47,
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CC1101_MCSM0,
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0x18,
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CC1101_FOCCFG,
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0x16,
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CC1101_AGCCTRL0,
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0xB2,
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CC1101_AGCCTRL1,
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0x00,
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CC1101_AGCCTRL2,
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0xC7,
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CC1101_FREND0,
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0x10,
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CC1101_FREND1,
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0x56,
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CC1101_BSCFG,
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0x1C,
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CC1101_FSTEST,
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0x59,
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/* End load reg */
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0,
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0,
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// msk_async_patable[8]
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0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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};
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const uint8_t subghz_device_cc1101_preset_gfsk_9_99kb_async_regs[] = {
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CC1101_IOCFG0,
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0x06, //GDO0 Output Pin Configuration
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CC1101_FIFOTHR,
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0x47, //RX FIFO and TX FIFO Thresholds
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//1 : CRC calculation in TX and CRC check in RX enabled,
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//1 : Variable packet length mode. Packet length configured by the first byte after sync word
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CC1101_PKTCTRL0,
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0x05,
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CC1101_FSCTRL1,
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0x06, //Frequency Synthesizer Control
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CC1101_SYNC1,
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0x46,
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CC1101_SYNC0,
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0x4C,
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CC1101_ADDR,
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0x00,
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CC1101_PKTLEN,
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0x00,
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CC1101_MDMCFG4,
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0xC8, //Modem Configuration 9.99
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CC1101_MDMCFG3,
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0x93, //Modem Configuration
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CC1101_MDMCFG2,
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0x12, // 2: 16/16 sync word bits detected
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CC1101_DEVIATN,
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0x34, //Deviation = 19.042969
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CC1101_MCSM0,
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0x18, //Main Radio Control State Machine Configuration
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CC1101_FOCCFG,
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0x16, //Frequency Offset Compensation Configuration
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CC1101_AGCCTRL2,
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0x43, //AGC Control
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CC1101_AGCCTRL1,
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0x40,
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CC1101_AGCCTRL0,
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0x91,
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CC1101_WORCTRL,
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0xFB, //Wake On Radio Control
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/* End load reg */
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0,
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0,
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// gfsk_async_patable[8]
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0xC0, // 10dBm 0xC0, 7dBm 0xC8, 5dBm 0x84, 0dBm 0x60, -10dBm 0x34, -15dBm 0x1D, -20dBm 0x0E, -30dBm 0x12
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0x00,
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0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
#pragma once
|
||||
#pragma once
|
||||
#include <furi.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern const uint8_t subghz_device_cc1101_preset_ook_270khz_async_regs[];
|
||||
extern const uint8_t subghz_device_cc1101_preset_ook_650khz_async_regs[];
|
||||
extern const uint8_t subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs[];
|
||||
extern const uint8_t subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs[];
|
||||
extern const uint8_t subghz_device_cc1101_preset_msk_99_97kb_async_regs[];
|
||||
extern const uint8_t subghz_device_cc1101_preset_gfsk_9_99kb_async_regs[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,96 @@
|
||||
#include "cc1101_int_interconnect.h"
|
||||
#include <furi_hal.h>
|
||||
#include "../cc1101_configs.h"
|
||||
|
||||
#define TAG "SubGhzDeviceCC1101Int"
|
||||
|
||||
static bool subghz_device_cc1101_int_interconnect_is_frequency_valid(uint32_t frequency) {
|
||||
bool ret = furi_hal_subghz_is_frequency_valid(frequency);
|
||||
if(!ret) {
|
||||
furi_crash("SubGhz: Incorrect frequency.");
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static uint32_t subghz_device_cc1101_int_interconnect_set_frequency(uint32_t frequency) {
|
||||
subghz_device_cc1101_int_interconnect_is_frequency_valid(frequency);
|
||||
return furi_hal_subghz_set_frequency_and_path(frequency);
|
||||
}
|
||||
|
||||
static bool subghz_device_cc1101_int_interconnect_start_async_tx(void* callback, void* context) {
|
||||
return furi_hal_subghz_start_async_tx((FuriHalSubGhzAsyncTxCallback)callback, context);
|
||||
}
|
||||
|
||||
static void subghz_device_cc1101_int_interconnect_start_async_rx(void* callback, void* context) {
|
||||
furi_hal_subghz_start_async_rx((FuriHalSubGhzCaptureCallback)callback, context);
|
||||
}
|
||||
|
||||
static void subghz_device_cc1101_int_interconnect_load_preset(
|
||||
FuriHalSubGhzPreset preset,
|
||||
uint8_t* preset_data) {
|
||||
switch(preset) {
|
||||
case FuriHalSubGhzPresetOok650Async:
|
||||
furi_hal_subghz_load_custom_preset(subghz_device_cc1101_preset_ook_650khz_async_regs);
|
||||
break;
|
||||
case FuriHalSubGhzPresetOok270Async:
|
||||
furi_hal_subghz_load_custom_preset(subghz_device_cc1101_preset_ook_270khz_async_regs);
|
||||
break;
|
||||
case FuriHalSubGhzPreset2FSKDev238Async:
|
||||
furi_hal_subghz_load_custom_preset(subghz_device_cc1101_preset_2fsk_dev2_38khz_async_regs);
|
||||
break;
|
||||
case FuriHalSubGhzPreset2FSKDev476Async:
|
||||
furi_hal_subghz_load_custom_preset(subghz_device_cc1101_preset_2fsk_dev47_6khz_async_regs);
|
||||
break;
|
||||
case FuriHalSubGhzPresetMSK99_97KbAsync:
|
||||
furi_hal_subghz_load_custom_preset(subghz_device_cc1101_preset_msk_99_97kb_async_regs);
|
||||
break;
|
||||
case FuriHalSubGhzPresetGFSK9_99KbAsync:
|
||||
furi_hal_subghz_load_custom_preset(subghz_device_cc1101_preset_gfsk_9_99kb_async_regs);
|
||||
break;
|
||||
|
||||
default:
|
||||
furi_hal_subghz_load_custom_preset(preset_data);
|
||||
}
|
||||
}
|
||||
|
||||
static bool subghz_device_cc1101_int_interconnect_is_connect(void) {
|
||||
return true;
|
||||
}
|
||||
|
||||
const SubGhzDeviceInterconnect subghz_device_cc1101_int_interconnect = {
|
||||
.begin = NULL,
|
||||
.end = furi_hal_subghz_shutdown,
|
||||
.is_connect = subghz_device_cc1101_int_interconnect_is_connect,
|
||||
.reset = furi_hal_subghz_reset,
|
||||
.sleep = furi_hal_subghz_sleep,
|
||||
.idle = furi_hal_subghz_idle,
|
||||
.load_preset = subghz_device_cc1101_int_interconnect_load_preset,
|
||||
.set_frequency = subghz_device_cc1101_int_interconnect_set_frequency,
|
||||
.is_frequency_valid = furi_hal_subghz_is_frequency_valid,
|
||||
.set_async_mirror_pin = furi_hal_subghz_set_async_mirror_pin,
|
||||
.get_data_gpio = furi_hal_subghz_get_data_gpio,
|
||||
|
||||
.set_tx = furi_hal_subghz_tx,
|
||||
.flush_tx = furi_hal_subghz_flush_tx,
|
||||
.start_async_tx = subghz_device_cc1101_int_interconnect_start_async_tx,
|
||||
.is_async_complete_tx = furi_hal_subghz_is_async_tx_complete,
|
||||
.stop_async_tx = furi_hal_subghz_stop_async_tx,
|
||||
|
||||
.set_rx = furi_hal_subghz_rx,
|
||||
.flush_rx = furi_hal_subghz_flush_rx,
|
||||
.start_async_rx = subghz_device_cc1101_int_interconnect_start_async_rx,
|
||||
.stop_async_rx = furi_hal_subghz_stop_async_rx,
|
||||
|
||||
.get_rssi = furi_hal_subghz_get_rssi,
|
||||
.get_lqi = furi_hal_subghz_get_lqi,
|
||||
|
||||
.rx_pipe_not_empty = furi_hal_subghz_rx_pipe_not_empty,
|
||||
.is_rx_data_crc_valid = furi_hal_subghz_is_rx_data_crc_valid,
|
||||
.read_packet = furi_hal_subghz_read_packet,
|
||||
.write_packet = furi_hal_subghz_write_packet,
|
||||
};
|
||||
|
||||
const SubGhzDevice subghz_device_cc1101_int = {
|
||||
.name = SUBGHZ_DEVICE_CC1101_INT_NAME,
|
||||
.interconnect = &subghz_device_cc1101_int_interconnect,
|
||||
};
|
||||
@@ -0,0 +1,8 @@
|
||||
#pragma once
|
||||
#include "../types.h"
|
||||
|
||||
#define SUBGHZ_DEVICE_CC1101_INT_NAME "cc1101_int"
|
||||
|
||||
typedef struct SubGhzDeviceCC1101Int SubGhzDeviceCC1101Int;
|
||||
|
||||
extern const SubGhzDevice subghz_device_cc1101_int;
|
||||
@@ -0,0 +1,13 @@
|
||||
#pragma once
|
||||
|
||||
#include "registry.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern const SubGhzDeviceRegistry subghz_device_registry;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,236 @@
|
||||
#include "devices.h"
|
||||
|
||||
#include "registry.h"
|
||||
|
||||
void subghz_devices_init() {
|
||||
furi_check(!subghz_device_registry_is_valid());
|
||||
subghz_device_registry_init();
|
||||
}
|
||||
|
||||
void subghz_devices_deinit(void) {
|
||||
furi_check(subghz_device_registry_is_valid());
|
||||
subghz_device_registry_deinit();
|
||||
}
|
||||
|
||||
const SubGhzDevice* subghz_devices_get_by_name(const char* device_name) {
|
||||
furi_check(subghz_device_registry_is_valid());
|
||||
const SubGhzDevice* device = subghz_device_registry_get_by_name(device_name);
|
||||
return device;
|
||||
}
|
||||
|
||||
const char* subghz_devices_get_name(const SubGhzDevice* device) {
|
||||
const char* ret = NULL;
|
||||
if(device) {
|
||||
ret = device->name;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool subghz_devices_begin(const SubGhzDevice* device) {
|
||||
bool ret = false;
|
||||
furi_assert(device);
|
||||
if(device->interconnect->begin) {
|
||||
ret = device->interconnect->begin();
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void subghz_devices_end(const SubGhzDevice* device) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->end) {
|
||||
device->interconnect->end();
|
||||
}
|
||||
}
|
||||
|
||||
bool subghz_devices_is_connect(const SubGhzDevice* device) {
|
||||
bool ret = false;
|
||||
furi_assert(device);
|
||||
if(device->interconnect->is_connect) {
|
||||
ret = device->interconnect->is_connect();
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void subghz_devices_reset(const SubGhzDevice* device) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->reset) {
|
||||
device->interconnect->reset();
|
||||
}
|
||||
}
|
||||
|
||||
void subghz_devices_sleep(const SubGhzDevice* device) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->sleep) {
|
||||
device->interconnect->sleep();
|
||||
}
|
||||
}
|
||||
|
||||
void subghz_devices_idle(const SubGhzDevice* device) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->idle) {
|
||||
device->interconnect->idle();
|
||||
}
|
||||
}
|
||||
|
||||
void subghz_devices_load_preset(
|
||||
const SubGhzDevice* device,
|
||||
FuriHalSubGhzPreset preset,
|
||||
uint8_t* preset_data) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->load_preset) {
|
||||
device->interconnect->load_preset(preset, preset_data);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t subghz_devices_set_frequency(const SubGhzDevice* device, uint32_t frequency) {
|
||||
uint32_t ret = 0;
|
||||
furi_assert(device);
|
||||
if(device->interconnect->set_frequency) {
|
||||
ret = device->interconnect->set_frequency(frequency);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool subghz_devices_is_frequency_valid(const SubGhzDevice* device, uint32_t frequency) {
|
||||
bool ret = false;
|
||||
furi_assert(device);
|
||||
if(device->interconnect->is_frequency_valid) {
|
||||
ret = device->interconnect->is_frequency_valid(frequency);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void subghz_devices_set_async_mirror_pin(const SubGhzDevice* device, const GpioPin* gpio) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->set_async_mirror_pin) {
|
||||
device->interconnect->set_async_mirror_pin(gpio);
|
||||
}
|
||||
}
|
||||
|
||||
const GpioPin* subghz_devices_get_data_gpio(const SubGhzDevice* device) {
|
||||
const GpioPin* ret = NULL;
|
||||
furi_assert(device);
|
||||
if(device->interconnect->get_data_gpio) {
|
||||
ret = device->interconnect->get_data_gpio();
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool subghz_devices_set_tx(const SubGhzDevice* device) {
|
||||
bool ret = 0;
|
||||
furi_assert(device);
|
||||
if(device->interconnect->set_tx) {
|
||||
ret = device->interconnect->set_tx();
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void subghz_devices_flush_tx(const SubGhzDevice* device) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->flush_tx) {
|
||||
device->interconnect->flush_tx();
|
||||
}
|
||||
}
|
||||
|
||||
bool subghz_devices_start_async_tx(const SubGhzDevice* device, void* callback, void* context) {
|
||||
bool ret = false;
|
||||
furi_assert(device);
|
||||
if(device->interconnect->start_async_tx) {
|
||||
ret = device->interconnect->start_async_tx(callback, context);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool subghz_devices_is_async_complete_tx(const SubGhzDevice* device) {
|
||||
bool ret = false;
|
||||
furi_assert(device);
|
||||
if(device->interconnect->is_async_complete_tx) {
|
||||
ret = device->interconnect->is_async_complete_tx();
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void subghz_devices_stop_async_tx(const SubGhzDevice* device) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->stop_async_tx) {
|
||||
device->interconnect->stop_async_tx();
|
||||
}
|
||||
}
|
||||
|
||||
void subghz_devices_set_rx(const SubGhzDevice* device) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->set_rx) {
|
||||
device->interconnect->set_rx();
|
||||
}
|
||||
}
|
||||
|
||||
void subghz_devices_flush_rx(const SubGhzDevice* device) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->flush_rx) {
|
||||
device->interconnect->flush_rx();
|
||||
}
|
||||
}
|
||||
|
||||
void subghz_devices_start_async_rx(const SubGhzDevice* device, void* callback, void* context) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->start_async_rx) {
|
||||
device->interconnect->start_async_rx(callback, context);
|
||||
}
|
||||
}
|
||||
|
||||
void subghz_devices_stop_async_rx(const SubGhzDevice* device) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->stop_async_rx) {
|
||||
device->interconnect->stop_async_rx();
|
||||
}
|
||||
}
|
||||
|
||||
float subghz_devices_get_rssi(const SubGhzDevice* device) {
|
||||
float ret = 0;
|
||||
furi_assert(device);
|
||||
if(device->interconnect->get_rssi) {
|
||||
ret = device->interconnect->get_rssi();
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint8_t subghz_devices_get_lqi(const SubGhzDevice* device) {
|
||||
uint8_t ret = 0;
|
||||
furi_assert(device);
|
||||
if(device->interconnect->get_lqi) {
|
||||
ret = device->interconnect->get_lqi();
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool subghz_devices_rx_pipe_not_empty(const SubGhzDevice* device) {
|
||||
bool ret = false;
|
||||
furi_assert(device);
|
||||
if(device->interconnect->rx_pipe_not_empty) {
|
||||
ret = device->interconnect->rx_pipe_not_empty();
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool subghz_devices_is_rx_data_crc_valid(const SubGhzDevice* device) {
|
||||
bool ret = false;
|
||||
furi_assert(device);
|
||||
if(device->interconnect->is_rx_data_crc_valid) {
|
||||
ret = device->interconnect->is_rx_data_crc_valid();
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void subghz_devices_read_packet(const SubGhzDevice* device, uint8_t* data, uint8_t* size) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->read_packet) {
|
||||
device->interconnect->read_packet(data, size);
|
||||
}
|
||||
}
|
||||
|
||||
void subghz_devices_write_packet(const SubGhzDevice* device, const uint8_t* data, uint8_t size) {
|
||||
furi_assert(device);
|
||||
if(device->interconnect->write_packet) {
|
||||
device->interconnect->write_packet(data, size);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#pragma once
|
||||
|
||||
#include "types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct SubGhzDevice SubGhzDevice;
|
||||
|
||||
void subghz_devices_init();
|
||||
void subghz_devices_deinit(void);
|
||||
|
||||
const SubGhzDevice* subghz_devices_get_by_name(const char* device_name);
|
||||
const char* subghz_devices_get_name(const SubGhzDevice* device);
|
||||
bool subghz_devices_begin(const SubGhzDevice* device);
|
||||
void subghz_devices_end(const SubGhzDevice* device);
|
||||
bool subghz_devices_is_connect(const SubGhzDevice* device);
|
||||
void subghz_devices_reset(const SubGhzDevice* device);
|
||||
void subghz_devices_sleep(const SubGhzDevice* device);
|
||||
void subghz_devices_idle(const SubGhzDevice* device);
|
||||
void subghz_devices_load_preset(
|
||||
const SubGhzDevice* device,
|
||||
FuriHalSubGhzPreset preset,
|
||||
uint8_t* preset_data);
|
||||
uint32_t subghz_devices_set_frequency(const SubGhzDevice* device, uint32_t frequency);
|
||||
bool subghz_devices_is_frequency_valid(const SubGhzDevice* device, uint32_t frequency);
|
||||
void subghz_devices_set_async_mirror_pin(const SubGhzDevice* device, const GpioPin* gpio);
|
||||
const GpioPin* subghz_devices_get_data_gpio(const SubGhzDevice* device);
|
||||
|
||||
bool subghz_devices_set_tx(const SubGhzDevice* device);
|
||||
void subghz_devices_flush_tx(const SubGhzDevice* device);
|
||||
bool subghz_devices_start_async_tx(const SubGhzDevice* device, void* callback, void* context);
|
||||
bool subghz_devices_is_async_complete_tx(const SubGhzDevice* device);
|
||||
void subghz_devices_stop_async_tx(const SubGhzDevice* device);
|
||||
|
||||
void subghz_devices_set_rx(const SubGhzDevice* device);
|
||||
void subghz_devices_flush_rx(const SubGhzDevice* device);
|
||||
void subghz_devices_start_async_rx(const SubGhzDevice* device, void* callback, void* context);
|
||||
void subghz_devices_stop_async_rx(const SubGhzDevice* device);
|
||||
|
||||
float subghz_devices_get_rssi(const SubGhzDevice* device);
|
||||
uint8_t subghz_devices_get_lqi(const SubGhzDevice* device);
|
||||
|
||||
bool subghz_devices_rx_pipe_not_empty(const SubGhzDevice* device);
|
||||
bool subghz_devices_is_rx_data_crc_valid(const SubGhzDevice* device);
|
||||
void subghz_devices_read_packet(const SubGhzDevice* device, uint8_t* data, uint8_t* size);
|
||||
void subghz_devices_write_packet(const SubGhzDevice* device, const uint8_t* data, uint8_t size);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,13 @@
|
||||
#pragma once
|
||||
|
||||
/** Radio Presets */
|
||||
typedef enum {
|
||||
FuriHalSubGhzPresetIDLE, /**< default configuration */
|
||||
FuriHalSubGhzPresetOok270Async, /**< OOK, bandwidth 270kHz, asynchronous */
|
||||
FuriHalSubGhzPresetOok650Async, /**< OOK, bandwidth 650kHz, asynchronous */
|
||||
FuriHalSubGhzPreset2FSKDev238Async, /**< FM, deviation 2.380371 kHz, asynchronous */
|
||||
FuriHalSubGhzPreset2FSKDev476Async, /**< FM, deviation 47.60742 kHz, asynchronous */
|
||||
FuriHalSubGhzPresetMSK99_97KbAsync, /**< MSK, deviation 47.60742 kHz, 99.97Kb/s, asynchronous */
|
||||
FuriHalSubGhzPresetGFSK9_99KbAsync, /**< GFSK, deviation 19.042969 kHz, 9.996Kb/s, asynchronous */
|
||||
FuriHalSubGhzPresetCustom, /**Custom Preset*/
|
||||
} FuriHalSubGhzPreset;
|
||||
@@ -0,0 +1,76 @@
|
||||
#include "registry.h"
|
||||
|
||||
#include "cc1101_int/cc1101_int_interconnect.h"
|
||||
#include <flipper_application/plugins/plugin_manager.h>
|
||||
#include <loader/firmware_api/firmware_api.h>
|
||||
|
||||
#define TAG "SubGhzDeviceRegistry"
|
||||
|
||||
struct SubGhzDeviceRegistry {
|
||||
const SubGhzDevice** items;
|
||||
size_t size;
|
||||
PluginManager* manager;
|
||||
};
|
||||
|
||||
static SubGhzDeviceRegistry* subghz_device_registry = NULL;
|
||||
|
||||
void subghz_device_registry_init(void) {
|
||||
SubGhzDeviceRegistry* subghz_device =
|
||||
(SubGhzDeviceRegistry*)malloc(sizeof(SubGhzDeviceRegistry));
|
||||
subghz_device->manager = plugin_manager_alloc(
|
||||
SUBGHZ_RADIO_DEVICE_PLUGIN_APP_ID,
|
||||
SUBGHZ_RADIO_DEVICE_PLUGIN_API_VERSION,
|
||||
firmware_api_interface);
|
||||
|
||||
//ToDo: fix path to plugins
|
||||
if(plugin_manager_load_all(subghz_device->manager, "/any/apps_data/subghz/plugins") !=
|
||||
//if(plugin_manager_load_all(subghz_device->manager, APP_DATA_PATH("plugins")) !=
|
||||
PluginManagerErrorNone) {
|
||||
FURI_LOG_E(TAG, "Failed to load all libs");
|
||||
}
|
||||
|
||||
subghz_device->size = plugin_manager_get_count(subghz_device->manager) + 1;
|
||||
subghz_device->items =
|
||||
(const SubGhzDevice**)malloc(sizeof(SubGhzDevice*) * subghz_device->size);
|
||||
subghz_device->items[0] = &subghz_device_cc1101_int;
|
||||
for(uint32_t i = 1; i < subghz_device->size; i++) {
|
||||
const SubGhzDevice* plugin = plugin_manager_get_ep(subghz_device->manager, i - 1);
|
||||
subghz_device->items[i] = plugin;
|
||||
}
|
||||
|
||||
FURI_LOG_I(TAG, "Loaded %zu radio device", subghz_device->size);
|
||||
subghz_device_registry = subghz_device;
|
||||
}
|
||||
|
||||
void subghz_device_registry_deinit(void) {
|
||||
plugin_manager_free(subghz_device_registry->manager);
|
||||
free(subghz_device_registry->items);
|
||||
free(subghz_device_registry);
|
||||
subghz_device_registry = NULL;
|
||||
}
|
||||
|
||||
bool subghz_device_registry_is_valid(void) {
|
||||
return subghz_device_registry != NULL;
|
||||
}
|
||||
|
||||
const SubGhzDevice* subghz_device_registry_get_by_name(const char* name) {
|
||||
furi_assert(subghz_device_registry);
|
||||
|
||||
if(name != NULL) {
|
||||
for(size_t i = 0; i < subghz_device_registry->size; i++) {
|
||||
if(strcmp(name, subghz_device_registry->items[i]->name) == 0) {
|
||||
return subghz_device_registry->items[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const SubGhzDevice* subghz_device_registry_get_by_index(size_t index) {
|
||||
furi_assert(subghz_device_registry);
|
||||
if(index < subghz_device_registry->size) {
|
||||
return subghz_device_registry->items[index];
|
||||
} else {
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,40 @@
|
||||
#pragma once
|
||||
|
||||
#include "types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct SubGhzDevice SubGhzDevice;
|
||||
|
||||
void subghz_device_registry_init(void);
|
||||
|
||||
void subghz_device_registry_deinit(void);
|
||||
|
||||
bool subghz_device_registry_is_valid(void);
|
||||
|
||||
/**
|
||||
* Registration by name SubGhzDevice.
|
||||
* @param name SubGhzDevice name
|
||||
* @return SubGhzDevice* pointer to a SubGhzDevice instance
|
||||
*/
|
||||
const SubGhzDevice* subghz_device_registry_get_by_name(const char* name);
|
||||
|
||||
/**
|
||||
* Registration subghzdevice by index in array SubGhzDevice.
|
||||
* @param index SubGhzDevice by index in array
|
||||
* @return SubGhzDevice* pointer to a SubGhzDevice instance
|
||||
*/
|
||||
const SubGhzDevice* subghz_device_registry_get_by_index(size_t index);
|
||||
|
||||
/**
|
||||
* Getting the number of registered subghzdevices.
|
||||
* @param subghz_device SubGhzDeviceRegistry
|
||||
* @return Number of subghzdevices
|
||||
*/
|
||||
size_t subghz_device_registry_count(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,91 @@
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#include <furi.h>
|
||||
#include <furi_hal.h>
|
||||
|
||||
#include "preset.h"
|
||||
|
||||
#include <flipper_application/flipper_application.h>
|
||||
|
||||
#define SUBGHZ_RADIO_DEVICE_PLUGIN_APP_ID "subghz_radio_device"
|
||||
#define SUBGHZ_RADIO_DEVICE_PLUGIN_API_VERSION 1
|
||||
|
||||
typedef struct SubGhzDeviceRegistry SubGhzDeviceRegistry;
|
||||
typedef struct SubGhzDevice SubGhzDevice;
|
||||
|
||||
typedef bool (*SubGhzBegin)(void);
|
||||
typedef void (*SubGhzEnd)(void);
|
||||
typedef bool (*SubGhzIsConnect)(void);
|
||||
typedef void (*SubGhzReset)(void);
|
||||
typedef void (*SubGhzSleep)(void);
|
||||
typedef void (*SubGhzIdle)(void);
|
||||
typedef void (*SubGhzLoadPreset)(FuriHalSubGhzPreset preset, uint8_t* preset_data);
|
||||
typedef uint32_t (*SubGhzSetFrequency)(uint32_t frequency);
|
||||
typedef bool (*SubGhzIsFrequencyValid)(uint32_t frequency);
|
||||
|
||||
typedef void (*SubGhzSetAsyncMirrorPin)(const GpioPin* gpio);
|
||||
typedef const GpioPin* (*SubGhzGetDataGpio)(void);
|
||||
|
||||
typedef bool (*SubGhzSetTx)(void);
|
||||
typedef void (*SubGhzFlushTx)(void);
|
||||
typedef bool (*SubGhzStartAsyncTx)(void* callback, void* context);
|
||||
typedef bool (*SubGhzIsAsyncCompleteTx)(void);
|
||||
typedef void (*SubGhzStopAsyncTx)(void);
|
||||
|
||||
typedef void (*SubGhzSetRx)(void);
|
||||
typedef void (*SubGhzFlushRx)(void);
|
||||
typedef void (*SubGhzStartAsyncRx)(void* callback, void* context);
|
||||
typedef void (*SubGhzStopAsyncRx)(void);
|
||||
|
||||
typedef float (*SubGhzGetRSSI)(void);
|
||||
typedef uint8_t (*SubGhzGetLQI)(void);
|
||||
|
||||
typedef bool (*SubGhzRxPipeNotEmpty)(void);
|
||||
typedef bool (*SubGhzRxIsDataCrcValid)(void);
|
||||
typedef void (*SubGhzReadPacket)(uint8_t* data, uint8_t* size);
|
||||
typedef void (*SubGhzWritePacket)(const uint8_t* data, uint8_t size);
|
||||
|
||||
typedef struct {
|
||||
SubGhzBegin begin;
|
||||
SubGhzEnd end;
|
||||
|
||||
SubGhzIsConnect is_connect;
|
||||
SubGhzReset reset;
|
||||
SubGhzSleep sleep;
|
||||
SubGhzIdle idle;
|
||||
|
||||
SubGhzLoadPreset load_preset;
|
||||
SubGhzSetFrequency set_frequency;
|
||||
SubGhzIsFrequencyValid is_frequency_valid;
|
||||
SubGhzSetAsyncMirrorPin set_async_mirror_pin;
|
||||
SubGhzGetDataGpio get_data_gpio;
|
||||
|
||||
SubGhzSetTx set_tx;
|
||||
SubGhzFlushTx flush_tx;
|
||||
SubGhzStartAsyncTx start_async_tx;
|
||||
SubGhzIsAsyncCompleteTx is_async_complete_tx;
|
||||
SubGhzStopAsyncTx stop_async_tx;
|
||||
|
||||
SubGhzSetRx set_rx;
|
||||
SubGhzFlushRx flush_rx;
|
||||
SubGhzStartAsyncRx start_async_rx;
|
||||
SubGhzStopAsyncRx stop_async_rx;
|
||||
|
||||
SubGhzGetRSSI get_rssi;
|
||||
SubGhzGetLQI get_lqi;
|
||||
|
||||
SubGhzRxPipeNotEmpty rx_pipe_not_empty;
|
||||
SubGhzRxIsDataCrcValid is_rx_data_crc_valid;
|
||||
SubGhzReadPacket read_packet;
|
||||
SubGhzWritePacket write_packet;
|
||||
|
||||
} SubGhzDeviceInterconnect;
|
||||
|
||||
struct SubGhzDevice {
|
||||
const char* name;
|
||||
const SubGhzDeviceInterconnect* interconnect;
|
||||
};
|
||||
Reference in New Issue
Block a user