ApiHal: initialize clock in parallel, switch LSE driving to high, enable EXTI line 18 to fix LSECSS, move some interrupts service routines to api-hal-interrupts. (#614)
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				@ -88,7 +88,7 @@ void rtc_init() {
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        // Start LSI1 needed for CSS
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					        // Start LSI1 needed for CSS
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        LL_RCC_LSI1_Enable();
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					        LL_RCC_LSI1_Enable();
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        // Try to start LSE normal way
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					        // Try to start LSE normal way
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        LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_MEDIUMLOW);
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					        LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_HIGH);
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        LL_RCC_LSE_Enable();
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					        LL_RCC_LSE_Enable();
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        uint32_t c = 0;
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					        uint32_t c = 0;
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        while(!RTC_CLOCK_IS_READY() && c < 200) {
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					        while(!RTC_CLOCK_IS_READY() && c < 200) {
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@ -47,15 +47,7 @@
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/* USER CODE END EM */
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					/* USER CODE END EM */
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/* Exported functions prototypes ---------------------------------------------*/
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					/* Exported functions prototypes ---------------------------------------------*/
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void NMI_Handler(void);
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void HardFault_Handler(void);
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void MemManage_Handler(void);
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void BusFault_Handler(void);
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void UsageFault_Handler(void);
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void DebugMon_Handler(void);
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void SysTick_Handler(void);
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					void SysTick_Handler(void);
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void TAMP_STAMP_LSECSS_IRQHandler(void);
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void RCC_IRQHandler(void);
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void ADC1_IRQHandler(void);
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					void ADC1_IRQHandler(void);
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void USB_LP_IRQHandler(void);
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					void USB_LP_IRQHandler(void);
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void COMP_IRQHandler(void);
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					void COMP_IRQHandler(void);
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@ -16,57 +16,10 @@ extern void HW_TS_RTC_Wakeup_Handler();
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extern void HW_IPCC_Tx_Handler();
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					extern void HW_IPCC_Tx_Handler();
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extern void HW_IPCC_Rx_Handler();
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					extern void HW_IPCC_Rx_Handler();
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void NMI_Handler(void) {
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    if (LL_RCC_IsActiveFlag_HSECSS()) {
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        LL_RCC_ClearFlag_HSECSS();
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        NVIC_SystemReset();
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    }
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}
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void HardFault_Handler(void) {
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    if ((*(volatile uint32_t *)CoreDebug_BASE) & (1 << 0)) {
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        __asm("bkpt 1");
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    }
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    while (1) {}
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}
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void MemManage_Handler(void) {
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    __asm("bkpt 1");
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    while (1) {}
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}
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void BusFault_Handler(void) {
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    __asm("bkpt 1");
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    while (1) {}
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}
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void UsageFault_Handler(void) {
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    __asm("bkpt 1");
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    while (1) {}
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}
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void DebugMon_Handler(void) {
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}
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void SysTick_Handler(void) {
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					void SysTick_Handler(void) {
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    HAL_IncTick();
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					    HAL_IncTick();
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}
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					}
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void TAMP_STAMP_LSECSS_IRQHandler(void) {
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    if (LL_RCC_IsActiveFlag_LSECSS()) {
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        LL_RCC_ClearFlag_LSECSS();
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        if (!LL_RCC_LSE_IsReady()) {
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            // TODO: notify user about issue with LSE
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            LL_RCC_ForceBackupDomainReset();
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            LL_RCC_ReleaseBackupDomainReset();
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            NVIC_SystemReset();
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        }
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    }
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}
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void RCC_IRQHandler(void) {
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}
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void ADC1_IRQHandler(void) {
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					void ADC1_IRQHandler(void) {
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    HAL_ADC_IRQHandler(&hadc1);
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					    HAL_ADC_IRQHandler(&hadc1);
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}
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					}
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@ -5,26 +5,29 @@
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#include <stm32wbxx_ll_rcc.h>
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					#include <stm32wbxx_ll_rcc.h>
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#include <stm32wbxx_ll_utils.h>
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					#include <stm32wbxx_ll_utils.h>
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					#define HS_CLOCK_IS_READY() (LL_RCC_HSE_IsReady() && LL_RCC_HSI_IsReady())
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					#define LS_CLOCK_IS_READY() (LL_RCC_LSE_IsReady() && LL_RCC_LSI1_IsReady())
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void api_hal_clock_init() {
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					void api_hal_clock_init() {
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					    /* Prepare Flash memory for 64mHz system clock */
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    LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
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					    LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
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    while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_3);
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					    while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_3);
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    /* HSE configuration and activation */
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					    /* HSE and HSI configuration and activation */
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    LL_RCC_HSE_SetCapacitorTuning(0x26);
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					    LL_RCC_HSE_SetCapacitorTuning(0x26);
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    LL_RCC_HSE_Enable();
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					    LL_RCC_HSE_Enable();
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    while(LL_RCC_HSE_IsReady() != 1) ;
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    /* HSI configuration and activation */
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    LL_RCC_HSI_Enable();
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					    LL_RCC_HSI_Enable();
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    while(LL_RCC_HSI_IsReady() != 1) 
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					    while(!HS_CLOCK_IS_READY());
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    /* LSE configuration and activation */
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    LL_PWR_EnableBkUpAccess();
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    LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_MEDIUMLOW);
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    LL_RCC_LSE_Enable();
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    while(LL_RCC_LSE_IsReady() != 1) ;
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    LL_RCC_HSE_EnableCSS();
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					    LL_RCC_HSE_EnableCSS();
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					    /* LSE and LSI1 configuration and activation */
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					    LL_PWR_EnableBkUpAccess();
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					    LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_HIGH);
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					    LL_RCC_LSE_Enable();
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					    LL_RCC_LSI1_Enable();
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					    while(!LS_CLOCK_IS_READY());
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					    LL_EXTI_EnableIT_0_31(LL_EXTI_LINE_18); /* Why? Because that's why. See RM0434, Table 61. CPU1 vector table. */
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					    LL_EXTI_EnableRisingTrig_0_31(LL_EXTI_LINE_18);
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    LL_RCC_EnableIT_LSECSS();
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					    LL_RCC_EnableIT_LSECSS();
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    LL_RCC_LSE_EnableCSS();
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					    LL_RCC_LSE_EnableCSS();
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@ -68,8 +71,7 @@ void api_hal_clock_init() {
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    LL_SetSystemCoreClock(64000000);
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					    LL_SetSystemCoreClock(64000000);
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    /* Update the time base */
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					    /* Update the time base */
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    if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
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					    if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK) {
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    {
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        Error_Handler();
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					        Error_Handler();
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    }
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					    }
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@ -104,6 +106,7 @@ void api_hal_clock_init() {
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    LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH);
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					    LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH);
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    // APB1
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					    // APB1
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					    LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB);
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    LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
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					    LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
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    // APB2
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					    // APB2
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@ -12,8 +12,15 @@ volatile ApiHalInterruptISR api_hal_tim_tim2_isr = NULL;
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volatile ApiHalInterruptISR api_hal_dma_channel_isr[API_HAL_INTERRUPT_DMA_COUNT][API_HAL_INTERRUPT_DMA_CHANNELS_COUNT] = {0};
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					volatile ApiHalInterruptISR api_hal_dma_channel_isr[API_HAL_INTERRUPT_DMA_COUNT][API_HAL_INTERRUPT_DMA_CHANNELS_COUNT] = {0};
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void api_hal_interrupt_init() {
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					void api_hal_interrupt_init() {
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					    NVIC_SetPriority(RCC_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
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					    NVIC_EnableIRQ(RCC_IRQn);
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					    NVIC_SetPriority(TAMP_STAMP_LSECSS_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
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					    NVIC_EnableIRQ(TAMP_STAMP_LSECSS_IRQn);
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    NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
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					    NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
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    NVIC_EnableIRQ(DMA1_Channel1_IRQn);
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					    NVIC_EnableIRQ(DMA1_Channel1_IRQn);
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    FURI_LOG_I("FuriHalInterrupt", "Init OK");
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					    FURI_LOG_I("FuriHalInterrupt", "Init OK");
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}
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					}
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@ -131,3 +138,54 @@ void DMA2_Channel7_IRQHandler(void) {
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void DMA2_Channel8_IRQHandler(void) {
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					void DMA2_Channel8_IRQHandler(void) {
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    if (api_hal_dma_channel_isr[1][7]) api_hal_dma_channel_isr[1][7]();
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					    if (api_hal_dma_channel_isr[1][7]) api_hal_dma_channel_isr[1][7]();
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}
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					}
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					void TAMP_STAMP_LSECSS_IRQHandler(void) {
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					    if (LL_RCC_IsActiveFlag_LSECSS()) {
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					        LL_RCC_ClearFlag_LSECSS();
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					        if (!LL_RCC_LSE_IsReady()) {
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					            FURI_LOG_E("FuriHalInterrupt", "LSE CSS fired: resetting system");
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					            NVIC_SystemReset();
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					        } else {
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					            FURI_LOG_E("FuriHalInterrupt", "LSE CSS fired: but LSE is alive");
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					        }
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					    }
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					}
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					void RCC_IRQHandler(void) {
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					}
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					void NMI_Handler(void) {
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					    if (LL_RCC_IsActiveFlag_HSECSS()) {
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					        LL_RCC_ClearFlag_HSECSS();
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					        FURI_LOG_E("FuriHalInterrupt", "HSE CSS fired: resetting system");
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					        NVIC_SystemReset();
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					    }
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					}
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					void HardFault_Handler(void) {
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					    if ((*(volatile uint32_t *)CoreDebug_BASE) & (1 << 0)) {
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					        __asm("bkpt 1");
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					    }
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					    while (1) {}
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					}
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					void MemManage_Handler(void) {
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					    __asm("bkpt 1");
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					    while (1) {}
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					}
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					void BusFault_Handler(void) {
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					    __asm("bkpt 1");
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					    while (1) {}
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					}
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					void UsageFault_Handler(void) {
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					    __asm("bkpt 1");
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					    while (1) {}
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					}
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					void DebugMon_Handler(void) {
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					}
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