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Github: fix non zero return behavior in docker actions. Firmware: fix F6 build. (#886)

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* Github: treat non 0 exit code as fatal
* GitHub: inject missing -e flag to bash in docker
* Firmware: sync targets
This commit is contained in:
あく 2021-12-09 07:58:07 +03:00 committed by GitHub
parent 9f28338d9e
commit f5b2ed67d5
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 13 additions and 14 deletions
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2
.github/workflows/build.yml vendored
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@ -82,6 +82,7 @@ jobs:
uses: ./.github/actions/docker uses: ./.github/actions/docker
with: with:
run: | run: |
set -e
for TARGET in ${TARGETS} for TARGET in ${TARGETS}
do do
make TARGET=${TARGET} make TARGET=${TARGET}
@ -92,6 +93,7 @@ jobs:
uses: ./.github/actions/docker uses: ./.github/actions/docker
with: with:
run: | run: |
set -e
for TARGET in ${TARGETS} for TARGET in ${TARGETS}
do do
mv dist/${TARGET}/* artifacts/ mv dist/${TARGET}/* artifacts/

1
firmware/targets/f6/ble-glue/serial_service.h
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@ -4,6 +4,7 @@
#include <stdbool.h> #include <stdbool.h>
#define SERIAL_SVC_DATA_LEN_MAX (486) #define SERIAL_SVC_DATA_LEN_MAX (486)
#define SERIAL_SVC_CHAR_VALUE_LEN_MAX (243)
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {

18
firmware/targets/f6/furi-hal/furi-hal-subghz.c
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@ -298,7 +298,7 @@ static const uint8_t furi_hal_subghz_preset_gfsk_9_99kb_async_regs[][2] = {
//1 : CRC calculation in TX and CRC check in RX enabled, //1 : CRC calculation in TX and CRC check in RX enabled,
//1 : Variable packet length mode. Packet length configured by the first byte after sync word //1 : Variable packet length mode. Packet length configured by the first byte after sync word
{CC1101_PKTCTRL0, 0x05}, {CC1101_PKTCTRL0,0x05},
{CC1101_FSCTRL1, 0x06}, //Frequency Synthesizer Control {CC1101_FSCTRL1, 0x06}, //Frequency Synthesizer Control
@ -315,7 +315,7 @@ static const uint8_t furi_hal_subghz_preset_gfsk_9_99kb_async_regs[][2] = {
{CC1101_MCSM0, 0x18}, //Main Radio Control State Machine Configuration {CC1101_MCSM0, 0x18}, //Main Radio Control State Machine Configuration
{CC1101_FOCCFG, 0x16}, //Frequency Offset Compensation Configuration {CC1101_FOCCFG, 0x16}, //Frequency Offset Compensation Configuration
{CC1101_AGCCTRL2, 0x43}, //AGC Control {CC1101_AGCCTRL2, 0x43 }, //AGC Control
{CC1101_AGCCTRL1, 0x40}, {CC1101_AGCCTRL1, 0x40},
{CC1101_AGCCTRL0, 0x91}, {CC1101_AGCCTRL0, 0x91},
@ -392,8 +392,7 @@ void furi_hal_subghz_init() {
; ;
// GD0 high // GD0 high
cc1101_write_reg( cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG0, CC1101IocfgHW | CC1101_IOCFG_INV);
&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG0, CC1101IocfgHW | CC1101_IOCFG_INV);
while(hal_gpio_read(&gpio_cc1101_g0) != true) while(hal_gpio_read(&gpio_cc1101_g0) != true)
; ;
@ -454,7 +453,7 @@ void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset) {
} else if(preset == FuriHalSubGhzPresetGFSK9_99KbAsync) { } else if(preset == FuriHalSubGhzPresetGFSK9_99KbAsync) {
furi_hal_subghz_load_registers(furi_hal_subghz_preset_gfsk_9_99kb_async_regs); furi_hal_subghz_load_registers(furi_hal_subghz_preset_gfsk_9_99kb_async_regs);
furi_hal_subghz_load_patable(furi_hal_subghz_preset_gfsk_async_patable); furi_hal_subghz_load_patable(furi_hal_subghz_preset_gfsk_async_patable);
} else { } else{
furi_crash(NULL); furi_crash(NULL);
} }
} }
@ -499,8 +498,7 @@ void furi_hal_subghz_flush_tx() {
bool furi_hal_subghz_rx_pipe_not_empty() { bool furi_hal_subghz_rx_pipe_not_empty() {
CC1101RxBytes status[1]; CC1101RxBytes status[1];
furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz); furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
cc1101_read_reg( cc1101_read_reg(&furi_hal_spi_bus_handle_subghz, (CC1101_STATUS_RXBYTES) | CC1101_BURST, (uint8_t*)status);
&furi_hal_spi_bus_handle_subghz, (CC1101_STATUS_RXBYTES) | CC1101_BURST, (uint8_t*)status);
furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz); furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
// TODO: you can add a buffer overflow flag if needed // TODO: you can add a buffer overflow flag if needed
if(status->NUM_RXBYTES > 0) { if(status->NUM_RXBYTES > 0) {
@ -674,15 +672,13 @@ void furi_hal_subghz_set_path(FuriHalSubGhzPath path) {
furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz); furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
if(path == FuriHalSubGhzPath433) { if(path == FuriHalSubGhzPath433) {
hal_gpio_write(&gpio_rf_sw_0, 0); hal_gpio_write(&gpio_rf_sw_0, 0);
cc1101_write_reg( cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
} else if(path == FuriHalSubGhzPath315) { } else if(path == FuriHalSubGhzPath315) {
hal_gpio_write(&gpio_rf_sw_0, 1); hal_gpio_write(&gpio_rf_sw_0, 1);
cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW); cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW);
} else if(path == FuriHalSubGhzPath868) { } else if(path == FuriHalSubGhzPath868) {
hal_gpio_write(&gpio_rf_sw_0, 1); hal_gpio_write(&gpio_rf_sw_0, 1);
cc1101_write_reg( cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
} else if(path == FuriHalSubGhzPathIsolate) { } else if(path == FuriHalSubGhzPathIsolate) {
hal_gpio_write(&gpio_rf_sw_0, 0); hal_gpio_write(&gpio_rf_sw_0, 0);
cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW); cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW);