STM32WB55_CM41.9STM32WB55_CM4CM4r0p1littletruetrue4false8320x200x00xFFFFFFFFDMA1Direct memory access controllerDMA0x400200000x00x400registersDMA1_Channel1DMA1 Channel1 global interrupt11DMA1_Channel2DMA1 Channel2 global interrupt12DMA1_Channel3DMA1 Channel3 interrupt13DMA1_Channel4DMA1 Channel4 interrupt14DMA1_Channel5DMA1 Channel5 interrupt15DMA1_Channel6DMA1 Channel6 interrupt16DMA1_Channel7DMA1 Channel 7 interrupt17ISRISRinterrupt status register0x00x20read-only0x00000000TEIF7Channel x transfer error flag (x = 1 ..7)271HTIF7Channel x half transfer flag (x = 1 ..7)261TCIF7Channel x transfer complete flag (x = 1 ..7)251GIF7Channel x global interrupt flag (x = 1 ..7)241TEIF6Channel x transfer error flag (x = 1 ..7)231HTIF6Channel x half transfer flag (x = 1 ..7)221TCIF6Channel x transfer complete flag (x = 1 ..7)211GIF6Channel x global interrupt flag (x = 1 ..7)201TEIF5Channel x transfer error flag (x = 1 ..7)191HTIF5Channel x half transfer flag (x = 1 ..7)181TCIF5Channel x transfer complete flag (x = 1 ..7)171GIF5Channel x global interrupt flag (x = 1 ..7)161TEIF4Channel x transfer error flag (x = 1 ..7)151HTIF4Channel x half transfer flag (x = 1 ..7)141TCIF4Channel x transfer complete flag (x = 1 ..7)131GIF4Channel x global interrupt flag (x = 1 ..7)121TEIF3Channel x transfer error flag (x = 1 ..7)111HTIF3Channel x half transfer flag (x = 1 ..7)101TCIF3Channel x transfer complete flag (x = 1 ..7)91GIF3Channel x global interrupt flag (x = 1 ..7)81TEIF2Channel x transfer error flag (x = 1 ..7)71HTIF2Channel x half transfer flag (x = 1 ..7)61TCIF2Channel x transfer complete flag (x = 1 ..7)51GIF2Channel x global interrupt flag (x = 1 ..7)41TEIF1Channel x transfer error flag (x = 1 ..7)31HTIF1Channel x half transfer flag (x = 1 ..7)21TCIF1Channel x transfer complete flag (x = 1 ..7)11GIF1Channel x global interrupt flag (x = 1 ..7)01IFCRIFCRinterrupt flag clear register0x40x20write-only0x00000000CTEIF7Channel x transfer error clear (x = 1 ..7)271CHTIF7Channel x half transfer clear (x = 1 ..7)261CTCIF7Channel x transfer complete clear (x = 1 ..7)251CGIF7Channel x global interrupt clear (x = 1 ..7)241CTEIF6Channel x transfer error clear (x = 1 ..7)231CHTIF6Channel x half transfer clear (x = 1 ..7)221CTCIF6Channel x transfer complete clear (x = 1 ..7)211CGIF6Channel x global interrupt clear (x = 1 ..7)201CTEIF5Channel x transfer error clear (x = 1 ..7)191CHTIF5Channel x half transfer clear (x = 1 ..7)181CTCIF5Channel x transfer complete clear (x = 1 ..7)171CGIF5Channel x global interrupt clear (x = 1 ..7)161CTEIF4Channel x transfer error clear (x = 1 ..7)151CHTIF4Channel x half transfer clear (x = 1 ..7)141CTCIF4Channel x transfer complete clear (x = 1 ..7)131CGIF4Channel x global interrupt clear (x = 1 ..7)121CTEIF3Channel x transfer error clear (x = 1 ..7)111CHTIF3Channel x half transfer clear (x = 1 ..7)101CTCIF3Channel x transfer complete clear (x = 1 ..7)91CGIF3Channel x global interrupt clear (x = 1 ..7)81CTEIF2Channel x transfer error clear (x = 1 ..7)71CHTIF2Channel x half transfer clear (x = 1 ..7)61CTCIF2Channel x transfer complete clear (x = 1 ..7)51CGIF2Channel x global interrupt clear (x = 1 ..7)41CTEIF1Channel x transfer error clear (x = 1 ..7)31CHTIF1Channel x half transfer clear (x = 1 ..7)21CTCIF1Channel x transfer complete clear (x = 1 ..7)11CGIF1Channel x global interrupt clear (x = 1 ..7)01CCR1CCR1channel x configuration register0x80x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR1CNDTR1channel x number of data register0xC0x20read-write0x00000000NDTNumber of data to transfer016CPAR1CPAR1channel x peripheral address register0x100x20read-write0x00000000PAPeripheral address032CMAR1CMAR1channel x memory address register0x140x20read-write0x00000000MAMemory address032CCR2CCR2channel x configuration register0x1C0x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR2CNDTR2channel x number of data register0x200x20read-write0x00000000NDTNumber of data to transfer016CPAR2CPAR2channel x peripheral address register0x240x20read-write0x00000000PAPeripheral address032CMAR2CMAR2channel x memory address register0x280x20read-write0x00000000MAMemory address032CCR3CCR3channel x configuration register0x300x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR3CNDTR3channel x number of data register0x340x20read-write0x00000000NDTNumber of data to transfer016CPAR3CPAR3channel x peripheral address register0x380x20read-write0x00000000PAPeripheral address032CMAR3CMAR3channel x memory address register0x3C0x20read-write0x00000000MAMemory address032CCR4CCR4channel x configuration register0x440x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR4CNDTR4channel x number of data register0x480x20read-write0x00000000NDTNumber of data to transfer016CPAR4CPAR4channel x peripheral address register0x4C0x20read-write0x00000000PAPeripheral address032CMAR4CMAR4channel x memory address register0x500x20read-write0x00000000MAMemory address032CCR5CCR5channel x configuration register0x580x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR5CNDTR5channel x number of data register0x5C0x20read-write0x00000000NDTNumber of data to transfer016CPAR5CPAR5channel x peripheral address register0x600x20read-write0x00000000PAPeripheral address032CMAR5CMAR5channel x memory address register0x640x20read-write0x00000000MAMemory address032CCR6CCR6channel x configuration register0x6C0x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR6CNDTR6channel x number of data register0x700x20read-write0x00000000NDTNumber of data to transfer016CPAR6CPAR6channel x peripheral address register0x740x20read-write0x00000000PAPeripheral address032CMAR6CMAR6channel x memory address register0x780x20read-write0x00000000MAMemory address032CCR7CCR7channel x configuration register0x800x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR7CNDTR7channel x number of data register0x840x20read-write0x00000000NDTNumber of data to transfer016CPAR7CPAR7channel x peripheral address register0x880x20read-write0x00000000PAPeripheral address032CMAR7CMAR7channel x memory address register0x8C0x20read-write0x00000000MAMemory address032DMA2Direct memory access controllerDMA0x400204000x00x400registersDMA2_CH1DMA2 channel 1 interrupt55DMA2_CH2DMA2 channel 2 interrupt56DMA2_CH3DMA2 channel 3 interrupt57DMA2_CH4DMA2 channel 4 interrupt58DMA2_CH5DMA2 channel 5 interrupt59DMA2_CH6DMA2 channel 6 interrupt60DMA2_CH7DMA2 channel 7 interrupt61ISRISRinterrupt status register0x00x20read-only0x00000000TEIF7Channel x transfer error flag (x = 1 ..7)271HTIF7Channel x half transfer flag (x = 1 ..7)261TCIF7Channel x transfer complete flag (x = 1 ..7)251GIF7Channel x global interrupt flag (x = 1 ..7)241TEIF6Channel x transfer error flag (x = 1 ..7)231HTIF6Channel x half transfer flag (x = 1 ..7)221TCIF6Channel x transfer complete flag (x = 1 ..7)211GIF6Channel x global interrupt flag (x = 1 ..7)201TEIF5Channel x transfer error flag (x = 1 ..7)191HTIF5Channel x half transfer flag (x = 1 ..7)181TCIF5Channel x transfer complete flag (x = 1 ..7)171GIF5Channel x global interrupt flag (x = 1 ..7)161TEIF4Channel x transfer error flag (x = 1 ..7)151HTIF4Channel x half transfer flag (x = 1 ..7)141TCIF4Channel x transfer complete flag (x = 1 ..7)131GIF4Channel x global interrupt flag (x = 1 ..7)121TEIF3Channel x transfer error flag (x = 1 ..7)111HTIF3Channel x half transfer flag (x = 1 ..7)101TCIF3Channel x transfer complete flag (x = 1 ..7)91GIF3Channel x global interrupt flag (x = 1 ..7)81TEIF2Channel x transfer error flag (x = 1 ..7)71HTIF2Channel x half transfer flag (x = 1 ..7)61TCIF2Channel x transfer complete flag (x = 1 ..7)51GIF2Channel x global interrupt flag (x = 1 ..7)41TEIF1Channel x transfer error flag (x = 1 ..7)31HTIF1Channel x half transfer flag (x = 1 ..7)21TCIF1Channel x transfer complete flag (x = 1 ..7)11GIF1Channel x global interrupt flag (x = 1 ..7)01IFCRIFCRinterrupt flag clear register0x40x20write-only0x00000000CTEIF7Channel x transfer error clear (x = 1 ..7)271CHTIF7Channel x half transfer clear (x = 1 ..7)261CTCIF7Channel x transfer complete clear (x = 1 ..7)251CGIF7Channel x global interrupt clear (x = 1 ..7)241CTEIF6Channel x transfer error clear (x = 1 ..7)231CHTIF6Channel x half transfer clear (x = 1 ..7)221CTCIF6Channel x transfer complete clear (x = 1 ..7)211CGIF6Channel x global interrupt clear (x = 1 ..7)201CTEIF5Channel x transfer error clear (x = 1 ..7)191CHTIF5Channel x half transfer clear (x = 1 ..7)181CTCIF5Channel x transfer complete clear (x = 1 ..7)171CGIF5Channel x global interrupt clear (x = 1 ..7)161CTEIF4Channel x transfer error clear (x = 1 ..7)151CHTIF4Channel x half transfer clear (x = 1 ..7)141CTCIF4Channel x transfer complete clear (x = 1 ..7)131CGIF4Channel x global interrupt clear (x = 1 ..7)121CTEIF3Channel x transfer error clear (x = 1 ..7)111CHTIF3Channel x half transfer clear (x = 1 ..7)101CTCIF3Channel x transfer complete clear (x = 1 ..7)91CGIF3Channel x global interrupt clear (x = 1 ..7)81CTEIF2Channel x transfer error clear (x = 1 ..7)71CHTIF2Channel x half transfer clear (x = 1 ..7)61CTCIF2Channel x transfer complete clear (x = 1 ..7)51CGIF2Channel x global interrupt clear (x = 1 ..7)41CTEIF1Channel x transfer error clear (x = 1 ..7)31CHTIF1Channel x half transfer clear (x = 1 ..7)21CTCIF1Channel x transfer complete clear (x = 1 ..7)11CGIF1Channel x global interrupt clear (x = 1 ..7)01CCR1CCR1channel x configuration register0x80x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR1CNDTR1channel x number of data register0xC0x20read-write0x00000000NDTNumber of data to transfer016CPAR1CPAR1channel x peripheral address register0x100x20read-write0x00000000PAPeripheral address032CMAR1CMAR1channel x memory address register0x140x20read-write0x00000000MAMemory address032CCR2CCR2channel x configuration register0x1C0x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR2CNDTR2channel x number of data register0x200x20read-write0x00000000NDTNumber of data to transfer016CPAR2CPAR2channel x peripheral address register0x240x20read-write0x00000000PAPeripheral address032CMAR2CMAR2channel x memory address register0x280x20read-write0x00000000MAMemory address032CCR3CCR3channel x configuration register0x300x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR3CNDTR3channel x number of data register0x340x20read-write0x00000000NDTNumber of data to transfer016CPAR3CPAR3channel x peripheral address register0x380x20read-write0x00000000PAPeripheral address032CMAR3CMAR3channel x memory address register0x3C0x20read-write0x00000000MAMemory address032CCR4CCR4channel x configuration register0x440x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR4CNDTR4channel x number of data register0x480x20read-write0x00000000NDTNumber of data to transfer016CPAR4CPAR4channel x peripheral address register0x4C0x20read-write0x00000000PAPeripheral address032CMAR4CMAR4channel x memory address register0x500x20read-write0x00000000MAMemory address032CCR5CCR5channel x configuration register0x580x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR5CNDTR5channel x number of data register0x5C0x20read-write0x00000000NDTNumber of data to transfer016CPAR5CPAR5channel x peripheral address register0x600x20read-write0x00000000PAPeripheral address032CMAR5CMAR5channel x memory address register0x640x20read-write0x00000000MAMemory address032CCR6CCR6channel x configuration register0x6C0x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR6CNDTR6channel x number of data register0x700x20read-write0x00000000NDTNumber of data to transfer016CPAR6CPAR6channel x peripheral address register0x740x20read-write0x00000000PAPeripheral address032CMAR6CMAR6channel x memory address register0x780x20read-write0x00000000MAMemory address032CCR7CCR7channel x configuration register0x800x20read-write0x00000000MEM2MEMMemory to memory mode141PLChannel priority level122MSIZEMemory size102PSIZEPeripheral size82MINCMemory increment mode71PINCPeripheral increment mode61CIRCCircular mode51DIRData transfer direction41TEIETransfer error interrupt enable31HTIEHalf transfer interrupt enable21TCIETransfer complete interrupt enable11ENChannel enable01CNDTR7CNDTR7channel x number of data register0x840x20read-write0x00000000NDTNumber of data to transfer016CPAR7CPAR7channel x peripheral address register0x880x20read-write0x00000000PAPeripheral address032CMAR7CMAR7channel x memory address register0x8C0x20read-write0x00000000MAMemory address032CSELRCSELRchannel selection register0xA80x20read-write0x00000000C7SDMA channel 7 selection244C6SDMA channel 6 selection204C5SDMA channel 5 selection164C4SDMA channel 4 selection124C3SDMA channel 3 selection84C2SDMA channel 2 selection44C1SDMA channel 1 selection04DMAMUX1Direct memory access MultiplexerDMAMUX0x400208000x00x400registersDMAMUX_OVRDMAMUX overrun interrupt62C0CRC0CRDMA Multiplexer Channel 0 Control register0x00x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08C1CRC1CRDMA Multiplexer Channel 1 Control register0x40x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08C2CRC2CRDMA Multiplexer Channel 2 Control register0x80x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08C3CRC3CRDMA Multiplexer Channel 3 Control register0xC0x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08C4CRC4CRDMA Multiplexer Channel 4 Control register0x100x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08C5CRC5CRDMA Multiplexer Channel 5 Control register0x140x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08C6CRC6CRDMA Multiplexer Channel 6 Control register0x180x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08C7CRC7CRDMA Multiplexer Channel 7 Control register0x1C0x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08C8CRC8CRDMA Multiplexer Channel 8 Control register0x200x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08C9CRC9CRDMA Multiplexer Channel 9 Control register0x240x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08C10CRC10CRDMA Multiplexer Channel 10 Control register0x280x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08C11CRC11CRDMA Multiplexer Channel 11 Control register0x2C0x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08C12CRC12CRDMA Multiplexer Channel 12 Control register0x300x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08C13CRC13CRDMA Multiplexer Channel 13 Control register0x340x20read-write0x00000000SYNC_IDSYNC_ID245NBREQNb request195SPOLSync polarity172SESynchronization enable161EGEEvent Generation Enable91SOIESynchronization Overrun Interrupt Enable81DMAREQ_IDDMA Request ID08CSRCSRDMA Multiplexer Channel Status register0x800x20read-only0x00000000SOF0Synchronization Overrun Flag 001SOF1Synchronization Overrun Flag 111SOF2Synchronization Overrun Flag 221SOF3Synchronization Overrun Flag 331SOF4Synchronization Overrun Flag 441SOF5Synchronization Overrun Flag 551SOF6Synchronization Overrun Flag 661SOF7Synchronization Overrun Flag 771SOF8Synchronization Overrun Flag 881SOF9Synchronization Overrun Flag 991SOF10Synchronization Overrun Flag 10101SOF11Synchronization Overrun Flag 11111SOF12Synchronization Overrun Flag 12121SOF13Synchronization Overrun Flag 13131CFRCFRDMA Channel Clear Flag Register0x840x20write-only0x00000000CSOF0Synchronization Clear Overrun Flag 001CSOF1Synchronization Clear Overrun Flag 111CSOF2Synchronization Clear Overrun Flag 221CSOF3Synchronization Clear Overrun Flag 331CSOF4Synchronization Clear Overrun Flag 441CSOF5Synchronization Clear Overrun Flag 551CSOF6Synchronization Clear Overrun Flag 661CSOF7Synchronization Clear Overrun Flag 771CSOF8Synchronization Clear Overrun Flag 881CSOF9Synchronization Clear Overrun Flag 991CSOF10Synchronization Clear Overrun Flag 10101CSOF11Synchronization Clear Overrun Flag 11111CSOF12Synchronization Clear Overrun Flag 12121CSOF13Synchronization Clear Overrun Flag 13131RG0CRRG0CRDMA Request Generator 0 Control Register0x1000x20read-write0x00000000GNBREQNumber of Request195GPOLGeneration Polarity172GEGeneration Enable161OIEOverrun Interrupt Enable81SIG_IDSignal ID05RG1CRRG1CRDMA Request Generator 1 Control Register0x1040x20read-write0x00000000GNBREQNumber of Request195GPOLGeneration Polarity172GEGeneration Enable161OIEOverrun Interrupt Enable81SIG_IDSignal ID05RG2CRRG2CRDMA Request Generator 2 Control Register0x1080x20read-write0x00000000GNBREQNumber of Request195GPOLGeneration Polarity172GEGeneration Enable161OIEOverrun Interrupt Enable81SIG_IDSignal ID05RG3CRRG3CRDMA Request Generator 3 Control Register0x10C0x20read-write0x00000000GNBREQNumber of Request195GPOLGeneration Polarity172GEGeneration Enable161OIEOverrun Interrupt Enable81SIG_IDSignal ID05RGSRRGSRDMA Request Generator Status Register0x1400x20read-only0x00000000OF0Generator Overrun Flag 001OF1Generator Overrun Flag 111OF2Generator Overrun Flag 221OF3Generator Overrun Flag 331RGCFRRGCFRDMA Request Generator Clear Flag Register0x1440x20write-only0x00000000COF0Clear trigger Overrun Flag 001COF1Clear trigger Overrun Flag 111COF2Clear trigger Overrun Flag 221COF3Clear trigger Overrun Flag 331CRCCyclic redundancy check calculation unitCRC0x400230000x00x400registersDRDRData register0x00x20read-write0xFFFFFFFFDRData register bits032IDRIDRIndependent data register0x40x20read-write0x00000000IDRGeneral-purpose 32-bit data register bits032CRCRControl register0x80x20read-write0x00000000REV_OUTReverse output data71REV_INReverse input data52POLYSIZEPolynomial size32RESETRESET bit01INITINITInitial CRC value0x100x20read-write0xFFFFFFFFCRC_INITProgrammable initial CRC value032POLPOLpolynomial0x140x20read-write0x04C11DB7POLProgrammable polynomial032LCDLiquid crystal display controllerLCD0x400024000x00x400registersLCDLCD global interrupt49CRCRcontrol register0x00x20read-write0x00000000BIASBias selector52DUTYDuty selection23VSELVoltage source selection11LCDENLCD controller enable01MUX_SEGMux segment enable71BUFENVoltage output buffer enable81FCRFCRframe control register0x40x20read-write0x00000000PSPS 16-bit prescaler224DIVDIV clock divider184BLINKBlink mode selection162BLINKFBlink frequency selection133CCContrast control103DEADDead time duration73PONPulse ON duration43UDDIEUpdate display done interrupt enable31SOFIEStart of frame interrupt enable11HDHigh drive enable01SRSRstatus register0x80x200x00000020FCRSFLCD Frame Control Register Synchronization flag51read-onlyRDYReady flag41read-onlyUDDUpdate Display Done31read-onlyUDRUpdate display request21read-writeSOFStart of frame flag11read-onlyENSENS01read-onlyCLRCLRclear register0xC0x20write-only0x00000000UDDCUpdate display done clear31SOFCStart of frame flag clear11RAM_COM0RAM_COM0display memory0x140x20read-write0x00000000S31S31311S30S30301S29S29291S28S28281S27S27271S26S26261S25S25251S24S24241S23S23231S22S22221S21S21211S20S20201S19S19191S18S18181S17S17171S16S16161S15S15151S14S14141S13S13131S12S12121S11S11111S10S10101S09S0991S08S0881S07S0771S06S0661S05S0551S04S0441S03S0331S02S0221S01S0111S00S0001RAM_COM1RAM_COM1display memory0x1C0x20read-write0x00000000S31S31311S30S30301S29S29291S28S28281S27S27271S26S26261S25S25251S24S24241S23S23231S22S22221S21S21211S20S20201S19S19191S18S18181S17S17171S16S16161S15S15151S14S14141S13S13131S12S12121S11S11111S10S10101S09S0991S08S0881S07S0771S06S0661S05S0551S04S0441S03S0331S02S0221S01S0111S00S0001RAM_COM2RAM_COM2display memory0x240x20read-write0x00000000S31S31311S30S30301S29S29291S28S28281S27S27271S26S26261S25S25251S24S24241S23S23231S22S22221S21S21211S20S20201S19S19191S18S18181S17S17171S16S16161S15S15151S14S14141S13S13131S12S12121S11S11111S10S10101S09S0991S08S0881S07S0771S06S0661S05S0551S04S0441S03S0331S02S0221S01S0111S00S0001RAM_COM3RAM_COM3display memory0x2C0x20read-write0x00000000S31S31311S30S30301S29S29291S28S28281S27S27271S26S26261S25S25251S24S24241S23S23231S22S22221S21S21211S20S20201S19S19191S18S18181S17S17171S16S16161S15S15151S14S14141S13S13131S12S12121S11S11111S10S10101S09S0991S08S0881S07S0771S06S0661S05S0551S04S0441S03S0331S02S0221S01S0111S00S0001RAM_COM4RAM_COM4display memory0x340x20read-write0x00000000S31S31311S30S30301S29S29291S28S28281S27S27271S26S26261S25S25251S24S24241S23S23231S22S22221S21S21211S20S20201S19S19191S18S18181S17S17171S16S16161S15S15151S14S14141S13S13131S12S12121S11S11111S10S10101S09S0991S08S0881S07S0771S06S0661S05S0551S04S0441S03S0331S02S0221S01S0111S00S0001RAM_COM5RAM_COM5display memory0x3C0x20read-write0x00000000S31S31311S30S30301S29S29291S28S28281S27S27271S26S26261S25S25251S24S24241S23S23231S22S22221S21S21211S20S20201S19S19191S18S18181S17S17171S16S16161S15S15151S14S14141S13S13131S12S12121S11S11111S10S10101S09S0991S08S0881S07S0771S06S0661S05S0551S04S0441S03S0331S02S0221S01S0111S00S0001RAM_COM6RAM_COM6display memory0x440x20read-write0x00000000S31S31311S30S30301S29S29291S28S28281S27S27271S26S26261S25S25251S24S24241S23S23231S22S22221S21S21211S20S20201S19S19191S18S18181S17S17171S16S16161S15S15151S14S14141S13S13131S12S12121S11S11111S10S10101S09S0991S08S0881S07S0771S06S0661S05S0551S04S0441S03S0331S02S0221S01S0111S00S0001RAM_COM7RAM_COM7display memory0x4C0x20read-write0x00000000S31S31311S30S30301S29S29291S28S28281S27S27271S26S26261S25S25251S24S24241S23S23231S22S22221S21S21211S20S20201S19S19191S18S18181S17S17171S16S16161S15S15151S14S14141S13S13131S12S12121S11S11111S10S10101S09S0991S08S0881S07S0771S06S0661S05S0551S04S0441S03S0331S02S0221S01S0111S00S0001TSCTouch sensing controllerTSC0x400240000x00x400registersTSCTSC global interrupt39CRCRcontrol register0x00x20read-write0x00000000CTPHCharge transfer pulse high284CTPLCharge transfer pulse low244SSDSpread spectrum deviation177SSESpread spectrum enable161SSPSCSpread spectrum prescaler151PGPSCpulse generator prescaler123MCVMax count value53IODEFI/O Default mode41SYNCPOLSynchronization pin polarity31AMAcquisition mode21STARTStart a new acquisition11TSCETouch sensing controller enable01IERIERinterrupt enable register0x40x20read-write0x00000000MCEIEMax count error interrupt enable11EOAIEEnd of acquisition interrupt enable01ICRICRinterrupt clear register0x80x20read-write0x00000000MCEICMax count error interrupt clear11EOAICEnd of acquisition interrupt clear01ISRISRinterrupt status register0xC0x20read-write0x00000000MCEFMax count error flag11EOAFEnd of acquisition flag01IOHCRIOHCRI/O hysteresis control register0x100x20read-write0xFFFFFFFFG7_IO4G7_IO4271G7_IO3G7_IO3261G7_IO2G7_IO2251G7_IO1G7_IO1241G6_IO4G6_IO4231G6_IO3G6_IO3221G6_IO2G6_IO2211G6_IO1G6_IO1201G5_IO4G5_IO4191G5_IO3G5_IO3181G5_IO2G5_IO2171G5_IO1G5_IO1161G4_IO4G4_IO4151G4_IO3G4_IO3141G4_IO2G4_IO2131G4_IO1G4_IO1121G3_IO4G3_IO4111G3_IO3G3_IO3101G3_IO2G3_IO291G3_IO1G3_IO181G2_IO4G2_IO471G2_IO3G2_IO361G2_IO2G2_IO251G2_IO1G2_IO141G1_IO4G1_IO431G1_IO3G1_IO321G1_IO2G1_IO211G1_IO1G1_IO101IOASCRIOASCRI/O analog switch control register0x180x20read-write0x00000000G7_IO4G7_IO4271G7_IO3G7_IO3261G7_IO2G7_IO2251G7_IO1G7_IO1241G6_IO4G6_IO4231G6_IO3G6_IO3221G6_IO2G6_IO2211G6_IO1G6_IO1201G5_IO4G5_IO4191G5_IO3G5_IO3181G5_IO2G5_IO2171G5_IO1G5_IO1161G4_IO4G4_IO4151G4_IO3G4_IO3141G4_IO2G4_IO2131G4_IO1G4_IO1121G3_IO4G3_IO4111G3_IO3G3_IO3101G3_IO2G3_IO291G3_IO1G3_IO181G2_IO4G2_IO471G2_IO3G2_IO361G2_IO2G2_IO251G2_IO1G2_IO141G1_IO4G1_IO431G1_IO3G1_IO321G1_IO2G1_IO211G1_IO1G1_IO101IOSCRIOSCRI/O sampling control register0x200x20read-write0x00000000G7_IO4G7_IO4271G7_IO3G7_IO3261G7_IO2G7_IO2251G7_IO1G7_IO1241G6_IO4G6_IO4231G6_IO3G6_IO3221G6_IO2G6_IO2211G6_IO1G6_IO1201G5_IO4G5_IO4191G5_IO3G5_IO3181G5_IO2G5_IO2171G5_IO1G5_IO1161G4_IO4G4_IO4151G4_IO3G4_IO3141G4_IO2G4_IO2131G4_IO1G4_IO1121G3_IO4G3_IO4111G3_IO3G3_IO3101G3_IO2G3_IO291G3_IO1G3_IO181G2_IO4G2_IO471G2_IO3G2_IO361G2_IO2G2_IO251G2_IO1G2_IO141G1_IO4G1_IO431G1_IO3G1_IO321G1_IO2G1_IO211G1_IO1G1_IO101IOCCRIOCCRI/O channel control register0x280x20read-write0x00000000G7_IO4G7_IO4271G7_IO3G7_IO3261G7_IO2G7_IO2251G7_IO1G7_IO1241G6_IO4G6_IO4231G6_IO3G6_IO3221G6_IO2G6_IO2211G6_IO1G6_IO1201G5_IO4G5_IO4191G5_IO3G5_IO3181G5_IO2G5_IO2171G5_IO1G5_IO1161G4_IO4G4_IO4151G4_IO3G4_IO3141G4_IO2G4_IO2131G4_IO1G4_IO1121G3_IO4G3_IO4111G3_IO3G3_IO3101G3_IO2G3_IO291G3_IO1G3_IO181G2_IO4G2_IO471G2_IO3G2_IO361G2_IO2G2_IO251G2_IO1G2_IO141G1_IO4G1_IO431G1_IO3G1_IO321G1_IO2G1_IO211G1_IO1G1_IO101IOGCSRIOGCSRI/O group control status register0x300x200x00000000G7SAnalog I/O group x status221read-onlyG6SAnalog I/O group x status211read-onlyG5SAnalog I/O group x status201read-onlyG4SAnalog I/O group x status191read-onlyG3SAnalog I/O group x status181read-onlyG2SAnalog I/O group x status171read-onlyG1SAnalog I/O group x status161read-onlyG7EAnalog I/O group x enable61read-writeG6EAnalog I/O group x enable51read-writeG5EAnalog I/O group x enable41read-writeG4EAnalog I/O group x enable31read-writeG3EAnalog I/O group x enable21read-writeG2EAnalog I/O group x enable11read-writeG1EAnalog I/O group x enable01read-writeIOG1CRIOG1CRI/O group x counter register0x340x20read-only0x00000000CNTCounter value014IOG2CRIOG2CRI/O group x counter register0x380x20read-only0x00000000CNTCounter value014IOG3CRIOG3CRI/O group x counter register0x3C0x20read-only0x00000000CNTCounter value014IOG4CRIOG4CRI/O group x counter register0x400x20read-only0x00000000CNTCounter value014IOG5CRIOG5CRI/O group x counter register0x440x20read-only0x00000000CNTCounter value014IOG6CRIOG6CRI/O group x counter register0x480x20read-only0x00000000CNTCounter value014IOG7CRIOG7CRI/O group x counter register0x4C0x20read-only0x00000000CNTCounter value014IWDGIndependent watchdogIWDG0x400030000x00x400registersKRKRKey register0x00x20write-only0x00000000KEYKey value (write only, read 0x0000)016PRPRPrescaler register0x40x20read-write0x00000000PRPrescaler divider03RLRRLRReload register0x80x20read-write0x00000FFFRLWatchdog counter reload value012SRSRStatus register0xC0x20read-only0x00000000WVUWatchdog counter window value update21RVUWatchdog counter reload value update11PVUWatchdog prescaler value update01WINRWINRWindow register0x100x20read-write0x00000FFFWINWatchdog counter window value012WWDGSystem window watchdogWWDG0x40002C000x00x400registersWWDGWindow Watchdog interrupt0CRCRControl register0x00x20read-write0x0000007FWDGAActivation bit71T7-bit counter (MSB to LSB)07CFRCFRConfiguration register0x40x20read-write0x0000007FWDGTBTimer base113EWIEarly wakeup interrupt91W7-bit window value07SRSRStatus register0x80x20read-write0x00000000EWIFEarly wakeup interrupt flag01I2C1Inter-integrated circuitI2C0x400054000x00x400registersI2C1_EVI2C1 event interrupt30I2C1_ERI2C1 error interrupt31CR1CR1Control register 10x00x20read-write0x00000000PEPeripheral enable01TXIETX Interrupt enable11RXIERX Interrupt enable21ADDRIEAddress match interrupt enable (slave only)31NACKIENot acknowledge received interrupt enable41STOPIESTOP detection Interrupt enable51TCIETransfer Complete interrupt enable61ERRIEError interrupts enable71DNFDigital noise filter84ANFOFFAnalog noise filter OFF121TXDMAENDMA transmission requests enable141RXDMAENDMA reception requests enable151SBCSlave byte control161NOSTRETCHClock stretching disable171WUPENWakeup from STOP enable181GCENGeneral call enable191SMBHENSMBus Host address enable201SMBDENSMBus Device Default address enable211ALERTENSMBUS alert enable221PECENPEC enable231CR2CR2Control register 20x40x20read-write0x00000000PECBYTEPacket error checking byte261AUTOENDAutomatic end mode (master mode)251RELOADNBYTES reload mode241NBYTESNumber of bytes168NACKNACK generation (slave mode)151STOPStop generation (master mode)141STARTStart generation131HEAD10R10-bit address header only read direction (master receiver mode)121ADD1010-bit addressing mode (master mode)111RD_WRNTransfer direction (master mode)101SADDSlave address bit (master mode)010OAR1OAR1Own address register 10x80x20read-write0x00000000OA1Interface address010OA1MODEOwn Address 1 10-bit mode101OA1ENOwn Address 1 enable151OAR2OAR2Own address register 20xC0x20read-write0x00000000OA2Interface address17OA2MSKOwn Address 2 masks83OA2ENOwn Address 2 enable151TIMINGRTIMINGRTiming register0x100x20read-write0x00000000SCLLSCL low period (master mode)08SCLHSCL high period (master mode)88SDADELData hold time164SCLDELData setup time204PRESCTiming prescaler284TIMEOUTRTIMEOUTRStatus register 10x140x20read-write0x00000000TIMEOUTABus timeout A012TIDLEIdle clock timeout detection121TIMOUTENClock timeout enable151TIMEOUTBBus timeout B1612TEXTENExtended clock timeout enable311ISRISRInterrupt and Status register0x180x200x00000001ADDCODEAddress match code (Slave mode)177read-onlyDIRTransfer direction (Slave mode)161read-onlyBUSYBus busy151read-onlyALERTSMBus alert131read-onlyTIMEOUTTimeout or t_low detection flag121read-onlyPECERRPEC Error in reception111read-onlyOVROverrun/Underrun (slave mode)101read-onlyARLOArbitration lost91read-onlyBERRBus error81read-onlyTCRTransfer Complete Reload71read-onlyTCTransfer Complete (master mode)61read-onlySTOPFStop detection flag51read-onlyNACKFNot acknowledge received flag41read-onlyADDRAddress matched (slave mode)31read-onlyRXNEReceive data register not empty (receivers)21read-onlyTXISTransmit interrupt status (transmitters)11read-writeTXETransmit data register empty (transmitters)01read-writeICRICRInterrupt clear register0x1C0x20write-only0x00000000ALERTCFAlert flag clear131TIMOUTCFTimeout detection flag clear121PECCFPEC Error flag clear111OVRCFOverrun/Underrun flag clear101ARLOCFArbitration lost flag clear91BERRCFBus error flag clear81STOPCFStop detection flag clear51NACKCFNot Acknowledge flag clear41ADDRCFAddress Matched flag clear31PECRPECRPEC register0x200x20read-only0x00000000PECPacket error checking register08RXDRRXDRReceive data register0x240x20read-only0x00000000RXDATA8-bit receive data08TXDRTXDRTransmit data register0x280x20read-write0x00000000TXDATA8-bit transmit data08I2C30x40005C00I2C3_EVI2C3 event interrupt32I2C3_ERI2C3 error interrupt33FlashFlashFlash0x580040000x00x90registersFLASHFlash global interrupt4ACRACRAccess control register0x00x20read-write0x00000600LATENCYLatency03PRFTENPrefetch enable81ICENInstruction cache enable91DCENData cache enable101ICRSTInstruction cache reset111DCRSTData cache reset121PESCPU1 CortexM4 program erase suspend request151EMPTYFlash User area empty161KEYRKEYRFlash key register0x80x20write-only0x00000000KEYRKEYR032OPTKEYROPTKEYROption byte key register0xC0x20write-only0x00000000OPTKEYROption byte key032SRSRStatus register0x100x200x00000000EOPEnd of operation01read-writeOPERROperation error11read-writePROGERRProgramming error31read-writeWRPERRWrite protected error41read-writePGAERRProgramming alignment error51read-writeSIZERRSize error61read-writePGSERRProgramming sequence error71read-writeMISERRFast programming data miss error81read-writeFASTERRFast programming error91read-writeOPTNVUser Option OPTVAL indication131read-onlyRDERRPCROP read error141read-writeOPTVERROption validity error151read-writeBSYBusy161read-onlyCFGBSYProgramming or erase configuration busy181read-onlyPESDProgramming or erase operation suspended191read-onlyCRCRFlash control register0x140x20read-write0xC0000000PGProgramming01PERPage erase11MERThis bit triggers the mass erase (all user pages) when set21PNBPage number selection38STRTStart161OPTSTRTOptions modification start171FSTPGFast programming181EOPIEEnd of operation interrupt enable241ERRIEError interrupt enable251RDERRIEPCROP read error interrupt enable261OBL_LAUNCHForce the option byte loading271OPTLOCKOptions Lock301LOCKFLASH_CR Lock311ECCRECCRFlash ECC register0x180x200x00000000ADDR_ECCECC fail address017read-onlySYSF_ECCSystem Flash ECC fail201read-onlyECCCIEECC correction interrupt enable241read-writeCPUIDCPU identification263read-onlyECCCECC correction301read-writeECCDECC detection311read-writeOPTROPTRFlash option register0x200x20read-write0x10708000RDPRead protection level08ESESecurity enabled81BOR_LEVBOR reset Level93nRST_STOPnRST_STOP121nRST_STDBYnRST_STDBY131nRST_SHDWnRST_SHDW141IDWG_SWIndependent watchdog selection161IWDG_STOPIndependent watchdog counter freeze in Stop mode171IWDG_STDBYIndependent watchdog counter freeze in Standby mode181WWDG_SWWindow watchdog selection191nBOOT1Boot configuration231SRAM2_PESRAM2 parity check enable241SRAM2_RSTSRAM2 Erase when system reset251nSWBOOT0Software Boot0261nBOOT0nBoot0 option bit271AGC_TRIMRadio Automatic Gain Control Trimming293PCROP1ASRPCROP1ASRFlash Bank 1 PCROP Start address zone A register0x240x20read-write0xFFFFFE00PCROP1A_STRTBank 1 PCROPQ area start offset09PCROP1AERPCROP1AERFlash Bank 1 PCROP End address zone A register0x280x20read-write0x7FFFFE00PCROP1A_ENDBank 1 PCROP area end offset09PCROP_RDPPCROP area preserved when RDP level decreased311WRP1ARWRP1ARFlash Bank 1 WRP area A address register0x2C0x20read-write0xFF00FF00WRP1A_STRTBank 1 WRP first area A start offset08WRP1A_ENDBank 1 WRP first area A end offset168WRP1BRWRP1BRFlash Bank 1 WRP area B address register0x300x20read-write0xFF00FF00WRP1B_STRTBank 1 WRP second area B end offset168WRP1B_ENDBank 1 WRP second area B start offset08PCROP1BSRPCROP1BSRFlash Bank 1 PCROP Start address area B register0x340x20read-write0xFFFFFE00PCROP1B_STRTBank 1 PCROP area B start offset09PCROP1BERPCROP1BERFlash Bank 1 PCROP End address area B register0x380x20read-write0xFFFFFE00PCROP1B_ENDBank 1 PCROP area end area B offset09IPCCBRIPCCBRIPCC mailbox data buffer address register0x3C0x20read-write0xFFFFC000IPCCDBAPCC mailbox data buffer base address014C2ACRC2ACRCPU2 cortex M0 access control register0x5C0x20read-write0x00000600PRFTENCPU2 cortex M0 prefetch enable81ICENCPU2 cortex M0 instruction cache enable91ICRSTCPU2 cortex M0 instruction cache reset111PESCPU2 cortex M0 program erase suspend request151C2SRC2SRCPU2 cortex M0 status register0x600x20read-write0x00000000EOPEnd of operation01OPERROperation error11PROGERRProgramming error31WRPERRwrite protection error41PGAERRProgramming alignment error51SIZERRSize error61PGSERRProgramming sequence error71MISSERRFast programming data miss error81FASTERRFast programming error91RDERRPCROP read error141BSYBusy161CFGBSYProgramming or erase configuration busy181PESDProgramming or erase operation suspended191C2CRC2CRCPU2 cortex M0 control register0x640x20read-write0x00000000PGProgramming01PERPage erase11MERMasse erase21PNBPage Number selection38STRTStart161FSTPGFast programming181EOPIEEnd of operation interrupt enable241ERRIEError interrupt enable251RDERRIEPCROP read error interrupt enable261SFRSFRSecure flash start address register0x800x20read-write0xFFFFEE00SFSASecure flash start address08DDSDisable Cortex M0 debug access121FSDFlash security disable81SRRVRSRRVRSecure SRAM2 start address and cortex M0 reset vector register0x840x20read-write0x01000000SBRVcortex M0 access control register018SBRSASecure backup SRAM2a start address185BRSDbackup SRAM2a security disable231SNBRSASecure non backup SRAM2a start address255C2OPTCPU2 cortex M0 boot reset vector memory selection311NBRSDnon-backup SRAM2b security disable301QUADSPIQuadSPI interfaceQUADSPI0xA00010000x00x400registersQUADSPIQSPI global interrupt50CRCRcontrol register0x00x20read-write0x00000000PRESCALERClock prescaler248PMMPolling match mode231APMSAutomatic poll mode stop221TOIETimeOut interrupt enable201SMIEStatus match interrupt enable191FTIEFIFO threshold interrupt enable181TCIETransfer complete interrupt enable171TEIETransfer error interrupt enable161FTHRESFIFO threshold level85SSHIFTSample shift41TCENTimeout counter enable31DMAENDMA enable21ABORTAbort request11ENEnable01DCRDCRdevice configuration register0x40x20read-write0x00000000FSIZEFLASH memory size165CSHTChip select high time83CKMODEMode 0 / mode 301SRSRstatus register0x80x20read-only0x00000000FLEVELFIFO level86BUSYBusy51TOFTimeout flag41SMFStatus match flag31FTFFIFO threshold flag21TCFTransfer complete flag11TEFTransfer error flag01FCRFCRflag clear register0xC0x20read-write0x00000000CTOFClear timeout flag41CSMFClear status match flag31CTCFClear transfer complete flag11CTEFClear transfer error flag01DLRDLRdata length register0x100x20read-write0x00000000DLData length032CCRCCRcommunication configuration register0x140x20read-write0x00000000DDRMDouble data rate mode311SIOOSend instruction only once mode281FMODEFunctional mode262DMODEData mode242DCYCNumber of dummy cycles185ABSIZEAlternate bytes size162ABMODEAlternate bytes mode142ADSIZEAddress size122ADMODEAddress mode102IMODEInstruction mode82INSTRUCTIONInstruction08ARARaddress register0x180x20read-write0x00000000ADDRESSAddress032ABRABRABR0x1C0x20read-write0x00000000ALTERNATEALTERNATE032DRDRdata register0x200x20read-write0x00000000DATAData032PSMKRPSMKRpolling status mask register0x240x20read-write0x00000000MASKStatus mask032PSMARPSMARpolling status match register0x280x20read-write0x00000000MATCHStatus match032PIRPIRpolling interval register0x2C0x20read-write0x00000000INTERVALPolling interval016LPTRLPTRlow-power timeout register0x300x20read-write0x00000000TIMEOUTTimeout period016RCCReset and clock controlRCC0x580000000x00x400registersRCCRCC global interrupt5CRCRClock control register0x00x200x00000061PLLSAI1RDYSAI1 PLL clock ready flag271read-onlyPLLSAI1ONSAI1 PLL enable261read-writePLLRDYMain PLL clock ready flag251read-onlyPLLONMain PLL enable241read-writeHSEPREHSE sysclk and PLL M divider prescaler201read-writeCSSONHSE Clock security system enable191write-onlyHSEBYPHSE crystal oscillator bypass181read-writeHSERDYHSE clock ready flag171read-onlyHSEONHSE clock enabled161read-writeHSIKERDYHSI kernel clock ready flag for peripherals requests121read-onlyHSIASFSHSI automatic start from Stop111read-writeHSIRDYHSI clock ready flag101read-onlyHSIKERONHSI always enable for peripheral kernels91read-writeHSIONHSI clock enabled81read-writeMSIRANGEMSI clock ranges44read-writeMSIPLLENMSI clock PLL enable21read-writeMSIRDYMSI clock ready flag11read-onlyMSIONMSI clock enable01read-writeICSCRICSCRInternal clock sources calibration register0x40x200x40000000HSITRIMHSI clock trimming247read-writeHSICALHSI clock calibration168read-onlyMSITRIMMSI clock trimming88read-writeMSICALMSI clock calibration08read-onlyCFGRCFGRClock configuration register0x80x200x00070000MCOPREMicrocontroller clock output prescaler283read-writeMCOSELMicrocontroller clock output244read-writePPRE2FAPB2 prescaler flag181read-onlyPPRE1FAPB1 prescaler flag171read-onlyHPREFAHB prescaler flag161read-onlySTOPWUCKWakeup from Stop and CSS backup clock selection151read-writePPRE2APB high-speed prescaler (APB2)113read-writePPRE1PB low-speed prescaler (APB1)83read-writeHPREAHB prescaler44read-writeSWSSystem clock switch status22read-onlySWSystem clock switch02read-writePLLCFGRPLLCFGRPLLSYS configuration register0xC0x20read-write0x22040100PLLRMain PLLSYS division factor R for SYSCLK (system clock)293PLLRENMain PLLSYSR PLLCLK output enable281PLLQMain PLLSYS division factor Q for PLLSYSUSBCLK253PLLQENMain PLLSYSQ output enable241PLLPMain PLL division factor P for PPLSYSSAICLK175PLLPENMain PLLSYSP output enable161PLLNMain PLLSYS multiplication factor N87PLLMDivision factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock43PLLSRCMain PLL, PLLSAI1 and PLLSAI2 entry clock source02PLLSAI1CFGRPLLSAI1CFGRPLLSAI1 configuration register0x100x20read-write0x22040100PLLRPLLSAI division factor R for PLLADC1CLK (ADC clock)293PLLRENPLLSAI PLLADC1CLK output enable281PLLQSAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)253PLLQENSAIPLL PLLSAIUSBCLK output enable241PLLPSAI1PLL division factor P for PLLSAICLK (SAI1clock)175PLLPENSAIPLL PLLSAI1CLK output enable161PLLNSAIPLL multiplication factor for VCO87CIERCIERClock interrupt enable register0x180x20read-write0x00000000LSI2RDYIELSI2 ready interrupt enable111HSI48RDYIEHSI48 ready interrupt enable101LSECSSIELSE clock security system interrupt enable91PLLSAI1RDYIEPLLSAI1 ready interrupt enable61PLLRDYIEPLLSYS ready interrupt enable51HSERDYIEHSE ready interrupt enable41HSIRDYIEHSI ready interrupt enable31MSIRDYIEMSI ready interrupt enable21LSERDYIELSE ready interrupt enable11LSI1RDYIELSI1 ready interrupt enable01CIFRCIFRClock interrupt flag register0x1C0x20read-only0x00000000LSI2RDYFLSI2 ready interrupt flag111HSI48RDYFHSI48 ready interrupt flag101LSECSSFLSE Clock security system interrupt flag91HSECSSFHSE Clock security system interrupt flag81PLLSAI1RDYFPLLSAI1 ready interrupt flag61PLLRDYFPLL ready interrupt flag51HSERDYFHSE ready interrupt flag41HSIRDYFHSI ready interrupt flag31MSIRDYFMSI ready interrupt flag21LSERDYFLSE ready interrupt flag11LSI1RDYFLSI1 ready interrupt flag01CICRCICRClock interrupt clear register0x200x20write-only0x00000000LSI2RDYCLSI2 ready interrupt clear111HSI48RDYCHSI48 ready interrupt clear101LSECSSCLSE Clock security system interrupt clear91HSECSSCHSE Clock security system interrupt clear81PLLSAI1RDYCPLLSAI1 ready interrupt clear61PLLRDYCPLL ready interrupt clear51HSERDYCHSE ready interrupt clear41HSIRDYCHSI ready interrupt clear31MSIRDYCMSI ready interrupt clear21LSERDYCLSE ready interrupt clear11LSI1RDYCLSI1 ready interrupt clear01SMPSCRSMPSCRStep Down converter control register0x240x200x00000301SMPSSWSStep Down converter clock switch status82read-onlySMPSDIVStep Down converter clock prescaler42read-writeSMPSSELStep Down converter clock selection02read-writeAHB1RSTRAHB1RSTRAHB1 peripheral reset register0x280x20read-write0x00000000TSCRSTTouch Sensing Controller reset161CRCRSTCRC reset121DMAMUXRSTDMAMUX reset21DMA2RSTDMA2 reset11DMA1RSTDMA1 reset01AHB2RSTRAHB2RSTRAHB2 peripheral reset register0x2C0x20read-write0x00000000AES1RSTAES1 hardware accelerator reset161ADCRSTADC reset131GPIOHRSTIO port H reset71GPIOERSTIO port E reset41GPIODRSTIO port D reset31GPIOCRSTIO port C reset21GPIOBRSTIO port B reset11GPIOARSTIO port A reset01AHB3RSTRAHB3RSTRAHB3 peripheral reset register0x300x20read-write0x00000000FLASHRSTFlash interface reset251IPCCRSTIPCC interface reset201HSEMRSTHSEM interface reset191RNGRSTRNG interface reset181AES2RSTAES2 interface reset171PKARSTPKA interface reset161QSPIRSTQuad SPI memory interface reset81APB1RSTR1APB1RSTR1APB1 peripheral reset register 10x380x20read-write0x00000000LPTIM1RSTLow Power Timer 1 reset311USBFSRSTUSB FS reset261CRSRSTCRS reset241I2C3RSTI2C3 reset231I2C1RSTI2C1 reset211SPI2RSTSPI2 reset141LCDRSTLCD interface reset91TIM2RSTTIM2 timer reset01APB1RSTR2APB1RSTR2APB1 peripheral reset register 20x3C0x20read-write0x00000000LPTIM2RSTLow-power timer 2 reset51LPUART1RSTLow-power UART 1 reset01APB2RSTRAPB2RSTRAPB2 peripheral reset register0x400x20read-write0x00000000SAI1RSTSerial audio interface 1 (SAI1) reset211TIM17RSTTIM17 timer reset181TIM16RSTTIM16 timer reset171USART1RSTUSART1 reset141SPI1RSTSPI1 reset121TIM1RSTTIM1 timer reset111APB3RSTRAPB3RSTRAPB3 peripheral reset register0x440x20read-write0x00000000RFRSTRadio system BLE reset01AHB1ENRAHB1ENRAHB1 peripheral clock enable register0x480x20read-write0x00000100TSCENTouch Sensing Controller clock enable161CRCENCPU1 CRC clock enable121DMAMUXENDMAMUX clock enable21DMA2ENDMA2 clock enable11DMA1ENDMA1 clock enable01AHB2ENRAHB2ENRAHB2 peripheral clock enable register0x4C0x20read-write0x00000000AES1ENAES1 accelerator clock enable161ADCENADC clock enable131GPIOHENIO port H clock enable71GPIOEENIO port E clock enable41GPIODENIO port D clock enable31GPIOCENIO port C clock enable21GPIOBENIO port B clock enable11GPIOAENIO port A clock enable01AHB3ENRAHB3ENRAHB3 peripheral clock enable register0x500x20read-write0x02080000FLASHENFLASHEN251IPCCENIPCCEN201HSEMENHSEMEN191RNGENRNGEN181AES2ENAES2EN171PKAENPKAEN161QSPIENQSPIEN81APB1ENR1APB1ENR1APB1ENR10x580x20read-write0x00000400LPTIM1ENCPU1 Low power timer 1 clock enable311USBENCPU1 USB clock enable261CRSENCPU1 CRS clock enable241I2C3ENCPU1 I2C3 clock enable231I2C1ENCPU1 I2C1 clock enable211SPI2ENCPU1 SPI2 clock enable141WWDGENCPU1 Window watchdog clock enable111RTCAPBENCPU1 RTC APB clock enable101LCDENCPU1 LCD clock enable91TIM2ENCPU1 TIM2 timer clock enable01APB1ENR2APB1ENR2APB1 peripheral clock enable register 20x5C0x20read-write0x00000000LPTIM2ENCPU1 LPTIM2EN51LPUART1ENCPU1 Low power UART 1 clock enable01APB2ENRAPB2ENRAPB2ENR0x600x20read-write0x00000000SAI1ENCPU1 SAI1 clock enable211TIM17ENCPU1 TIM17 timer clock enable181TIM16ENCPU1 TIM16 timer clock enable171USART1ENCPU1 USART1clock enable141SPI1ENCPU1 SPI1 clock enable121TIM1ENCPU1 TIM1 timer clock enable111AHB1SMENRAHB1SMENRAHB1 peripheral clocks enable in Sleep and Stop modes register0x680x20read-write0x00011207TSCSMENCPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes161CRCSMENCPU1 CRCSMEN121SRAM1SMENCPU1 SRAM1 interface clocks enable during Sleep and Stop modes91DMAMUXSMENCPU1 DMAMUX clocks enable during Sleep and Stop modes21DMA2SMENCPU1 DMA2 clocks enable during Sleep and Stop modes11DMA1SMENCPU1 DMA1 clocks enable during Sleep and Stop modes01AHB2SMENRAHB2SMENRAHB2 peripheral clocks enable in Sleep and Stop modes register0x6C0x20read-write0x0001209FAES1SMENCPU1 AES1 accelerator clocks enable during Sleep and Stop modes161ADCFSSMENCPU1 ADC clocks enable during Sleep and Stop modes131GPIOHSMENCPU1 IO port H clocks enable during Sleep and Stop modes71GPIOESMENCPU1 IO port E clocks enable during Sleep and Stop modes41GPIODSMENCPU1 IO port D clocks enable during Sleep and Stop modes31GPIOCSMENCPU1 IO port C clocks enable during Sleep and Stop modes21GPIOBSMENCPU1 IO port B clocks enable during Sleep and Stop modes11GPIOASMENCPU1 IO port A clocks enable during Sleep and Stop modes01AHB3SMENRAHB3SMENRAHB3 peripheral clocks enable in Sleep and Stop modes register0x700x20read-write0x03070100FLASHSMENFlash interface clocks enable during CPU1 sleep mode251SRAM2SMENSRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode241RNGSMENTrue RNG clocks enable during CPU1 sleep mode181AES2SMENAES2 accelerator clocks enable during CPU1 sleep mode171PKASMENPKA accelerator clocks enable during CPU1 sleep mode161QSPISMENQSPISMEN81APB1SMENR1APB1SMENR1APB1SMENR10x780x20read-write0x85A04E01LPTIM1SMENLow power timer 1 clocks enable during CPU1 Sleep mode311USBSMENUSB FS clocks enable during CPU1 Sleep mode261CRSMENCRS clocks enable during CPU1 Sleep mode241I2C3SMENI2C3 clocks enable during CPU1 Sleep mode231I2C1SMENI2C1 clocks enable during CPU1 Sleep mode211SPI2SMENSPI2 clocks enable during CPU1 Sleep mode141WWDGSMENWindow watchdog clocks enable during CPU1 Sleep mode111RTCAPBSMENRTC APB clocks enable during CPU1 Sleep mode101LCDSMENLCD clocks enable during CPU1 Sleep mode91TIM2SMENTIM2 timer clocks enable during CPU1 Sleep mode01APB1SMENR2APB1SMENR2APB1 peripheral clocks enable in Sleep and Stop modes register 20x7C0x20read-write0x000000021LPTIM2SMENLow power timer 2 clocks enable during CPU1 Sleep mode51LPUART1SMENLow power UART 1 clocks enable during CPU1 Sleep mode01APB2SMENRAPB2SMENRAPB2SMENR0x800x20read-write0x00265800SAI1SMENSAI1 clocks enable during CPU1 Sleep mode211TIM17SMENTIM17 timer clocks enable during CPU1 Sleep mode181TIM16SMENTIM16 timer clocks enable during CPU1 Sleep mode171USART1SMENUSART1clocks enable during CPU1 Sleep mode141SPI1SMENSPI1 clocks enable during CPU1 Sleep mode121TIM1SMENTIM1 timer clocks enable during CPU1 Sleep mode111CCIPRCCIPRCCIPR0x880x20read-write0x00000000RNGSELRNG clock source selection302ADCSELADCs clock source selection282CLK48SEL48 MHz clock source selection262SAI1SELSAI1 clock source selection222LPTIM2SELLow power timer 2 clock source selection202LPTIM1SELLow power timer 1 clock source selection182I2C3SELI2C3 clock source selection162I2C1SELI2C1 clock source selection122LPUART1SELLPUART1 clock source selection102USART1SELUSART1 clock source selection02BDCRBDCRBDCR0x900x200x00000000LSCOSELLow speed clock output selection251read-writeLSCOENLow speed clock output enable241read-writeBDRSTBackup domain software reset161read-writeRTCENRTC clock enable151read-writeRTCSELRTC clock source selection82read-writeLSECSSD_CSS on LSE failure detection61read-onlyLSECSSONLSECSSON51read-writeLSEDRVSE oscillator drive capability32read-writeLSEBYPLSE oscillator bypass21read-writeLSERDYLSE oscillator ready11read-onlyLSEONLSE oscillator enable01read-writeCSRCSRCSR0x940x200x0C000000LPWRRSTFLow-power reset flag311read-onlyWWDGRSTFWindow watchdog reset flag301read-onlyIWDGRSTFIndependent window watchdog reset flag291read-onlySFTRSTFSoftware reset flag281read-onlyBORRSTFBOR flag271read-onlyPINRSTFPin reset flag261read-onlyOBLRSTFOption byte loader reset flag251read-onlyRMVFRemove reset flag231read-writeRFWKPSELRF system wakeup clock source selection142read-writeLSI2BWLSI2 oscillator bias configuration84read-writeLSI2TRIMOKLSI2 oscillator trim OK51read-onlyLSI2TRIMENLSI2 oscillator trimming enable41read-writeLSI2RDYLSI2 oscillator ready31read-onlyLSI2ONLSI2 oscillator enabled21read-writeLSI1RDYLSI1 oscillator ready11read-onlyLSI1ONLSI1 oscillator enabled01read-writeRFRSTSRadio system BLE and 802.15.4 reset status161read-onlyCRRCRCRRCRClock recovery RC register0x980x200x00000000HSI48CALHSI48 clock calibration79read-onlyHSI48RDYHSI48 clock ready11read-onlyHSI48ONHSI48 oscillator enabled01read-writeHSECRHSECRClock HSE register0x9C0x200x00000030HSETUNEHSE capacitor tuning86read-onlyHSEGMCHSE current control43read-writeHSESHSE Sense amplifier threshold31read-writeUNLOCKEDRegister lock system01read-writeEXTCFGREXTCFGRExtended clock recovery register0x1080x200x00030000RFCSSRF clock source selected201read-onlyC2HPREFCPU2 AHB prescaler flag171read-onlySHDHPREFShared AHB prescaler flag161read-onlyC2HPRECPU2 AHB prescaler44read-writeSHDHPREShared AHB prescaler04read-writeC2AHB1ENRC2AHB1ENRCPU2 AHB1 peripheral clock enable register0x1480x20read-write0x00000000TSCENCPU2 Touch Sensing Controller clock enable161CRCENCPU2 CRC clock enable121SRAM1ENCPU2 SRAM1 clock enable91DMAMUXENCPU2 DMAMUX clock enable21DMA2ENCPU2 DMA2 clock enable11DMA1ENCPU2 DMA1 clock enable01C2AHB2ENRC2AHB2ENRCPU2 AHB2 peripheral clock enable register0x14C0x20read-write0x00000000AES1ENCPU2 AES1 accelerator clock enable161ADCENCPU2 ADC clock enable131GPIOHENCPU2 IO port H clock enable71GPIOEENCPU2 IO port E clock enable41GPIODENCPU2 IO port D clock enable31GPIOCENCPU2 IO port C clock enable21GPIOBENCPU2 IO port B clock enable11GPIOAENCPU2 IO port A clock enable01C2AHB3ENRC2AHB3ENRCPU2 AHB3 peripheral clock enable register0x1500x20read-write0x02080000FLASHENCPU2 FLASHEN251IPCCENCPU2 IPCCEN201HSEMENCPU2 HSEMEN191RNGENCPU2 RNGEN181AES2ENCPU2 AES2EN171PKAENCPU2 PKAEN161C2APB1ENR1C2APB1ENR1CPU2 APB1ENR10x1580x20read-write0x00000400LPTIM1ENCPU2 Low power timer 1 clock enable311USBENCPU2 USB clock enable261CRSENCPU2 CRS clock enable241I2C3ENCPU2 I2C3 clock enable231I2C1ENCPU2 I2C1 clock enable211SPI2ENCPU2 SPI2 clock enable141RTCAPBENCPU2 RTC APB clock enable101LCDENCPU2 LCD clock enable91TIM2ENCPU2 TIM2 timer clock enable01C2APB1ENR2C2APB1ENR2CPU2 APB1 peripheral clock enable register 20x15C0x20read-write0x00000000LPTIM2ENCPU2 LPTIM2EN51LPUART1ENCPU2 Low power UART 1 clock enable01C2APB2ENRC2APB2ENRCPU2 APB2ENR0x1600x20read-write0x00000000SAI1ENCPU2 SAI1 clock enable211TIM17ENCPU2 TIM17 timer clock enable181TIM16ENCPU2 TIM16 timer clock enable171USART1ENCPU2 USART1clock enable141SPI1ENCPU2 SPI1 clock enable121TIM1ENCPU2 TIM1 timer clock enable111C2APB3ENRC2APB3ENRCPU2 APB3ENR0x1640x20read-write0x00000000EN802CPU2 802.15.4 interface clock enable11BLEENCPU2 BLE interface clock enable01C2AHB1SMENRC2AHB1SMENRCPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register0x1680x20read-write0x00011207TSCSMENCPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes161CRCSMENCPU2 CRCSMEN121SRAM1SMENSRAM1 interface clock enable during CPU1 CSleep mode91DMAMUXSMENCPU2 DMAMUX clocks enable during Sleep and Stop modes21DMA2SMENCPU2 DMA2 clocks enable during Sleep and Stop modes11DMA1SMENCPU2 DMA1 clocks enable during Sleep and Stop modes01C2AHB2SMENRC2AHB2SMENRCPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register0x16C0x20read-write0x0001209FAES1SMENCPU2 AES1 accelerator clocks enable during Sleep and Stop modes161ADCFSSMENCPU2 ADC clocks enable during Sleep and Stop modes131GPIOHSMENCPU2 IO port H clocks enable during Sleep and Stop modes71GPIOESMENCPU2 IO port E clocks enable during Sleep and Stop modes41GPIODSMENCPU2 IO port D clocks enable during Sleep and Stop modes31GPIOCSMENCPU2 IO port C clocks enable during Sleep and Stop modes21GPIOBSMENCPU2 IO port B clocks enable during Sleep and Stop modes11GPIOASMENCPU2 IO port A clocks enable during Sleep and Stop modes01C2AHB3SMENRC2AHB3SMENRCPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register0x1700x20read-write0x03070000FLASHSMENFlash interface clocks enable during CPU2 sleep modes251SRAM2SMENSRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes241RNGSMENTrue RNG clocks enable during CPU2 sleep modes181AES2SMENAES2 accelerator clocks enable during CPU2 sleep modes171PKASMENPKA accelerator clocks enable during CPU2 sleep modes161C2APB1SMENR1C2APB1SMENR1CPU2 APB1SMENR10x1780x20read-write0x85A04601LPTIM1SMENLow power timer 1 clocks enable during CPU2 Sleep mode311USBSMENUSB FS clocks enable during CPU2 Sleep mode261CRSMENCRS clocks enable during CPU2 Sleep mode241I2C3SMENI2C3 clocks enable during CPU2 Sleep mode231I2C1SMENI2C1 clocks enable during CPU2 Sleep mode211SPI2SMENSPI2 clocks enable during CPU2 Sleep mode141RTCAPBSMENRTC APB clocks enable during CPU2 Sleep mode101LCDSMENLCD clocks enable during CPU2 Sleep mode91TIM2SMENTIM2 timer clocks enable during CPU2 Sleep mode01C2APB1SMENR2C2APB1SMENR2CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 20x17C0x20read-write0x000000021LPTIM2SMENLow power timer 2 clocks enable during CPU2 Sleep mode51LPUART1SMENLow power UART 1 clocks enable during CPU2 Sleep mode01C2APB2SMENRC2APB2SMENRCPU2 APB2SMENR0x1800x20read-write0x00265800SAI1SMENSAI1 clocks enable during CPU2 Sleep mode211TIM17SMENTIM17 timer clocks enable during CPU2 Sleep mode181TIM16SMENTIM16 timer clocks enable during CPU2 Sleep mode171USART1SMENUSART1clocks enable during CPU2 Sleep mode141SPI1SMENSPI1 clocks enable during CPU2 Sleep mode121TIM1SMENTIM1 timer clocks enable during CPU2 Sleep mode111C2APB3SMENRC2APB3SMENRCPU2 APB3SMENR0x1840x20read-write0x0000003SMEN802802.15.4 interface clocks enable during CPU2 Sleep modes11BLESMENBLE interface clocks enable during CPU2 Sleep mode01PWRPower controlPWR0x580004000x00x400registersPWR_SOTFPWR switching on the fly interrupt43CR1CR1Power control register 10x00x20read-write0x00000200LPRLow-power run141VOSVoltage scaling range selection92DBPDisable backup domain write protection81FPDSFlash power down mode during LPsSleep for CPU151FPDRFlash power down mode during LPRun for CPU141LPMSLow-power mode selection for CPU103CR2CR2Power control register 20x40x20read-write0x00000000USVVDDUSB USB supply valid101PVME3Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V61PVME1Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V41PLSPower voltage detector level selection13PVDEPower voltage detector enable01CR3CR3Power control register 30x80x20read-write0x00008000EIWULEnable internal wakeup line for CPU1151EC2HEnable CPU2 Hold interrupt for CPU1141E802AEnable end of activity interrupt for CPU1131EBLEAEnable BLE end of activity interrupt for CPU1111ECRPEEnable critical radio phase end of activity interrupt for CPU1121APCApply pull-up and pull-down configuration101RRSSRAM2a retention in Standby mode91EBORHSDFBEnable BORH and Step Down counverter forced in Bypass interrups for CPU181EWUP5Enable Wakeup pin WKUP541EWUP4Enable Wakeup pin WKUP431EWUP3Enable Wakeup pin WKUP321EWUP2Enable Wakeup pin WKUP211EWUP1Enable Wakeup pin WKUP101CR4CR4Power control register 40xC0x20read-write0x00000000C2BOOTBOOT CPU2 after reset or wakeup from Stop or Standby modes151VBRSVBAT battery charging resistor selection91VBEVBAT battery charging enable81WP5Wakeup pin WKUP5 polarity41WP4Wakeup pin WKUP4 polarity31WP3Wakeup pin WKUP3 polarity21WP2Wakeup pin WKUP2 polarity11WP1Wakeup pin WKUP1 polarity01SR1SR1Power status register 10x100x20read-only0x00000000WUFIInternal Wakeup interrupt flag151C2HFCPU2 Hold interrupt flag141AF802802.15.4 end of activity interrupt flag131BLEAFBLE end of activity interrupt flag121CRPEFEnable critical radio phase end of activity interrupt flag111WUF802802.15.4 wakeup interrupt flag101BLEWUFBLE wakeup interrupt flag91BORHFBORH interrupt flag81SDFBFStep Down converter forced in Bypass interrupt flag71CWUF5Wakeup flag 541CWUF4Wakeup flag 431CWUF3Wakeup flag 321CWUF2Wakeup flag 211CWUF1Wakeup flag 101SR2SR2Power status register 20x140x20read-only0x00000002PVMO3Peripheral voltage monitoring output: VDDA vs. 1.62 V141PVMO1Peripheral voltage monitoring output: VDDUSB vs. 1.2 V121PVDOPower voltage detector output111VOSFVoltage scaling flag101REGLPFLow-power regulator flag91REGLPSLow-power regulator started81SDSMPSFStep Down converter SMPS mode flag11SDBFStep Down converter Bypass mode flag01SCRSCRPower status clear register0x180x20write-only0x00000000CC2HFClear CPU2 Hold interrupt flag141C802AFClear 802.15.4 end of activity interrupt flag131CBLEAFClear BLE end of activity interrupt flag121CCRPEFClear critical radio phase end of activity interrupt flag111C802WUFClear 802.15.4 wakeup interrupt flag101CBLEWUFClear BLE wakeup interrupt flag91CBORHFClear BORH interrupt flag81CSMPSFBFClear SMPS Step Down converter forced in Bypass interrupt flag71CWUF5Clear wakeup flag 541CWUF4Clear wakeup flag 431CWUF3Clear wakeup flag 321CWUF2Clear wakeup flag 211CWUF1Clear wakeup flag 101CR5CR5Power control register 50x1C0x20read-write0x00004270SDEBEnable Step Down converter SMPS mode enabled151SDBENEnable Step Down converter Bypass mode enabled141SMPSCFGVOS configuration selection (non user)91BORHCBORH configuration selection81SDSCStep Down converter supplt startup current selection43SDVOSStep Down converter voltage output scaling04PUCRAPUCRAPower Port A pull-up control register0x200x20read-write0x00000000PU15Port A pull-up bit y (y=0..15)151PU13Port A pull-up bit y (y=0..15)131PU12Port A pull-up bit y (y=0..15)121PU11Port A pull-up bit y (y=0..15)111PU10Port A pull-up bit y (y=0..15)101PU9Port A pull-up bit y (y=0..15)91PU8Port A pull-up bit y (y=0..15)81PU7Port A pull-up bit y (y=0..15)71PU6Port A pull-up bit y (y=0..15)61PU5Port A pull-up bit y (y=0..15)51PU4Port A pull-up bit y (y=0..15)41PU3Port A pull-up bit y (y=0..15)31PU2Port A pull-up bit y (y=0..15)21PU1Port A pull-up bit y (y=0..15)11PU0Port A pull-up bit y (y=0..15)01PDCRAPDCRAPower Port A pull-down control register0x240x20read-write0x00000000PD14Port A pull-down bit y (y=0..15)141PD12Port A pull-down bit y (y=0..15)121PD11Port A pull-down bit y (y=0..15)111PD10Port A pull-down bit y (y=0..15)101PD9Port A pull-down bit y (y=0..15)91PD8Port A pull-down bit y (y=0..15)81PD7Port A pull-down bit y (y=0..15)71PD6Port A pull-down bit y (y=0..15)61PD5Port A pull-down bit y (y=0..15)51PD4Port A pull-down bit y (y=0..15)41PD3Port A pull-down bit y (y=0..15)31PD2Port A pull-down bit y (y=0..15)21PD1Port A pull-down bit y (y=0..15)11PD0Port A pull-down bit y (y=0..15)01PUCRBPUCRBPower Port B pull-up control register0x280x20read-write0x00000000PU15Port B pull-up bit y (y=0..15)151PU14Port B pull-up bit y (y=0..15)141PU13Port B pull-up bit y (y=0..15)131PU12Port B pull-up bit y (y=0..15)121PU11Port B pull-up bit y (y=0..15)111PU10Port B pull-up bit y (y=0..15)101PU9Port B pull-up bit y (y=0..15)91PU8Port B pull-up bit y (y=0..15)81PU7Port B pull-up bit y (y=0..15)71PU6Port B pull-up bit y (y=0..15)61PU5Port B pull-up bit y (y=0..15)51PU4Port B pull-up bit y (y=0..15)41PU3Port B pull-up bit y (y=0..15)31PU2Port B pull-up bit y (y=0..15)21PU1Port B pull-up bit y (y=0..15)11PU0Port B pull-up bit y (y=0..15)01PDCRBPDCRBPower Port B pull-down control register0x2C0x20read-write0x00000000PD15Port B pull-down bit y (y=0..15)151PD14Port B pull-down bit y (y=0..15)141PD13Port B pull-down bit y (y=0..15)131PD12Port B pull-down bit y (y=0..15)121PD11Port B pull-down bit y (y=0..15)111PD10Port B pull-down bit y (y=0..15)101PD9Port B pull-down bit y (y=0..15)91PD8Port B pull-down bit y (y=0..15)81PD7Port B pull-down bit y (y=0..15)71PD6Port B pull-down bit y (y=0..15)61PD5Port B pull-down bit y (y=0..15)51PD3Port B pull-down bit y (y=0..15)31PD2Port B pull-down bit y (y=0..15)21PD1Port B pull-down bit y (y=0..15)11PD0Port B pull-down bit y (y=0..15)01PUCRCPUCRCPower Port C pull-up control register0x300x20read-write0x00000000PU15Port C pull-up bit y (y=0..15)151PU14Port C pull-up bit y (y=0..15)141PU13Port C pull-up bit y (y=0..15)131PU12Port C pull-up bit y (y=0..15)121PU11Port C pull-up bit y (y=0..15)111PU10Port C pull-up bit y (y=0..15)101PU9Port C pull-up bit y (y=0..15)91PU8Port C pull-up bit y (y=0..15)81PU7Port C pull-up bit y (y=0..15)71PU6Port C pull-up bit y (y=0..15)61PU5Port C pull-up bit y (y=0..15)51PU4Port C pull-up bit y (y=0..15)41PU3Port C pull-up bit y (y=0..15)31PU2Port C pull-up bit y (y=0..15)21PU1Port C pull-up bit y (y=0..15)11PU0Port C pull-up bit y (y=0..15)01PDCRCPDCRCPower Port C pull-down control register0x340x20read-write0x00000000PD15Port C pull-down bit y (y=0..15)151PD14Port C pull-down bit y (y=0..15)141PD13Port C pull-down bit y (y=0..15)131PD12Port C pull-down bit y (y=0..15)121PD11Port C pull-down bit y (y=0..15)111PD10Port C pull-down bit y (y=0..15)101PD9Port C pull-down bit y (y=0..15)91PD8Port C pull-down bit y (y=0..15)81PD7Port C pull-down bit y (y=0..15)71PD6Port C pull-down bit y (y=0..15)61PD5Port C pull-down bit y (y=0..15)51PD4Port C pull-down bit y (y=0..15)41PD3Port C pull-down bit y (y=0..15)31PD2Port C pull-down bit y (y=0..15)21PD1Port C pull-down bit y (y=0..15)11PD0Port C pull-down bit y (y=0..15)01PUCRDPUCRDPower Port D pull-up control register0x380x20read-write0x00000000PU15Port D pull-up bit y (y=0..15)151PU14Port D pull-up bit y (y=0..15)141PU13Port D pull-up bit y (y=0..15)131PU12Port D pull-up bit y (y=0..15)121PU11Port D pull-up bit y (y=0..15)111PU10Port D pull-up bit y (y=0..15)101PU9Port D pull-up bit y (y=0..15)91PU8Port D pull-up bit y (y=0..15)81PU7Port D pull-up bit y (y=0..15)71PU6Port D pull-up bit y (y=0..15)61PU5Port D pull-up bit y (y=0..15)51PU4Port D pull-up bit y (y=0..15)41PU3Port D pull-up bit y (y=0..15)31PU2Port D pull-up bit y (y=0..15)21PU1Port D pull-up bit y (y=0..15)11PU0Port D pull-up bit y (y=0..15)01PDCRDPDCRDPower Port D pull-down control register0x3C0x20read-write0x00000000PD15Port D pull-down bit y (y=0..15)151PD14Port D pull-down bit y (y=0..15)141PD13Port D pull-down bit y (y=0..15)131PD12Port D pull-down bit y (y=0..15)121PD11Port D pull-down bit y (y=0..15)111PD10Port D pull-down bit y (y=0..15)101PD9Port D pull-down bit y (y=0..15)91PD8Port D pull-down bit y (y=0..15)81PD7Port D pull-down bit y (y=0..15)71PD6Port D pull-down bit y (y=0..15)61PD5Port D pull-down bit y (y=0..15)51PD4Port D pull-down bit y (y=0..15)41PD3Port D pull-down bit y (y=0..15)31PD2Port D pull-down bit y (y=0..15)21PD1Port D pull-down bit y (y=0..15)11PD0Port D pull-down bit y (y=0..15)01PUCREPUCREPower Port E pull-up control register0x400x20read-write0x00000000PU4Port E pull-up bit y (y=0..15)41PU3Port E pull-up bit y (y=0..15)31PU2Port E pull-up bit y (y=0..15)21PU1Port E pull-up bit y (y=0..15)11PU0Port E pull-up bit y (y=0..15)01PDCREPDCREPower Port E pull-down control register0x440x20read-write0x00000000PD4Port E pull-down bit y (y=0..15)41PD3Port E pull-down bit y (y=0..15)31PD2Port E pull-down bit y (y=0..15)21PD1Port E pull-down bit y (y=0..15)11PD0Port E pull-down bit y (y=0..15)01PUCRHPUCRHPower Port H pull-up control register0x580x20read-write0x00000000PU3Port H pull-up bit y (y=0..1)31PU1Port H pull-up bit y (y=0..1)11PU0Port H pull-up bit y (y=0..1)01PDCRHPDCRHPower Port H pull-down control register0x5C0x20read-write0x00000000PD3Port H pull-down bit y (y=0..1)31PD1Port H pull-down bit y (y=0..1)11PD0Port H pull-down bit y (y=0..1)01C2CR1C2CR1CPU2 Power control register 10x800x20read-write0x00000000EWKUP802802.15.4 external wakeup signal151BLEEWKUPBLE external wakeup signal141FPDSFlash power down mode during LPSleep for CPU251FPDRFlash power down mode during LPRun for CPU241LPMSLow-power mode selection for CPU203C2CR3C2CR3CPU2 Power control register 30x840x20read-write0X00008000EIWULEnable internal wakeup line for CPU2151APCApply pull-up and pull-down configuration for CPU2121E802WUPEnable 802.15.4 host wakeup interrupt for CPU2101EBLEWUPEnable BLE host wakeup interrupt for CPU291EWUP5Enable Wakeup pin WKUP5 for CPU241EWUP4Enable Wakeup pin WKUP4 for CPU231EWUP3Enable Wakeup pin WKUP3 for CPU221EWUP2Enable Wakeup pin WKUP2 for CPU211EWUP1Enable Wakeup pin WKUP1 for CPU201EXTSCREXTSCRPower status clear register0x880x200x00000000C2DSCPU2 deepsleep mode151read-onlyC1DSCPU1 deepsleep mode141read-onlyCRPFCritical Radio system phase131read-onlyC2STOPFSystem Stop flag for CPU2111read-onlyC2SBFSystem Standby flag for CPU2101read-onlyC1STOPFSystem Stop flag for CPU191read-onlyC1SBFSystem Standby flag for CPU181read-onlyCCRPFClear Critical Radio system phase21write-onlyC2CSSFClear CPU2 Stop Standby flags11write-onlyC1CSSFClear CPU1 Stop Standby flags01write-onlySYSCFG_VREFBUFSYSCFG_VREFBUFSYSCFG_VREFBUF0x400100000x00x200registersSYSCFG_MEMRMPSYSCFG_MEMRMPmemory remap register0x00x20read-write0x00000000MEM_MODEMemory mapping selection03SYSCFG_CFGR1SYSCFG_CFGR1configuration register 10x40x20read-write0x7C000001FPU_IEFloating Point Unit interrupts enable bits266I2C3_FMPI2C3 Fast-mode Plus driving capability activation221I2C1_FMPI2C1 Fast-mode Plus driving capability activation201I2C_PB9_FMPFast-mode Plus (Fm+) driving capability activation on PB9191I2C_PB8_FMPFast-mode Plus (Fm+) driving capability activation on PB8181I2C_PB7_FMPFast-mode Plus (Fm+) driving capability activation on PB7171I2C_PB6_FMPFast-mode Plus (Fm+) driving capability activation on PB6161BOOSTENI/O analog switch voltage booster enable81SYSCFG_EXTICR1SYSCFG_EXTICR1external interrupt configuration register 10x80x20read-write0x00000000EXTI3EXTI 3 configuration bits123EXTI2EXTI 2 configuration bits83EXTI1EXTI 1 configuration bits43EXTI0EXTI 0 configuration bits03SYSCFG_EXTICR2SYSCFG_EXTICR2external interrupt configuration register 20xC0x20read-write0x00000000EXTI7EXTI 7 configuration bits123EXTI6EXTI 6 configuration bits83EXTI5EXTI 5 configuration bits43EXTI4EXTI 4 configuration bits03SYSCFG_EXTICR3SYSCFG_EXTICR3external interrupt configuration register 30x100x20read-write0x00000000EXTI11EXTI 11 configuration bits123EXTI10EXTI 10 configuration bits83EXTI9EXTI 9 configuration bits43EXTI8EXTI 8 configuration bits03SYSCFG_EXTICR4SYSCFG_EXTICR4external interrupt configuration register 40x140x20read-write0x00000000EXTI15EXTI15 configuration bits123EXTI14EXTI14 configuration bits83EXTI13EXTI13 configuration bits43EXTI12EXTI12 configuration bits03SYSCFG_SCSRSYSCFG_SCSRSCSR0x180x200x00000000SRAM2BSYSRAM2 busy by erase operation11read-onlySRAM2ERSRAM2 Erase01read-writeC2RFDCPU2 SRAM fetch (execution) disable.311read-writeSYSCFG_CFGR2SYSCFG_CFGR2CFGR20x1C0x200x00000000SPFSRAM2 parity error flag81read-writeECCLECC Lock31write-onlyPVDLPVD lock enable bit21write-onlySPLSRAM2 parity lock bit11write-onlyCLLCortex-M4 LOCKUP (Hardfault) output enable bit01write-onlySYSCFG_SWPRSYSCFG_SWPRSRAM2 write protection register0x200x20write-only0x00000000P31WPSRAM2 page 31 write protection311P30WPP30WP301P29WPP29WP291P28WPP28WP281P27WPP27WP271P26WPP26WP261P25WPP25WP251P24WPP24WP241P23WPP23WP231P22WPP22WP221P21WPP21WP211P20WPP20WP201P19WPP19WP191P18WPP18WP181P17WPP17WP171P16WPP16WP161P15WPP15WP151P14WPP14WP141P13WPP13WP131P12WPP12WP121P11WPP11WP111P10WPP10WP101P9WPP9WP91P8WPP8WP81P7WPP7WP71P6WPP6WP61P5WPP5WP51P4WPP4WP41P3WPP3WP31P2WPP2WP21P1WPP1WP11P0WPP0WP01SYSCFG_SKRSYSCFG_SKRSKR0x240x20write-only0x00000000KEYSRAM2 write protection key for software erase08SYSCFG_SWPR2SYSCFG_SWPR2SRAM2 write protection register 20x280x20write-only0x00000000P63WPSRAM2 page 63 write protection311P62WPP62WP301P61WPP61WP291P60WPP60WP281P59WPP59WP271P58WPP58WP261P57WPP57WP251P56WPP56WP241P55WPP55WP231P54WPP54WP221P53WPP53WP211P52WPP52WP201P51WPP51WP191P50WPP50WP181P49WPP49WP171P48WPP48WP161P47WPP47WP151P46WPP46WP141P45WPP45WP131P44WPP44WP121P43WPP43WP111P42WPP42WP101P41WPP41WP91P40WPP40WP81P39WPP39WP71P38WPP38WP61P37WPP37WP51P36WPP36WP41P35WPP35WP31P34WPP34WP21P33WPP33WP11P32WPP32WP01VREFBUF_CSRVREFBUF_CSRVREF control and status register0x300x200x00000002ENVRVoltage reference buffer enable01read-writeHIZHigh impedance mode11read-writeVRSVoltage reference scale21read-writeVRRVoltage reference buffer ready31read-onlyVREFBUF_CCRVREFBUF_CCRcalibration control register0x340x20read-write0x00000000TRIMTrimming code06SYSCFG_IMR1SYSCFG_IMR1CPU1 interrupt mask register 10x1000x20read-write0x00000000TIM1IMPeripheral TIM1 interrupt mask to CPU1131TIM16IMPeripheral TIM16 interrupt mask to CPU1141TIM17IMPeripheral TIM17 interrupt mask to CPU1151EXIT5IMPeripheral EXIT5 interrupt mask to CPU1211EXIT6IMPeripheral EXIT6 interrupt mask to CPU1221EXIT7IMPeripheral EXIT7 interrupt mask to CPU1231EXIT8IMPeripheral EXIT8 interrupt mask to CPU1241EXIT9IMPeripheral EXIT9 interrupt mask to CPU1251EXIT10IMPeripheral EXIT10 interrupt mask to CPU1261EXIT11IMPeripheral EXIT11 interrupt mask to CPU1271EXIT12IMPeripheral EXIT12 interrupt mask to CPU1281EXIT13IMPeripheral EXIT13 interrupt mask to CPU1291EXIT14IMPeripheral EXIT14 interrupt mask to CPU1301EXIT15IMPeripheral EXIT15 interrupt mask to CPU1311SYSCFG_IMR2SYSCFG_IMR2CPU1 interrupt mask register 20x1040x20read-write0x00000000PVM3IMPeripheral PVM3 interrupt mask to CPU1181PVM1IMPeripheral PVM1 interrupt mask to CPU1161PVDIMPeripheral PVD interrupt mask to CPU1201SYSCFG_C2IMR1SYSCFG_C2IMR1CPU2 interrupt mask register 10x1080x20read-write0x00000000RTCSTAMPPeripheral RTCSTAMP interrupt mask to CPU201RTCWKUPPeripheral RTCWKUP interrupt mask to CPU231RTCALARMPeripheral RTCALARM interrupt mask to CPU241RCCPeripheral RCC interrupt mask to CPU251FLASHPeripheral FLASH interrupt mask to CPU261PKAPeripheral PKA interrupt mask to CPU281RNGPeripheral RNG interrupt mask to CPU291AES1Peripheral AES1 interrupt mask to CPU2101COMPPeripheral COMP interrupt mask to CPU2111ADCPeripheral ADC interrupt mask to CPU2121SYSCFG_C2IMR2SYSCFG_C2IMR2CPU2 interrupt mask register 10x10C0x20read-write0x00000000DMA1_CH1_IMPeripheral DMA1 CH1 interrupt mask to CPU201DMA1_CH2_IMPeripheral DMA1 CH2 interrupt mask to CPU211DMA1_CH3_IMPeripheral DMA1 CH3 interrupt mask to CPU221DMA1_CH4_IMPeripheral DMA1 CH4 interrupt mask to CPU231DMA1_CH5_IMPeripheral DMA1 CH5 interrupt mask to CPU241DMA1_CH6_IMPeripheral DMA1 CH6 interrupt mask to CPU251DMA1_CH7_IMPeripheral DMA1 CH7 interrupt mask to CPU261DMA2_CH1_IMPeripheral DMA2 CH1 interrupt mask to CPU181DMA2_CH2_IMPeripheral DMA2 CH2 interrupt mask to CPU191DMA2_CH3_IMPeripheral DMA2 CH3 interrupt mask to CPU1101DMA2_CH4_IMPeripheral DMA2 CH4 interrupt mask to CPU1111DMA2_CH5_IMPeripheral DMA2 CH5 interrupt mask to CPU1121DMA2_CH6_IMPeripheral DMA2 CH6 interrupt mask to CPU1131DMA2_CH7_IMPeripheral DMA2 CH7 interrupt mask to CPU1141DMAM_UX1_IMPeripheral DMAM UX1 interrupt mask to CPU1151PVM1IMPeripheral PVM1IM interrupt mask to CPU1161PVM3IMPeripheral PVM3IM interrupt mask to CPU1181PVDIMPeripheral PVDIM interrupt mask to CPU1201TSCIMPeripheral TSCIM interrupt mask to CPU1211LCDIMPeripheral LCDIM interrupt mask to CPU1221SYSCFG_SIPCRSYSCFG_SIPCRsecure IP control register0x1100x20read-write0x00000000SAES1Enable AES1 KEY[7:0] security.01SAES2Enable AES2 security.11SPKAEnable PKA security21SRNGEnable True RNG security31COMPComparator instance 1COMP0x400102000x00x9registersCOMPCOMP2 & COMP1 interrupt through AIEC[21:20]22COMP1_CSRCOMP1_CSRComparator control and status register0x00x200x00000000COMP1_ENComparator enable01read-writeCOMP1_PWRMODEComparator power mode22read-writeCOMP1_INMSELComparator input minus selection43read-writeCOMP1_INPSELComparator input plus selection72read-writeCOMP1_POLARITYComparator output polarity151read-writeCOMP1_HYSTComparator hysteresis162read-writeCOMP1_BLANKINGComparator blanking source183read-writeCOMP1_BRGENComparator voltage scaler enable221read-writeCOMP1_SCALENComparator scaler bridge enable231read-writeCOMP1_INMESELComparator input minus extended selection252read-writeCOMP1_VALUEComparator output level301read-onlyCOMP1_LOCKComparator lock311read-writeCOMP2_CSRCOMP2_CSRComparator 2 control and status register0x40x200x00000000COMP2_ENComparator 2 enable bit01read-writeCOMP2_PWRMODEPower Mode of the comparator 222read-writeCOMP2_INMSELComparator 2 input minus selection bits42read-writeCOMP2_INPSELComparator 1 input plus selection bit72read-writeCOMP2_WINMODEWindows mode selection bit91read-writeCOMP2_POLARITYComparator 2 polarity selection bit151read-writeCOMP2_HYSTComparator 2 hysteresis selection bits162read-writeCOMP2_BLANKINGComparator 2 blanking source selection bits183read-writeCOMP2_BRGENScaler bridge enable221read-writeCOMP2_SCALENVoltage scaler enable bit231read-writeCOMP2_INMESELcomparator 2 input minus extended selection bits.252read-writeCOMP2_VALUEComparator 2 output status bit301read-onlyCOMP2_LOCKCSR register lock bit311read-writeRNGRandom number generatorRNG0x580010000x00x400registersTrue_RNGTrue random number generator interrupt53CRCRcontrol register0x00x20read-write0x00000000RNGENRandom number generator enable21IEInterrupt enable31BYPBypass mode enable61SRSRstatus register0x40x200x00000000SEISSeed error interrupt status61read-writeCEISClock error interrupt status51read-writeSECSSeed error current status21read-onlyCECSClock error current status11read-onlyDRDYData ready01read-onlyDRDRdata register0x80x20read-only0x00000000RNDATARandom data032AES1Advanced encryption standard hardware accelerator 1AES10x500600000x00x400registersAES1AES1 global interrupt51CRCRcontrol register0x00x20read-write0x00000000NPBLBNumber of padding bytes in last block of payload204KEYSIZEKey size selection181CHMOD2AES chaining mode Bit2161GCMPHUsed only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected132DMAOUTENEnable DMA management of data output phase121DMAINENEnable DMA management of data input phase111ERRIEError interrupt enable101CCFIECCF flag interrupt enable91ERRCError clear81CCFCComputation Complete Flag Clear71CHMOD10AES chaining mode Bit1 Bit052MODEAES operating mode32DATATYPEData type selection (for data in and data out to/from the cryptographic block)12ENAES enable01SRSRstatus register0x40x20read-only0x00000000BUSYBusy flag31WRERRWrite error flag21RDERRRead error flag11CCFComputation complete flag01DINRDINRdata input register0x80x20read-write0x00000000AES_DINRData Input Register032DOUTRDOUTRdata output register0xC0x20read-only0x00000000AES_DOUTRData output register032KEYR0KEYR0key register 00x100x20read-write0x00000000AES_KEYR0Data Output Register (LSB key [31:0])032KEYR1KEYR1key register 10x140x20read-write0x00000000AES_KEYR1AES key register (key [63:32])032KEYR2KEYR2key register 20x180x20read-write0x00000000AES_KEYR2AES key register (key [95:64])032KEYR3KEYR3key register 30x1C0x20read-write0x00000000AES_KEYR3AES key register (MSB key [127:96])032IVR0IVR0initialization vector register 00x200x20read-write0x00000000AES_IVR0initialization vector register (LSB IVR [31:0])032IVR1IVR1initialization vector register 10x240x20read-write0x00000000AES_IVR1Initialization Vector Register (IVR [63:32])032IVR2IVR2initialization vector register 20x280x20read-write0x00000000AES_IVR2Initialization Vector Register (IVR [95:64])032IVR3IVR3initialization vector register 30x2C0x20read-write0x00000000AES_IVR3Initialization Vector Register (MSB IVR [127:96])032KEYR4KEYR4key register 40x300x20read-write0x00000000AES_KEYR4AES key register (MSB key [159:128])032KEYR5KEYR5key register 50x340x20read-write0x00000000AES_KEYR5AES key register (MSB key [191:160])032KEYR6KEYR6key register 60x380x20read-write0x00000000AES_KEYR6AES key register (MSB key [223:192])032KEYR7KEYR7key register 70x3C0x20read-write0x00000000AES_KEYR7AES key register (MSB key [255:224])032SUSP0RSUSP0RAES suspend register 00x400x20read-write0x00000000AES_SUSP0RAES suspend register 0032SUSP1RSUSP1RAES suspend register 10x440x20read-write0x00000000AES_SUSP1RAES suspend register 1032SUSP2RSUSP2RAES suspend register 20x480x20read-write0x00000000AES_SUSP2RAES suspend register 2032SUSP3RSUSP3RAES suspend register 30x4C0x20read-write0x00000000AES_SUSP3RAES suspend register 3032SUSP4RSUSP4RAES suspend register 40x500x20read-write0x00000000AES_SUSP4RAES suspend register 4032SUSP5RSUSP5RAES suspend register 50x540x20read-write0x00000000AES_SUSP5RAES suspend register 5032SUSP6RSUSP6RAES suspend register 60x580x20read-write0x00000000AES_SUSP6RAES suspend register 6032SUSP7RSUSP7RAES suspend register 70x5C0x20read-write0x00000000AES_SUSP7RAES suspend register 7032HWCFRHWCFRAES hardware configuration register0x3F00x20read-only0x00000002CFG4HW Generic 4124CFG3HW Generic 384CFG2HW Generic 244CFG1HW Generic 104VERRVERRAES version register0x3F40x20read-only0x00000010MAJREVMajor revision44MINREVMinor revision04IPIDRIPIDRAES identification register0x3F80x20read-only0x00170023IDIdentification code032SIDRSIDRAES size ID register0x3FC0x20read-only0xA3C5DD01IDSize Identification code032AES2Advanced encryption standard hardware accelerator 1AES10x580018000x00x400registersAES2AES2 global interrupt52CRCRcontrol register0x00x20read-write0x00000000NPBLBNumber of padding bytes in last block of payload204KEYSIZEKey size selection181CHMOD2AES chaining mode Bit2161GCMPHUsed only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected132DMAOUTENEnable DMA management of data output phase121DMAINENEnable DMA management of data input phase111ERRIEError interrupt enable101CCFIECCF flag interrupt enable91ERRCError clear81CCFCComputation Complete Flag Clear71CHMOD10AES chaining mode Bit1 Bit052MODEAES operating mode32DATATYPEData type selection (for data in and data out to/from the cryptographic block)12ENAES enable01SRSRstatus register0x40x20read-only0x00000000BUSYBusy flag31WRERRWrite error flag21RDERRRead error flag11CCFComputation complete flag01DINRDINRdata input register0x80x20read-write0x00000000AES_DINRData Input Register032DOUTRDOUTRdata output register0xC0x20read-only0x00000000AES_DOUTRData output register032KEYR0KEYR0key register 00x100x20read-write0x00000000AES_KEYR0Data Output Register (LSB key [31:0])032KEYR1KEYR1key register 10x140x20read-write0x00000000AES_KEYR1AES key register (key [63:32])032KEYR2KEYR2key register 20x180x20read-write0x00000000AES_KEYR2AES key register (key [95:64])032KEYR3KEYR3key register 30x1C0x20read-write0x00000000AES_KEYR3AES key register (MSB key [127:96])032IVR0IVR0initialization vector register 00x200x20read-write0x00000000AES_IVR0initialization vector register (LSB IVR [31:0])032IVR1IVR1initialization vector register 10x240x20read-write0x00000000AES_IVR1Initialization Vector Register (IVR [63:32])032IVR2IVR2initialization vector register 20x280x20read-write0x00000000AES_IVR2Initialization Vector Register (IVR [95:64])032IVR3IVR3initialization vector register 30x2C0x20read-write0x00000000AES_IVR3Initialization Vector Register (MSB IVR [127:96])032KEYR4KEYR4key register 40x300x20read-write0x00000000AES_KEYR4AES key register (MSB key [159:128])032KEYR5KEYR5key register 50x340x20read-write0x00000000AES_KEYR5AES key register (MSB key [191:160])032KEYR6KEYR6key register 60x380x20read-write0x00000000AES_KEYR6AES key register (MSB key [223:192])032KEYR7KEYR7key register 70x3C0x20read-write0x00000000AES_KEYR7AES key register (MSB key [255:224])032SUSP0RSUSP0RAES suspend register 00x400x20read-write0x00000000AES_SUSP0RAES suspend register 0032SUSP1RSUSP1RAES suspend register 10x440x20read-write0x00000000AES_SUSP1RAES suspend register 1032SUSP2RSUSP2RAES suspend register 20x480x20read-write0x00000000AES_SUSP2RAES suspend register 2032SUSP3RSUSP3RAES suspend register 30x4C0x20read-write0x00000000AES_SUSP3RAES suspend register 3032SUSP4RSUSP4RAES suspend register 40x500x20read-write0x00000000AES_SUSP4RAES suspend register 4032SUSP5RSUSP5RAES suspend register 50x540x20read-write0x00000000AES_SUSP5RAES suspend register 5032SUSP6RSUSP6RAES suspend register 60x580x20read-write0x00000000AES_SUSP6RAES suspend register 6032SUSP7RSUSP7RAES suspend register 70x5C0x20read-write0x00000000AES_SUSP7RAES suspend register 7032HWCFRHWCFRAES hardware configuration register0x600x20read-only0x00000002CFG4HW Generic 4124CFG3HW Generic 384CFG2HW Generic 244CFG1HW Generic 104VERRVERRAES version register0x640x20read-only0x00000010MAJREVMajor revision44MINREVMinor revision04IPIDRIPIDRAES identification register0x680x20read-only0x00170023IDIdentification code032SIDRSIDRAES size ID register0x6C0x20read-only0x00170023IDSize Identification code032HSEMHSEMHardware_Semaphore0x580014000x00x400registersHSEMSemaphore interrupt 0 to CPU146R0R0Semaphore 0 register0x00x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R1R1Semaphore 1 register0x40x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R2R2Semaphore 2 register0x80x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R3R3Semaphore 3 register0xC0x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R4R4Semaphore 4 register0x100x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R5R5Semaphore 5 register0x140x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R6R6Semaphore 6 register0x180x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R7R7Semaphore 7 register0x1C0x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R8R8Semaphore 8 register0x200x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R9R9Semaphore 9 register0x240x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R10R10Semaphore 10 register0x280x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R11R11Semaphore 11 register0x2C0x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R12R12Semaphore 12 register0x300x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R13R13Semaphore 13 register0x340x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R14R14Semaphore 14 register0x380x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R15R15Semaphore 15 register0x3C0x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R16R16Semaphore 16 register0x400x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R17R17Semaphore 17 register0x440x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R18R18Semaphore 18 register0x480x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R19R19Semaphore 19 register0x4C0x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R20R20Semaphore 20 register0x500x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R21R21Semaphore 21 register0x540x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R22R22Semaphore 22 register0x580x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R23R23Semaphore 23 register0x5C0x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R24R24Semaphore 24 register0x600x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R25R25Semaphore 25 register0x640x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R26R26Semaphore 26 register0x680x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R27R27Semaphore 27 register0x6C0x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R28R28Semaphore 28 register0x700x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R29R29Semaphore 29 register0x740x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R30R30Semaphore 30 register0x780x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08R31R31Semaphore 31 register0x7C0x20read-write0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR0RLR0Semaphore 0 read lock register0x800x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR1RLR1Semaphore 1 read lock register0x840x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR2RLR2Semaphore 2 read lock register0x880x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR3RLR3Semaphore 3 read lock register0x8C0x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR4RLR4Semaphore 4 read lock read lock register0x900x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR5RLR5Semaphore 5 read lock register0x940x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR6RLR6Semaphore 6 read lock register0x980x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR7RLR7Semaphore 7 read lock register0x9C0x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR8RLR8Semaphore 8 read lock register0xA00x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR9RLR9Semaphore 9 read lock register0xA40x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR10RLR10Semaphore 10 read lock register0xA80x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR11RLR11Semaphore 11 read lock register0xAC0x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR12RLR12Semaphore 12 read lock register0xB00x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR13RLR13Semaphore 13 read lock register0xB40x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR14RLR14Semaphore 14 read lock register0xB80x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR15RLR15Semaphore 15 read lock register0xBC0x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR16RLR16Semaphore 16 read lock register0xC00x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR17RLR17Semaphore 17 read lock register0xC40x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR18RLR18Semaphore 18 read lock register0xC80x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR19RLR19Semaphore 19 read lock register0xCC0x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR20RLR20Semaphore 20 read lock register0xD00x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR21RLR21Semaphore 21 read lock register0xD40x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR22RLR22Semaphore 22 read lock register0xD80x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR23RLR23Semaphore 23 read lock register0xDC0x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR24RLR24Semaphore 24 read lock register0xE00x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR25RLR25Semaphore 25 read lock register0xE40x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR26RLR26Semaphore 26 read lock register0xE80x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR27RLR27Semaphore 27 read lock register0xEC0x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR28RLR28Semaphore 28 read lock register0xF00x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR29RLR29Semaphore 29 read lock register0xF40x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR30RLR30Semaphore 30 read lock register0xF80x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08RLR31RLR31Semaphore 31 read lock register0xFC0x20read-only0x00000000LOCKlock indication311COREIDSemaphore CoreID84PROCIDSemaphore ProcessID08CRCRSemaphore Clear register0x1400x20read-write0x00000000KEYSemaphore clear Key1616COREIDCoreID of semaphore to be cleared84KEYRKEYRInterrupt clear register0x1440x20read-write0x00000000KEYSemaphore Clear Key1616HWCFGR2HWCFGR2Semaphore hardware configuration register 20x3EC0x20read-only0x00000084MASTERID4Hardware Configuration valid bus masters ID4124MASTERID3Hardware Configuration valid bus masters ID384MASTERID2Hardware Configuration valid bus masters ID244MASTERID1Hardware Configuration valid bus masters ID104HWCFGR1HWCFGR1Semaphore hardware configuration register 10x3F00x20read-only0x00000220NBINTHardware Configuration number of interrupts supported number of master IDs84NBSEMHardware Configuration number of semaphores08VERRVERRHSEM version register0x3F40x20read-only0x00000020MAJREVMajor Revision44MINREVMinor Revision04IPIDRIPIDRHSEM indentification register0x3F80x20read-only0x00100072IDIdentification Code032SIDRSIDRHSEM size indentification register0x3FC0x20read-only0xA3C5DD01SIDSize Identification Code032C1IER0C1IER0HSEM Interrupt enable register0x1000x20read-write0x00000000ISEmCPU(n) semaphore m enable bit032C1ICRC1ICRHSEM Interrupt clear register0x1040x20read-write0x00000000ISCmCPU(n) semaphore m clear bit032C1ISRC1ISRHSEM Interrupt status register0x1080x20read-only0x00000000ISFmCPU(n) semaphore m status bit before enable (mask)032C1MISRC1MISRHSEM Masked interrupt status register0x10C0x20read-only0x00000000MISFmmasked CPU(n) semaphore m status bit after enable (mask).032C2IER0C2IER0HSEM Interrupt enable register0x1100x20read-write0x00000000ISEmCPU(2) semaphore m enable bit.032C2ICRC2ICRHSEM Interrupt clear register0x1140x20read-write0x00000000ISCmCPU(2) semaphore m clear bit032C2ISRC2ISRHSEM Interrupt status register0x1180x20read-only0x00000000ISFmCPU(2) semaphore m status bit before enable (mask).032C2MISRC2MISRHSEM Masked interrupt status register0x11C0x20read-only0x00000000MISFmmasked CPU(2) semaphore m status bit after enable (mask).032ADCAnalog to Digital Converter instance 1ADC0x500400000x00x400registersADC1ADC1 global interrupt18ISRISRADC interrupt and status register0x00x20read-write0x00000000JQOVFADC group injected contexts queue overflow flag101AWD3ADC analog watchdog 3 flag91AWD2ADC analog watchdog 2 flag81AWD1ADC analog watchdog 1 flag71JEOSADC group injected end of sequence conversions flag61JEOCADC group injected end of unitary conversion flag51OVRADC group regular overrun flag41EOSADC group regular end of sequence conversions flag31EOCADC group regular end of unitary conversion flag21EOSMPADC group regular end of sampling flag11ADRDYADC ready flag01IERIERADC interrupt enable register0x40x20read-write0x00000000JQOVFIEADC group injected contexts queue overflow interrupt101AWD3IEADC analog watchdog 3 interrupt91AWD2IEADC analog watchdog 2 interrupt81AWD1IEADC analog watchdog 1 interrupt71JEOSIEADC group injected end of sequence conversions interrupt61JEOCIEADC group injected end of unitary conversion interrupt51OVRIEADC group regular overrun interrupt41EOSIEADC group regular end of sequence conversions interrupt31EOCIEADC group regular end of unitary conversion interrupt21EOSMPIEADC group regular end of sampling interrupt11ADRDYIEADC ready interrupt01CRCRADC control register0x80x20read-write0x00000000ADCALADC calibration311ADCALDIFADC differential mode for calibration301DEEPPWDADC deep power down enable291ADVREGENADC voltage regulator enable281JADSTPADC group injected conversion stop51ADSTPADC group regular conversion stop41JADSTARTADC group injected conversion start31ADSTARTADC group regular conversion start21ADDISADC disable11ADENADC enable01CFGRCFGRADC configuration register 10xC0x20read-write0x80000000JQDISADC group injected contexts queue disable311AWDCH1CHADC analog watchdog 1 monitored channel selection265JAUTOADC group injected automatic trigger mode251JAWD1ENADC analog watchdog 1 enable on scope ADC group injected241AWD1ENADC analog watchdog 1 enable on scope ADC group regular231AWD1SGLADC analog watchdog 1 monitoring a single channel or all channels221JQMADC group injected contexts queue mode211JDISCENADC group injected sequencer discontinuous mode201DISCNUMADC group regular sequencer discontinuous number of ranks173DISCENADC group regular sequencer discontinuous mode161AUTDLYADC low power auto wait141CONTADC group regular continuous conversion mode131OVRMODADC group regular overrun configuration121EXTENADC group regular external trigger polarity102EXTSELADC group regular external trigger source64ALIGNADC data alignement51RESADC data resolution32DMACFGADC DMA transfer configuration11DMAENADC DMA transfer enable01CFGR2CFGR2ADC configuration register 20x100x20read-write0x00000000ROVSMADC oversampling mode managing interlaced conversions of ADC group regular and group injected101TOVSADC oversampling discontinuous mode (triggered mode) for ADC group regular91OVSSADC oversampling shift54OVSRADC oversampling ratio23JOVSEADC oversampler enable on scope ADC group injected11ROVSEADC oversampler enable on scope ADC group regular01SMPR1SMPR1ADC sampling time register 10x140x20read-write0x00000000SMP9ADC channel 9 sampling time selection273SMP8ADC channel 8 sampling time selection243SMP7ADC channel 7 sampling time selection213SMP6ADC channel 6 sampling time selection183SMP5ADC channel 5 sampling time selection153SMP4ADC channel 4 sampling time selection123SMP3ADC channel 3 sampling time selection93SMP2ADC channel 2 sampling time selection63SMP1ADC channel 1 sampling time selection33SMPR2SMPR2ADC sampling time register 20x180x20read-write0x00000000SMP18ADC channel 18 sampling time selection243SMP17ADC channel 17 sampling time selection213SMP16ADC channel 16 sampling time selection183SMP15ADC channel 15 sampling time selection153SMP14ADC channel 14 sampling time selection123SMP13ADC channel 13 sampling time selection93SMP12ADC channel 12 sampling time selection63SMP11ADC channel 11 sampling time selection33SMP10ADC channel 10 sampling time selection03TR1TR1ADC analog watchdog 1 threshold register0x200x20read-write0x0FFF0000HT1ADC analog watchdog 1 threshold high1612LT1ADC analog watchdog 1 threshold low012TR2TR2ADC analog watchdog 2 threshold register0x240x20read-write0x0FFF0000HT2ADC analog watchdog 2 threshold high168LT2ADC analog watchdog 2 threshold low08TR3TR3ADC analog watchdog 3 threshold register0x280x20read-write0x0FFF0000HT3ADC analog watchdog 3 threshold high168LT3ADC analog watchdog 3 threshold low08SQR1SQR1ADC group regular sequencer ranks register 10x300x20read-write0x00000000SQ4ADC group regular sequencer rank 4245SQ3ADC group regular sequencer rank 3185SQ2ADC group regular sequencer rank 2125SQ1ADC group regular sequencer rank 165L3L304SQR2SQR2ADC group regular sequencer ranks register 20x340x20read-write0x00000000SQ9ADC group regular sequencer rank 9245SQ8ADC group regular sequencer rank 8185SQ7ADC group regular sequencer rank 7125SQ6ADC group regular sequencer rank 665SQ5ADC group regular sequencer rank 505SQR3SQR3ADC group regular sequencer ranks register 30x380x20read-write0x00000000SQ14ADC group regular sequencer rank 14245SQ13ADC group regular sequencer rank 13185SQ12ADC group regular sequencer rank 12125SQ11ADC group regular sequencer rank 1165SQ10ADC group regular sequencer rank 1005SQR4SQR4ADC group regular sequencer ranks register 40x3C0x20read-write0x00000000SQ16ADC group regular sequencer rank 1665SQ15ADC group regular sequencer rank 1505DRDRADC group regular conversion data register0x400x200x00000000RDATA_0_6Regular Data converted 0_606read-writeRDATA_7_151579read-onlyJSQRJSQRADC group injected sequencer register0x4C0x20read-write0x00000000JSQ4ADC group injected sequencer rank 4265JSQ3ADC group injected sequencer rank 3205JSQ2ADC group injected sequencer rank 2145JSQ1ADC group injected sequencer rank 185JEXTENADC group injected external trigger polarity62JEXTSELADC group injected external trigger source24JLADC group injected sequencer scan length02OFR1OFR1ADC offset number 1 register0x600x20read-write0x00000000OFFSET1_ENADC offset number 1 enable311OFFSET1_CHADC offset number 1 channel selection265OFFSET1ADC offset number 1 offset level012OFR2OFR2ADC offset number 2 register0x640x20read-write0x00000000OFFSET2_ENADC offset number 2 enable311OFFSET2_CHADC offset number 2 channel selection265OFFSET2ADC offset number 2 offset level012OFR3OFR3ADC offset number 3 register0x680x20read-write0x00000000OFFSET3_ENADC offset number 3 enable311OFFSET3_CHADC offset number 3 channel selection265OFFSET3ADC offset number 3 offset level012OFR4OFR4ADC offset number 4 register0x6C0x20read-write0x00000000OFFSET4_ENADC offset number 4 enable311OFFSET4_CHADC offset number 4 channel selection265OFFSET4ADC offset number 4 offset level012JDR1JDR1ADC group injected sequencer rank 1 register0x800x20read-only0x00000000JDATA1ADC group injected sequencer rank 1 conversion data016JDR2JDR2ADC group injected sequencer rank 2 register0x840x20read-only0x00000000JDATA2ADC group injected sequencer rank 2 conversion data016JDR3JDR3ADC group injected sequencer rank 3 register0x880x20read-only0x00000000JDATA3ADC group injected sequencer rank 3 conversion data016JDR4JDR4ADC group injected sequencer rank 4 register0x8C0x20read-only0x00000000JDATA4ADC group injected sequencer rank 4 conversion data016AWD2CRAWD2CRADC analog watchdog 2 configuration register0xA00x20read-write0x00000000AWD2CHADC analog watchdog 2 monitored channel selection019AWD3CRAWD3CRADC analog watchdog 3 configuration register0xA40x20read-write0x00000000AWD3CHADC analog watchdog 3 monitored channel selection019DIFSELDIFSELADC channel differential or single-ended mode selection register0xB00x200x00000000DIFSEL_0ADC channel differential or single-ended mode for channel 001read-onlyDIFSEL_1_15ADC channel differential or single-ended mode for channels 1 to 15115read-writeDIFSEL_16_18ADC channel differential or single-ended mode for channels 18 to 16163read-onlyCALFACTCALFACTADC calibration factors register0xB40x20read-write0x00000000CALFACT_DADC calibration factor in differential mode167CALFACT_SADC calibration factor in single-ended mode07CCRCCRADC common control register0x3080x20read-write0x00000000VBATENVBAT enable241TSENTemperature sensor enable231VREFENVREFEN221PRESCADC prescaler184CKMODEADC clock mode162GPIOAGeneral-purpose I/OsGPIO0x480000000x00x400registersMODERMODERGPIO port mode register0x00x20read-write0xABFFFFFFMODER15Port x configuration bits (y = 0..15)302MODER14Port x configuration bits (y = 0..15)282MODER13Port x configuration bits (y = 0..15)262MODER12Port x configuration bits (y = 0..15)242MODER11Port x configuration bits (y = 0..15)222MODER10Port x configuration bits (y = 0..15)202MODER9Port x configuration bits (y = 0..15)182MODER8Port x configuration bits (y = 0..15)162MODER7Port x configuration bits (y = 0..15)142MODER6Port x configuration bits (y = 0..15)122MODER5Port x configuration bits (y = 0..15)102MODER4Port x configuration bits (y = 0..15)82MODER3Port x configuration bits (y = 0..15)62MODER2Port x configuration bits (y = 0..15)42MODER1Port x configuration bits (y = 0..15)22MODER0Port x configuration bits (y = 0..15)02OTYPEROTYPERGPIO port output type register0x40x20read-write0x00000000OT15Port x configuration bits (y = 0..15)151OT14Port x configuration bits (y = 0..15)141OT13Port x configuration bits (y = 0..15)131OT12Port x configuration bits (y = 0..15)121OT11Port x configuration bits (y = 0..15)111OT10Port x configuration bits (y = 0..15)101OT9Port x configuration bits (y = 0..15)91OT8Port x configuration bits (y = 0..15)81OT7Port x configuration bits (y = 0..15)71OT6Port x configuration bits (y = 0..15)61OT5Port x configuration bits (y = 0..15)51OT4Port x configuration bits (y = 0..15)41OT3Port x configuration bits (y = 0..15)31OT2Port x configuration bits (y = 0..15)21OT1Port x configuration bits (y = 0..15)11OT0Port x configuration bits (y = 0..15)01OSPEEDROSPEEDRGPIO port output speed register0x80x20read-write0x0C000000OSPEEDR15Port x configuration bits (y = 0..15)302OSPEEDR14Port x configuration bits (y = 0..15)282OSPEEDR13Port x configuration bits (y = 0..15)262OSPEEDR12Port x configuration bits (y = 0..15)242OSPEEDR11Port x configuration bits (y = 0..15)222OSPEEDR10Port x configuration bits (y = 0..15)202OSPEEDR9Port x configuration bits (y = 0..15)182OSPEEDR8Port x configuration bits (y = 0..15)162OSPEEDR7Port x configuration bits (y = 0..15)142OSPEEDR6Port x configuration bits (y = 0..15)122OSPEEDR5Port x configuration bits (y = 0..15)102OSPEEDR4Port x configuration bits (y = 0..15)82OSPEEDR3Port x configuration bits (y = 0..15)62OSPEEDR2Port x configuration bits (y = 0..15)42OSPEEDR1Port x configuration bits (y = 0..15)22OSPEEDR0Port x configuration bits (y = 0..15)02PUPDRPUPDRGPIO port pull-up/pull-down register0xC0x20read-write0x64000000PUPDR15Port x configuration bits (y = 0..15)302PUPDR14Port x configuration bits (y = 0..15)282PUPDR13Port x configuration bits (y = 0..15)262PUPDR12Port x configuration bits (y = 0..15)242PUPDR11Port x configuration bits (y = 0..15)222PUPDR10Port x configuration bits (y = 0..15)202PUPDR9Port x configuration bits (y = 0..15)182PUPDR8Port x configuration bits (y = 0..15)162PUPDR7Port x configuration bits (y = 0..15)142PUPDR6Port x configuration bits (y = 0..15)122PUPDR5Port x configuration bits (y = 0..15)102PUPDR4Port x configuration bits (y = 0..15)82PUPDR3Port x configuration bits (y = 0..15)62PUPDR2Port x configuration bits (y = 0..15)42PUPDR1Port x configuration bits (y = 0..15)22PUPDR0Port x configuration bits (y = 0..15)02IDRIDRGPIO port input data register0x100x20read-only0x00000000IDR15Port input data (y = 0..15)151IDR14Port input data (y = 0..15)141IDR13Port input data (y = 0..15)131IDR12Port input data (y = 0..15)121IDR11Port input data (y = 0..15)111IDR10Port input data (y = 0..15)101IDR9Port input data (y = 0..15)91IDR8Port input data (y = 0..15)81IDR7Port input data (y = 0..15)71IDR6Port input data (y = 0..15)61IDR5Port input data (y = 0..15)51IDR4Port input data (y = 0..15)41IDR3Port input data (y = 0..15)31IDR2Port input data (y = 0..15)21IDR1Port input data (y = 0..15)11IDR0Port input data (y = 0..15)01ODRODRGPIO port output data register0x140x20read-write0x00000000ODR15Port output data (y = 0..15)151ODR14Port output data (y = 0..15)141ODR13Port output data (y = 0..15)131ODR12Port output data (y = 0..15)121ODR11Port output data (y = 0..15)111ODR10Port output data (y = 0..15)101ODR9Port output data (y = 0..15)91ODR8Port output data (y = 0..15)81ODR7Port output data (y = 0..15)71ODR6Port output data (y = 0..15)61ODR5Port output data (y = 0..15)51ODR4Port output data (y = 0..15)41ODR3Port output data (y = 0..15)31ODR2Port output data (y = 0..15)21ODR1Port output data (y = 0..15)11ODR0Port output data (y = 0..15)01BSRRBSRRGPIO port bit set/reset register0x180x20write-only0x00000000BR15Port x reset bit y (y = 0..15)311BR14Port x reset bit y (y = 0..15)301BR13Port x reset bit y (y = 0..15)291BR12Port x reset bit y (y = 0..15)281BR11Port x reset bit y (y = 0..15)271BR10Port x reset bit y (y = 0..15)261BR9Port x reset bit y (y = 0..15)251BR8Port x reset bit y (y = 0..15)241BR7Port x reset bit y (y = 0..15)231BR6Port x reset bit y (y = 0..15)221BR5Port x reset bit y (y = 0..15)211BR4Port x reset bit y (y = 0..15)201BR3Port x reset bit y (y = 0..15)191BR2Port x reset bit y (y = 0..15)181BR1Port x reset bit y (y = 0..15)171BR0Port x set bit y (y= 0..15)161BS15Port x set bit y (y= 0..15)151BS14Port x set bit y (y= 0..15)141BS13Port x set bit y (y= 0..15)131BS12Port x set bit y (y= 0..15)121BS11Port x set bit y (y= 0..15)111BS10Port x set bit y (y= 0..15)101BS9Port x set bit y (y= 0..15)91BS8Port x set bit y (y= 0..15)81BS7Port x set bit y (y= 0..15)71BS6Port x set bit y (y= 0..15)61BS5Port x set bit y (y= 0..15)51BS4Port x set bit y (y= 0..15)41BS3Port x set bit y (y= 0..15)31BS2Port x set bit y (y= 0..15)21BS1Port x set bit y (y= 0..15)11BS0Port x set bit y (y= 0..15)01LCKRLCKRGPIO port configuration lock register0x1C0x20read-write0x00000000LCKKPort x lock bit y (y= 0..15)161LCK15Port x lock bit y (y= 0..15)151LCK14Port x lock bit y (y= 0..15)141LCK13Port x lock bit y (y= 0..15)131LCK12Port x lock bit y (y= 0..15)121LCK11Port x lock bit y (y= 0..15)111LCK10Port x lock bit y (y= 0..15)101LCK9Port x lock bit y (y= 0..15)91LCK8Port x lock bit y (y= 0..15)81LCK7Port x lock bit y (y= 0..15)71LCK6Port x lock bit y (y= 0..15)61LCK5Port x lock bit y (y= 0..15)51LCK4Port x lock bit y (y= 0..15)41LCK3Port x lock bit y (y= 0..15)31LCK2Port x lock bit y (y= 0..15)21LCK1Port x lock bit y (y= 0..15)11LCK0Port x lock bit y (y= 0..15)01AFRLAFRLGPIO alternate function low register0x200x20read-write0x00000000AFSEL7Alternate function selection for port x bit y (y = 0..7)284AFSEL6Alternate function selection for port x bit y (y = 0..7)244AFSEL5Alternate function selection for port x bit y (y = 0..7)204AFSEL4Alternate function selection for port x bit y (y = 0..7)164AFSEL3Alternate function selection for port x bit y (y = 0..7)124AFSEL2Alternate function selection for port x bit y (y = 0..7)84AFSEL1Alternate function selection for port x bit y (y = 0..7)44AFSEL0Alternate function selection for port x bit y (y = 0..7)04AFRHAFRHGPIO alternate function high register0x240x20read-write0x00000000AFSEL15Alternate function selection for port x bit y (y = 8..15)284AFSEL14Alternate function selection for port x bit y (y = 8..15)244AFSEL13Alternate function selection for port x bit y (y = 8..15)204AFSEL12Alternate function selection for port x bit y (y = 8..15)164AFSEL11Alternate function selection for port x bit y (y = 8..15)124AFSEL10Alternate function selection for port x bit y (y = 8..15)84AFSEL9Alternate function selection for port x bit y (y = 8..15)44AFSEL8Alternate function selection for port x bit y (y = 8..15)04BRRBRRport bit reset register0x280x20write-only0x00000000BR0Port Reset bit01BR1Port Reset bit11BR2Port Reset bit21BR3Port Reset bit31BR4Port Reset bit41BR5Port Reset bit51BR6Port Reset bit61BR7Port Reset bit71BR8Port Reset bit81BR9Port Reset bit91BR10Port Reset bit101BR11Port Reset bit111BR12Port Reset bit121BR13Port Reset bit131BR14Port Reset bit141BR15Port Reset bit151GPIOBGeneral-purpose I/OsGPIO0x480004000x00x400registersMODERMODERGPIO port mode register0x00x20read-write0xFFFFFEBFMODER15Port x configuration bits (y = 0..15)302MODER14Port x configuration bits (y = 0..15)282MODER13Port x configuration bits (y = 0..15)262MODER12Port x configuration bits (y = 0..15)242MODER11Port x configuration bits (y = 0..15)222MODER10Port x configuration bits (y = 0..15)202MODER9Port x configuration bits (y = 0..15)182MODER8Port x configuration bits (y = 0..15)162MODER7Port x configuration bits (y = 0..15)142MODER6Port x configuration bits (y = 0..15)122MODER5Port x configuration bits (y = 0..15)102MODER4Port x configuration bits (y = 0..15)82MODER3Port x configuration bits (y = 0..15)62MODER2Port x configuration bits (y = 0..15)42MODER1Port x configuration bits (y = 0..15)22MODER0Port x configuration bits (y = 0..15)02OTYPEROTYPERGPIO port output type register0x40x20read-write0x00000000OT15Port x configuration bits (y = 0..15)151OT14Port x configuration bits (y = 0..15)141OT13Port x configuration bits (y = 0..15)131OT12Port x configuration bits (y = 0..15)121OT11Port x configuration bits (y = 0..15)111OT10Port x configuration bits (y = 0..15)101OT9Port x configuration bits (y = 0..15)91OT8Port x configuration bits (y = 0..15)81OT7Port x configuration bits (y = 0..15)71OT6Port x configuration bits (y = 0..15)61OT5Port x configuration bits (y = 0..15)51OT4Port x configuration bits (y = 0..15)41OT3Port x configuration bits (y = 0..15)31OT2Port x configuration bits (y = 0..15)21OT1Port x configuration bits (y = 0..15)11OT0Port x configuration bits (y = 0..15)01OSPEEDROSPEEDRGPIO port output speed register0x80x20read-write0x000000C0OSPEEDR15Port x configuration bits (y = 0..15)302OSPEEDR14Port x configuration bits (y = 0..15)282OSPEEDR13Port x configuration bits (y = 0..15)262OSPEEDR12Port x configuration bits (y = 0..15)242OSPEEDR11Port x configuration bits (y = 0..15)222OSPEEDR10Port x configuration bits (y = 0..15)202OSPEEDR9Port x configuration bits (y = 0..15)182OSPEEDR8Port x configuration bits (y = 0..15)162OSPEEDR7Port x configuration bits (y = 0..15)142OSPEEDR6Port x configuration bits (y = 0..15)122OSPEEDR5Port x configuration bits (y = 0..15)102OSPEEDR4Port x configuration bits (y = 0..15)82OSPEEDR3Port x configuration bits (y = 0..15)62OSPEEDR2Port x configuration bits (y = 0..15)42OSPEEDR1Port x configuration bits (y = 0..15)22OSPEEDR0Port x configuration bits (y = 0..15)02PUPDRPUPDRGPIO port pull-up/pull-down register0xC0x20read-write0x00000100PUPDR15Port x configuration bits (y = 0..15)302PUPDR14Port x configuration bits (y = 0..15)282PUPDR13Port x configuration bits (y = 0..15)262PUPDR12Port x configuration bits (y = 0..15)242PUPDR11Port x configuration bits (y = 0..15)222PUPDR10Port x configuration bits (y = 0..15)202PUPDR9Port x configuration bits (y = 0..15)182PUPDR8Port x configuration bits (y = 0..15)162PUPDR7Port x configuration bits (y = 0..15)142PUPDR6Port x configuration bits (y = 0..15)122PUPDR5Port x configuration bits (y = 0..15)102PUPDR4Port x configuration bits (y = 0..15)82PUPDR3Port x configuration bits (y = 0..15)62PUPDR2Port x configuration bits (y = 0..15)42PUPDR1Port x configuration bits (y = 0..15)22PUPDR0Port x configuration bits (y = 0..15)02IDRIDRGPIO port input data register0x100x20read-only0x00000000IDR15Port input data (y = 0..15)151IDR14Port input data (y = 0..15)141IDR13Port input data (y = 0..15)131IDR12Port input data (y = 0..15)121IDR11Port input data (y = 0..15)111IDR10Port input data (y = 0..15)101IDR9Port input data (y = 0..15)91IDR8Port input data (y = 0..15)81IDR7Port input data (y = 0..15)71IDR6Port input data (y = 0..15)61IDR5Port input data (y = 0..15)51IDR4Port input data (y = 0..15)41IDR3Port input data (y = 0..15)31IDR2Port input data (y = 0..15)21IDR1Port input data (y = 0..15)11IDR0Port input data (y = 0..15)01ODRODRGPIO port output data register0x140x20read-write0x00000000ODR15Port output data (y = 0..15)151ODR14Port output data (y = 0..15)141ODR13Port output data (y = 0..15)131ODR12Port output data (y = 0..15)121ODR11Port output data (y = 0..15)111ODR10Port output data (y = 0..15)101ODR9Port output data (y = 0..15)91ODR8Port output data (y = 0..15)81ODR7Port output data (y = 0..15)71ODR6Port output data (y = 0..15)61ODR5Port output data (y = 0..15)51ODR4Port output data (y = 0..15)41ODR3Port output data (y = 0..15)31ODR2Port output data (y = 0..15)21ODR1Port output data (y = 0..15)11ODR0Port output data (y = 0..15)01BSRRBSRRGPIO port bit set/reset register0x180x20write-only0x00000000BR15Port x reset bit y (y = 0..15)311BR14Port x reset bit y (y = 0..15)301BR13Port x reset bit y (y = 0..15)291BR12Port x reset bit y (y = 0..15)281BR11Port x reset bit y (y = 0..15)271BR10Port x reset bit y (y = 0..15)261BR9Port x reset bit y (y = 0..15)251BR8Port x reset bit y (y = 0..15)241BR7Port x reset bit y (y = 0..15)231BR6Port x reset bit y (y = 0..15)221BR5Port x reset bit y (y = 0..15)211BR4Port x reset bit y (y = 0..15)201BR3Port x reset bit y (y = 0..15)191BR2Port x reset bit y (y = 0..15)181BR1Port x reset bit y (y = 0..15)171BR0Port x set bit y (y= 0..15)161BS15Port x set bit y (y= 0..15)151BS14Port x set bit y (y= 0..15)141BS13Port x set bit y (y= 0..15)131BS12Port x set bit y (y= 0..15)121BS11Port x set bit y (y= 0..15)111BS10Port x set bit y (y= 0..15)101BS9Port x set bit y (y= 0..15)91BS8Port x set bit y (y= 0..15)81BS7Port x set bit y (y= 0..15)71BS6Port x set bit y (y= 0..15)61BS5Port x set bit y (y= 0..15)51BS4Port x set bit y (y= 0..15)41BS3Port x set bit y (y= 0..15)31BS2Port x set bit y (y= 0..15)21BS1Port x set bit y (y= 0..15)11BS0Port x set bit y (y= 0..15)01LCKRLCKRGPIO port configuration lock register0x1C0x20read-write0x00000000LCKKPort x lock bit y (y= 0..15)161LCK15Port x lock bit y (y= 0..15)151LCK14Port x lock bit y (y= 0..15)141LCK13Port x lock bit y (y= 0..15)131LCK12Port x lock bit y (y= 0..15)121LCK11Port x lock bit y (y= 0..15)111LCK10Port x lock bit y (y= 0..15)101LCK9Port x lock bit y (y= 0..15)91LCK8Port x lock bit y (y= 0..15)81LCK7Port x lock bit y (y= 0..15)71LCK6Port x lock bit y (y= 0..15)61LCK5Port x lock bit y (y= 0..15)51LCK4Port x lock bit y (y= 0..15)41LCK3Port x lock bit y (y= 0..15)31LCK2Port x lock bit y (y= 0..15)21LCK1Port x lock bit y (y= 0..15)11LCK0Port x lock bit y (y= 0..15)01AFRLAFRLGPIO alternate function low register0x200x20read-write0x00000000AFSEL7Alternate function selection for port x bit y (y = 0..7)284AFSEL6Alternate function selection for port x bit y (y = 0..7)244AFSEL5Alternate function selection for port x bit y (y = 0..7)204AFSEL4Alternate function selection for port x bit y (y = 0..7)164AFSEL3Alternate function selection for port x bit y (y = 0..7)124AFSEL2Alternate function selection for port x bit y (y = 0..7)84AFSEL1Alternate function selection for port x bit y (y = 0..7)44AFSEL0Alternate function selection for port x bit y (y = 0..7)04AFRHAFRHGPIO alternate function high register0x240x20read-write0x00000000AFSEL15Alternate function selection for port x bit y (y = 8..15)284AFSEL14Alternate function selection for port x bit y (y = 8..15)244AFSEL13Alternate function selection for port x bit y (y = 8..15)204AFSEL12Alternate function selection for port x bit y (y = 8..15)164AFSEL11Alternate function selection for port x bit y (y = 8..15)124AFSEL10Alternate function selection for port x bit y (y = 8..15)84AFSEL9Alternate function selection for port x bit y (y = 8..15)44AFSEL8Alternate function selection for port x bit y (y = 8..15)04BRRBRRport bit reset register0x280x20write-only0x00000000BR0Port Reset bit01BR1Port Reset bit11BR2Port Reset bit21BR3Port Reset bit31BR4Port Reset bit41BR5Port Reset bit51BR6Port Reset bit61BR7Port Reset bit71BR8Port Reset bit81BR9Port Reset bit91BR10Port Reset bit101BR11Port Reset bit111BR12Port Reset bit121BR13Port Reset bit131BR14Port Reset bit141BR15Port Reset bit151GPIOCGeneral-purpose I/OsGPIO0x480008000x00x400registersMODERMODERGPIO port mode register0x00x20read-write0xFFFFFFFFMODER15Port x configuration bits (y = 0..15)302MODER14Port x configuration bits (y = 0..15)282MODER13Port x configuration bits (y = 0..15)262MODER12Port x configuration bits (y = 0..15)242MODER11Port x configuration bits (y = 0..15)222MODER10Port x configuration bits (y = 0..15)202MODER9Port x configuration bits (y = 0..15)182MODER8Port x configuration bits (y = 0..15)162MODER7Port x configuration bits (y = 0..15)142MODER6Port x configuration bits (y = 0..15)122MODER5Port x configuration bits (y = 0..15)102MODER4Port x configuration bits (y = 0..15)82MODER3Port x configuration bits (y = 0..15)62MODER2Port x configuration bits (y = 0..15)42MODER1Port x configuration bits (y = 0..15)22MODER0Port x configuration bits (y = 0..15)02OTYPEROTYPERGPIO port output type register0x40x20read-write0x00000000OT15Port x configuration bits (y = 0..15)151OT14Port x configuration bits (y = 0..15)141OT13Port x configuration bits (y = 0..15)131OT12Port x configuration bits (y = 0..15)121OT11Port x configuration bits (y = 0..15)111OT10Port x configuration bits (y = 0..15)101OT9Port x configuration bits (y = 0..15)91OT8Port x configuration bits (y = 0..15)81OT7Port x configuration bits (y = 0..15)71OT6Port x configuration bits (y = 0..15)61OT5Port x configuration bits (y = 0..15)51OT4Port x configuration bits (y = 0..15)41OT3Port x configuration bits (y = 0..15)31OT2Port x configuration bits (y = 0..15)21OT1Port x configuration bits (y = 0..15)11OT0Port x configuration bits (y = 0..15)01OSPEEDROSPEEDRGPIO port output speed register0x80x20read-write0x000000C0OSPEEDR15Port x configuration bits (y = 0..15)302OSPEEDR14Port x configuration bits (y = 0..15)282OSPEEDR13Port x configuration bits (y = 0..15)262OSPEEDR12Port x configuration bits (y = 0..15)242OSPEEDR11Port x configuration bits (y = 0..15)222OSPEEDR10Port x configuration bits (y = 0..15)202OSPEEDR9Port x configuration bits (y = 0..15)182OSPEEDR8Port x configuration bits (y = 0..15)162OSPEEDR7Port x configuration bits (y = 0..15)142OSPEEDR6Port x configuration bits (y = 0..15)122OSPEEDR5Port x configuration bits (y = 0..15)102OSPEEDR4Port x configuration bits (y = 0..15)82OSPEEDR3Port x configuration bits (y = 0..15)62OSPEEDR2Port x configuration bits (y = 0..15)42OSPEEDR1Port x configuration bits (y = 0..15)22OSPEEDR0Port x configuration bits (y = 0..15)02PUPDRPUPDRGPIO port pull-up/pull-down register0xC0x20read-write0x00000100PUPDR15Port x configuration bits (y = 0..15)302PUPDR14Port x configuration bits (y = 0..15)282PUPDR13Port x configuration bits (y = 0..15)262PUPDR12Port x configuration bits (y = 0..15)242PUPDR11Port x configuration bits (y = 0..15)222PUPDR10Port x configuration bits (y = 0..15)202PUPDR9Port x configuration bits (y = 0..15)182PUPDR8Port x configuration bits (y = 0..15)162PUPDR7Port x configuration bits (y = 0..15)142PUPDR6Port x configuration bits (y = 0..15)122PUPDR5Port x configuration bits (y = 0..15)102PUPDR4Port x configuration bits (y = 0..15)82PUPDR3Port x configuration bits (y = 0..15)62PUPDR2Port x configuration bits (y = 0..15)42PUPDR1Port x configuration bits (y = 0..15)22PUPDR0Port x configuration bits (y = 0..15)02IDRIDRGPIO port input data register0x100x20read-only0x00000000IDR15Port input data (y = 0..15)151IDR14Port input data (y = 0..15)141IDR13Port input data (y = 0..15)131IDR12Port input data (y = 0..15)121IDR11Port input data (y = 0..15)111IDR10Port input data (y = 0..15)101IDR9Port input data (y = 0..15)91IDR8Port input data (y = 0..15)81IDR7Port input data (y = 0..15)71IDR6Port input data (y = 0..15)61IDR5Port input data (y = 0..15)51IDR4Port input data (y = 0..15)41IDR3Port input data (y = 0..15)31IDR2Port input data (y = 0..15)21IDR1Port input data (y = 0..15)11IDR0Port input data (y = 0..15)01ODRODRGPIO port output data register0x140x20read-write0x00000000ODR15Port output data (y = 0..15)151ODR14Port output data (y = 0..15)141ODR13Port output data (y = 0..15)131ODR12Port output data (y = 0..15)121ODR11Port output data (y = 0..15)111ODR10Port output data (y = 0..15)101ODR9Port output data (y = 0..15)91ODR8Port output data (y = 0..15)81ODR7Port output data (y = 0..15)71ODR6Port output data (y = 0..15)61ODR5Port output data (y = 0..15)51ODR4Port output data (y = 0..15)41ODR3Port output data (y = 0..15)31ODR2Port output data (y = 0..15)21ODR1Port output data (y = 0..15)11ODR0Port output data (y = 0..15)01BSRRBSRRGPIO port bit set/reset register0x180x20write-only0x00000000BR15Port x reset bit y (y = 0..15)311BR14Port x reset bit y (y = 0..15)301BR13Port x reset bit y (y = 0..15)291BR12Port x reset bit y (y = 0..15)281BR11Port x reset bit y (y = 0..15)271BR10Port x reset bit y (y = 0..15)261BR9Port x reset bit y (y = 0..15)251BR8Port x reset bit y (y = 0..15)241BR7Port x reset bit y (y = 0..15)231BR6Port x reset bit y (y = 0..15)221BR5Port x reset bit y (y = 0..15)211BR4Port x reset bit y (y = 0..15)201BR3Port x reset bit y (y = 0..15)191BR2Port x reset bit y (y = 0..15)181BR1Port x reset bit y (y = 0..15)171BR0Port x set bit y (y= 0..15)161BS15Port x set bit y (y= 0..15)151BS14Port x set bit y (y= 0..15)141BS13Port x set bit y (y= 0..15)131BS12Port x set bit y (y= 0..15)121BS11Port x set bit y (y= 0..15)111BS10Port x set bit y (y= 0..15)101BS9Port x set bit y (y= 0..15)91BS8Port x set bit y (y= 0..15)81BS7Port x set bit y (y= 0..15)71BS6Port x set bit y (y= 0..15)61BS5Port x set bit y (y= 0..15)51BS4Port x set bit y (y= 0..15)41BS3Port x set bit y (y= 0..15)31BS2Port x set bit y (y= 0..15)21BS1Port x set bit y (y= 0..15)11BS0Port x set bit y (y= 0..15)01LCKRLCKRGPIO port configuration lock register0x1C0x20read-write0x00000000LCKKPort x lock bit y (y= 0..15)161LCK15Port x lock bit y (y= 0..15)151LCK14Port x lock bit y (y= 0..15)141LCK13Port x lock bit y (y= 0..15)131LCK12Port x lock bit y (y= 0..15)121LCK11Port x lock bit y (y= 0..15)111LCK10Port x lock bit y (y= 0..15)101LCK9Port x lock bit y (y= 0..15)91LCK8Port x lock bit y (y= 0..15)81LCK7Port x lock bit y (y= 0..15)71LCK6Port x lock bit y (y= 0..15)61LCK5Port x lock bit y (y= 0..15)51LCK4Port x lock bit y (y= 0..15)41LCK3Port x lock bit y (y= 0..15)31LCK2Port x lock bit y (y= 0..15)21LCK1Port x lock bit y (y= 0..15)11LCK0Port x lock bit y (y= 0..15)01AFRLAFRLGPIO alternate function low register0x200x20read-write0x00000000AFSEL7Alternate function selection for port x bit y (y = 0..7)284AFSEL6Alternate function selection for port x bit y (y = 0..7)244AFSEL5Alternate function selection for port x bit y (y = 0..7)204AFSEL4Alternate function selection for port x bit y (y = 0..7)164AFSEL3Alternate function selection for port x bit y (y = 0..7)124AFSEL2Alternate function selection for port x bit y (y = 0..7)84AFSEL1Alternate function selection for port x bit y (y = 0..7)44AFSEL0Alternate function selection for port x bit y (y = 0..7)04AFRHAFRHGPIO alternate function high register0x240x20read-write0x00000000AFSEL15Alternate function selection for port x bit y (y = 8..15)284AFSEL14Alternate function selection for port x bit y (y = 8..15)244AFSEL13Alternate function selection for port x bit y (y = 8..15)204AFSEL12Alternate function selection for port x bit y (y = 8..15)164AFSEL11Alternate function selection for port x bit y (y = 8..15)124AFSEL10Alternate function selection for port x bit y (y = 8..15)84AFSEL9Alternate function selection for port x bit y (y = 8..15)44AFSEL8Alternate function selection for port x bit y (y = 8..15)04BRRBRRport bit reset register0x280x20write-only0x00000000BR0Port Reset bit01BR1Port Reset bit11BR2Port Reset bit21BR3Port Reset bit31BR4Port Reset bit41BR5Port Reset bit51BR6Port Reset bit61BR7Port Reset bit71BR8Port Reset bit81BR9Port Reset bit91BR10Port Reset bit101BR11Port Reset bit111BR12Port Reset bit121BR13Port Reset bit131BR14Port Reset bit141BR15Port Reset bit151GPIOD0x48000C00GPIOEGeneral-purpose I/OsGPIO0x480010000x00x400registersMODERMODERGPIO port mode register0x00x20read-write0x000003FFMODER4Port x configuration bits (y = 0..15)82MODER3Port x configuration bits (y = 0..15)62MODER2Port x configuration bits (y = 0..15)42MODER1Port x configuration bits (y = 0..15)22MODER0Port x configuration bits (y = 0..15)02OTYPEROTYPERGPIO port output type register0x40x20read-write0x00000000OT4Port x configuration bits (y = 0..15)41OT3Port x configuration bits (y = 0..15)31OT2Port x configuration bits (y = 0..15)21OT1Port x configuration bits (y = 0..15)11OT0Port x configuration bits (y = 0..15)01OSPEEDROSPEEDRGPIO port output speed register0x80x20read-write0x000000C0OSPEEDR4Port x configuration bits (y = 0..15)82OSPEEDR3Port x configuration bits (y = 0..15)62OSPEEDR2Port x configuration bits (y = 0..15)42OSPEEDR1Port x configuration bits (y = 0..15)22OSPEEDR0Port x configuration bits (y = 0..15)02PUPDRPUPDRGPIO port pull-up/pull-down register0xC0x20read-write0x00000000PUPDR4Port x configuration bits (y = 0..15)82PUPDR3Port x configuration bits (y = 0..15)62PUPDR2Port x configuration bits (y = 0..15)42PUPDR1Port x configuration bits (y = 0..15)22PUPDR0Port x configuration bits (y = 0..15)02IDRIDRGPIO port input data register0x100x20read-only0x00000000IDR4Port input data (y = 0..15)41IDR3Port input data (y = 0..15)31IDR2Port input data (y = 0..15)21IDR1Port input data (y = 0..15)11IDR0Port input data (y = 0..15)01ODRODRGPIO port output data register0x140x20read-write0x00000000ODR4Port output data (y = 0..15)41ODR3Port output data (y = 0..15)31ODR2Port output data (y = 0..15)21ODR1Port output data (y = 0..15)11ODR0Port output data (y = 0..15)01BSRRBSRRGPIO port bit set/reset register0x180x20write-only0x00000000BR4Port x reset bit y (y = 0..15)201BR3Port x reset bit y (y = 0..15)191BR2Port x reset bit y (y = 0..15)181BR1Port x reset bit y (y = 0..15)171BR0Port x set bit y (y= 0..15)161BS4Port x set bit y (y= 0..15)41BS3Port x set bit y (y= 0..15)31BS2Port x set bit y (y= 0..15)21BS1Port x set bit y (y= 0..15)11BS0Port x set bit y (y= 0..15)01LCKRLCKRGPIO port configuration lock register0x1C0x20read-write0x00000000LCKKPort x lock bit y (y= 0..15)161LCK4Port x lock bit y (y= 0..15)41LCK3Port x lock bit y (y= 0..15)31LCK2Port x lock bit y (y= 0..15)21LCK1Port x lock bit y (y= 0..15)11LCK0Port x lock bit y (y= 0..15)01AFRLAFRLGPIO alternate function low register0x200x20read-write0x00000000AFSEL4Alternate function selection for port x bit y (y = 0..7)164AFSEL3Alternate function selection for port x bit y (y = 0..7)124AFSEL2Alternate function selection for port x bit y (y = 0..7)84AFSEL1Alternate function selection for port x bit y (y = 0..7)44AFSEL0Alternate function selection for port x bit y (y = 0..7)04AFRHAFRHGPIO alternate function high register0x240x20read-write0x00000000AFSEL15Alternate function selection for port x bit y (y = 8..15)284AFSEL14Alternate function selection for port x bit y (y = 8..15)244AFSEL13Alternate function selection for port x bit y (y = 8..15)204AFSEL12Alternate function selection for port x bit y (y = 8..15)164AFSEL11Alternate function selection for port x bit y (y = 8..15)124AFSEL10Alternate function selection for port x bit y (y = 8..15)84AFSEL9Alternate function selection for port x bit y (y = 8..15)44AFSEL8Alternate function selection for port x bit y (y = 8..15)04BRRBRRport bit reset register0x280x20write-only0x00000000BR0Port Reset bit01BR1Port Reset bit11BR2Port Reset bit21BR3Port Reset bit31BR4Port Reset bit41GPIOHGeneral-purpose I/OsGPIO0x48001C000x00x400registersMODERMODERGPIO port mode register0x00x20read-write0x000000CFMODER3Port x configuration bits (y = 0..15)62MODER1Port x configuration bits (y = 0..15)22MODER0Port x configuration bits (y = 0..15)02OTYPEROTYPERGPIO port output type register0x40x20read-write0x00000000OT3Port x configuration bits (y = 0..15)31OT1Port x configuration bits (y = 0..15)11OT0Port x configuration bits (y = 0..15)01OSPEEDROSPEEDRGPIO port output speed register0x80x20read-write0x00000000OSPEEDR3Port x configuration bits (y = 0..15)62OSPEEDR1Port x configuration bits (y = 0..15)22OSPEEDR0Port x configuration bits (y = 0..15)02PUPDRPUPDRGPIO port pull-up/pull-down register0xC0x20read-write0x00000000PUPDR3Port x configuration bits (y = 0..15)62PUPDR1Port x configuration bits (y = 0..15)22PUPDR0Port x configuration bits (y = 0..15)02IDRIDRGPIO port input data register0x100x20read-only0x00000000IDR3Port input data (y = 0..15)31IDR1Port input data (y = 0..15)11IDR0Port input data (y = 0..15)01ODRODRGPIO port output data register0x140x20read-write0x00000000ODR3Port output data (y = 0..15)31ODR1Port output data (y = 0..15)11ODR0Port output data (y = 0..15)01BSRRBSRRGPIO port bit set/reset register0x180x20write-only0x00000000BR3Port x reset bit y (y = 0..15)191BR1Port x reset bit y (y = 0..15)171BR0Port x set bit y (y= 0..15)161BS3Port x set bit y (y= 0..15)31BS1Port x set bit y (y= 0..15)11BS0Port x set bit y (y= 0..15)01LCKRLCKRGPIO port configuration lock register0x1C0x20read-write0x00000000LCKKPort x lock bit y (y= 0..15)161LCK3Port x lock bit y (y= 0..15)31LCK1Port x lock bit y (y= 0..15)11LCK0Port x lock bit y (y= 0..15)01AFRLAFRLGPIO alternate function low register0x200x20read-write0x00000000AFSEL3Alternate function selection for port x bit y (y = 0..7)124AFSEL1Alternate function selection for port x bit y (y = 0..7)44AFSEL0Alternate function selection for port x bit y (y = 0..7)04AFRHAFRHGPIO alternate function high register0x240x20read-write0x00000000AFSEL15Alternate function selection for port x bit y (y = 8..15)284AFSEL14Alternate function selection for port x bit y (y = 8..15)244AFSEL13Alternate function selection for port x bit y (y = 8..15)204AFSEL12Alternate function selection for port x bit y (y = 8..15)164AFSEL11Alternate function selection for port x bit y (y = 8..15)124AFSEL10Alternate function selection for port x bit y (y = 8..15)84AFSEL9Alternate function selection for port x bit y (y = 8..15)44AFSEL8Alternate function selection for port x bit y (y = 8..15)04BRRBRRport bit reset register0x280x20write-only0x00000000BR0Port Reset bit01BR1Port Reset bit11BR3Port Reset bit31SAI1Serial audio interfaceSAI0x400154000x00x400registersSAI1SAI1 global interrupt38GCRGCRGlobal configuration register0x00x20read-write0x00000000SYNCOUTSynchronization outputs42SYNCINSynchronization inputs02BCR1BCR1BConfiguration register 10x240x20read-write0x00000040MCKENMaster clock generation enable271OSROversampling ratio for master clock261MCJDIVMaster clock divider206NODIVNo divider191DMAENDMA enable171SAIBENAudio block B enable161OutDriOutput drive131MONOMono mode121SYNCENSynchronization enable102CKSTRClock strobing edge91LSBFIRSTLeast significant bit first81DSData size53PRTCFGProtocol configuration22MODEAudio block mode02BCR2BCR2BConfiguration register 20x280x20read-write0x00000000COMPCompanding mode142CPLComplement bit131MUTECNMute counter76MUTEVALMute value61MUTEMute51TRISTristate management on data line41FFLUSFIFO flush31FTHFIFO threshold03BFRCRBFRCRBFRCR0x2C0x20read-write0x00000007FSOFFFrame synchronization offset181FSPOLFrame synchronization polarity171FSDEFFrame synchronization definition161FSALLFrame synchronization active level length87FRLFrame length08BSLOTRBSLOTRBSlot register0x300x20read-write0x00000000SLOTENSlot enable1616NBSLOTNumber of slots in an audio frame84SLOTSZSlot size62FBOFFFirst bit offset05BIMBIMBInterrupt mask register20x340x20read-write0x00000000LFSDETIELate frame synchronization detection interrupt enable61AFSDETIEAnticipated frame synchronization detection interrupt enable51CNRDYIECodec not ready interrupt enable41FREQIEFIFO request interrupt enable31WCKCFGWrong clock configuration interrupt enable21MUTEDETMute detection interrupt enable11OVRUDRIEOverrun/underrun interrupt enable01BSRBSRBStatus register0x380x20read-only0x00000008FLVLFIFO level threshold163LFSDETLate frame synchronization detection61AFSDETAnticipated frame synchronization detection51CNRDYCodec not ready41FREQFIFO request31WCKCFGWrong clock configuration flag21MUTEDETMute detection11OVRUDROverrun / underrun01BCLRFRBCLRFRBClear flag register0x3C0x20write-only0x00000000LFSDETClear late frame synchronization detection flag61CAFSDETClear anticipated frame synchronization detection flag51CNRDYClear codec not ready flag41WCKCFGClear wrong clock configuration flag21MUTEDETMute detection flag11OVRUDRClear overrun / underrun01BDRBDRBData register0x400x20read-write0x00000000DATAData032ACR1ACR1AConfiguration register 10x40x20read-write0x00000040MCKENMaster clock generation enable271OSROversampling ratio for master clock261MCJDIVMaster clock divider206NODIVNo divider191DMAENDMA enable171SAIBENAudio block B enable161OutDriOutput drive131MONOMono mode121SYNCENSynchronization enable102CKSTRClock strobing edge91LSBFIRSTLeast significant bit first81DSData size53PRTCFGProtocol configuration22MODEAudio block mode02ACR2ACR2AConfiguration register 20x80x20read-write0x00000000COMPCompanding mode142CPLComplement bit131MUTECNMute counter76MUTEVALMute value61MUTEMute51TRISTristate management on data line41FFLUSFIFO flush31FTHFIFO threshold03AFRCRAFRCRAFRCR0xC0x20read-write0x00000007FSOFFFrame synchronization offset181FSPOLFrame synchronization polarity171FSDEFFrame synchronization definition161FSALLFrame synchronization active level length87FRLFrame length08ASLOTRASLOTRASlot register0x100x20read-write0x00000000SLOTENSlot enable1616NBSLOTNumber of slots in an audio frame84SLOTSZSlot size62FBOFFFirst bit offset05AIMAIMAInterrupt mask register20x140x20read-write0x00000000LFSDETLate frame synchronization detection interrupt enable61AFSDETIEAnticipated frame synchronization detection interrupt enable51CNRDYIECodec not ready interrupt enable41FREQIEFIFO request interrupt enable31WCKCFGWrong clock configuration interrupt enable21MUTEDETMute detection interrupt enable11OVRUDRIEOverrun/underrun interrupt enable01ASRASRAStatus register0x180x20read-only0x00000008FLVLFIFO level threshold163LFSDETLate frame synchronization detection61AFSDETAnticipated frame synchronization detection51CNRDYCodec not ready41FREQFIFO request31WCKCFGWrong clock configuration flag. This bit is read only21MUTEDETMute detection11OVRUDROverrun / underrun01ACLRFRACLRFRAClear flag register0x1C0x20write-only0x00000000LFSDETClear late frame synchronization detection flag61CAFSDETClear anticipated frame synchronization detection flag51CNRDYClear codec not ready flag41WCKCFGClear wrong clock configuration flag21MUTEDETMute detection flag11OVRUDRClear overrun / underrun01ADRADRAData register0x200x20read-write0x00000000DATAData032PDMCRPDMCRPDM control register0x440x20read-write0x00000000CKEN4Clock enable of bitstream clock number 4111CKEN3Clock enable of bitstream clock number 3101CKEN2Clock enable of bitstream clock number 291CKEN1Clock enable of bitstream clock number 181MICNBRNumber of microphones42PDMENPDM enable01PDMDLYPDMDLYPDM delay register0x480x20read-write0x00000000DLYM4RDelay line for second microphone of pair 4283DLYM4LDelay line for first microphone of pair 4243DLYM3RDelay line for second microphone of pair 3203DLYM3LDelay line for first microphone of pair 3163DLYM2RDelay line for second microphone of pair 2123DLYM2LDelay line for first microphone of pair 283DLYM1RDelay line for second microphone of pair 143DLYM1LDelay line for first microphone of pair 103TIM2General-purpose-timersTIM0x400000000x00x400registersTIM2TIM2 global interrupt28CR1CR1control register 10x00x20read-write0x0000UIFREMAPUIF status bit remapping111CKDClock division82ARPEAuto-reload preload enable71CMSCenter-aligned mode selection52DIRDirection41OPMOne-pulse mode31URSUpdate request source21UDISUpdate disable11CENCounter enable01CR2CR2control register 20x40x20read-write0x0000TI1STI1 selection71MMSMaster mode selection43CCDSCapture/compare DMA selection31SMCRSMCRslave mode control register0x80x20read-write0x0000SMS_3Slave mode selection - bit 3161ETPExternal trigger polarity151ECEExternal clock enable141ETPSExternal trigger prescaler122ETFExternal trigger filter84MSMMaster/Slave mode71TSTrigger selection43OCCSOCREF clear selection31SMSSlave mode selection03DIERDIERDMA/Interrupt enable register0xC0x20read-write0x0000CC4DECapture/Compare 4 DMA request enable121CC3DECapture/Compare 3 DMA request enable111CC2DECapture/Compare 2 DMA request enable101CC1DECapture/Compare 1 DMA request enable91UDEUpdate DMA request enable81TIETrigger interrupt enable61CC4IECapture/Compare 4 interrupt enable41CC3IECapture/Compare 3 interrupt enable31CC2IECapture/Compare 2 interrupt enable21CC1IECapture/Compare 1 interrupt enable11UIEUpdate interrupt enable01SRSRstatus register0x100x20read-write0x0000CC4OFCapture/Compare 4 overcapture flag121CC3OFCapture/Compare 3 overcapture flag111CC2OFCapture/compare 2 overcapture flag101CC1OFCapture/Compare 1 overcapture flag91TIFTrigger interrupt flag61CC4IFCapture/Compare 4 interrupt flag41CC3IFCapture/Compare 3 interrupt flag31CC2IFCapture/Compare 2 interrupt flag21CC1IFCapture/compare 1 interrupt flag11UIFUpdate interrupt flag01EGREGRevent generation register0x140x20write-only0x0000TGTrigger generation61CC4GCapture/compare 4 generation41CC3GCapture/compare 3 generation31CC2GCapture/compare 2 generation21CC1GCapture/compare 1 generation11UGUpdate generation01CCMR1_OutputCCMR1_Outputcapture/compare mode register 1 (output mode)0x180x20read-write0x00000000OC2M_3Output Compare 2 mode - bit 3241OC1M_3Output Compare 1 mode - bit 3161OC2CEOutput compare 2 clear enable151OC2MOutput compare 2 mode123OC2PEOutput compare 2 preload enable111OC2FEOutput compare 2 fast enable101CC2SCapture/Compare 2 selection82OC1CEOutput compare 1 clear enable71OC1MOutput compare 1 mode43OC1PEOutput compare 1 preload enable31OC1FEOutput compare 1 fast enable21CC1SCapture/Compare 1 selection02CCMR1_InputCCMR1_Inputcapture/compare mode register 1 (input mode)CCMR1_Output0x180x20read-write0x00000000IC2FInput capture 2 filter124IC2PSCInput capture 2 prescaler102CC2SCapture/compare 2 selection82IC1FInput capture 1 filter44IC1PSCInput capture 1 prescaler22CC1SCapture/Compare 1 selection02CCMR2_OutputCCMR2_Outputcapture/compare mode register 2 (output mode)0x1C0x20read-write0x00000000OC4M_3Output Compare 4 mode - bit 3241OC3M_3Output Compare 3 mode - bit 3161OC4CEOutput compare 4 clear enable151OC4MOutput compare 4 mode123OC4PEOutput compare 4 preload enable111OC4FEOutput compare 4 fast enable101CC4SCapture/Compare 4 selection82OC3CEOutput compare 3 clear enable71OC3MOutput compare 3 mode43OC3PEOutput compare 3 preload enable31OC3FEOutput compare 3 fast enable21CC3SCapture/Compare 3 selection02CCMR2_InputCCMR2_Inputcapture/compare mode register 2 (input mode)CCMR2_Output0x1C0x20read-write0x00000000IC4FInput capture 4 filter124IC4PSCInput capture 4 prescaler102CC4SCapture/Compare 4 selection82IC3FInput capture 3 filter44IC3PSCInput capture 3 prescaler22CC3SCapture/Compare 3 selection02CCERCCERcapture/compare enable register0x200x20read-write0x0000CC4NPCapture/Compare 4 output Polarity151CC4PCapture/Compare 3 output Polarity131CC4ECapture/Compare 4 output enable121CC3NPCapture/Compare 3 output Polarity111CC3PCapture/Compare 3 output Polarity91CC3ECapture/Compare 3 output enable81CC2NPCapture/Compare 2 output Polarity71CC2PCapture/Compare 2 output Polarity51CC2ECapture/Compare 2 output enable41CC1NPCapture/Compare 1 output Polarity31CC1PCapture/Compare 1 output Polarity11CC1ECapture/Compare 1 output enable01CNTCNTcounter0x240x200x00000000CNT_HHigh counter value (TIM2 only)1615read-writeCNT_LLow counter value016read-writeUIFCPYValue depends on IUFREMAP in TIM2_CR1.311read-onlyPSCPSCprescaler0x280x20read-write0x0000PSCPrescaler value016ARRARRauto-reload register0x2C0x20read-write0x00000000ARR_HHigh Auto-reload value (TIM2 only)1616ARR_LLow Auto-reload value016CCR1CCR1capture/compare register 10x340x20read-write0x00000000CCR1_HHigh Capture/Compare 1 value (TIM2 only)1616CCR1_LLow Capture/Compare 1 value016CCR2CCR2capture/compare register 20x380x20read-write0x00000000CCR2_HHigh Capture/Compare 2 value (TIM2 only)1616CCR2_LLow Capture/Compare 2 value016CCR3CCR3capture/compare register 30x3C0x20read-write0x00000000CCR3_HHigh Capture/Compare value (TIM2 only)1616CCR3_LLow Capture/Compare value016CCR4CCR4capture/compare register 40x400x20read-write0x00000000CCR4_HHigh Capture/Compare value (TIM2 only)1616CCR4_LLow Capture/Compare value016DCRDCRDMA control register0x480x20read-write0x0000DBLDMA burst length85DBADMA base address05DMARDMARDMA address for full transfer0x4C0x20read-write0x0000DMABDMA register for burst accesses016ORORTIM2 option register0x500x20read-write0x0000TI4_RMPInput capture 4 remap22ETR_RMPExternal trigger remap11ITR_RMPInternal trigger remap01AFAFTIM2 alternate function option register 10x600x20read-write0x0000ETRSELExternal trigger source selection143TIM16General purpose timersTIM0x400144000x00x400registersCR1CR1control register 10x00x20read-write0x0000CENCounter enable01UDISUpdate disable11URSUpdate request source21OPMOne-pulse mode31ARPEAuto-reload preload enable71CKDClock division82UIFREMAPUIF status bit remapping111CR2CR2control register 20x40x20read-write0x0000OIS1NOutput Idle state 191OIS1Output Idle state 181CCDSCapture/compare DMA selection31CCUSCapture/compare control update selection21CCPCCapture/compare preloaded control01DIERDIERDMA/Interrupt enable register0xC0x20read-write0x0000UIEUpdate interrupt enable01CC1IECapture/Compare 1 interrupt enable11COMIECOM interrupt enable51BIEBreak interrupt enable71UDEUpdate DMA request enable81CC1DECapture/Compare 1 DMA request enable91SRSRstatus register0x100x20read-write0x0000CC1OFCapture/Compare 1 overcapture flag91BIFBreak interrupt flag71COMIFCOM interrupt flag51CC1IFCapture/compare 1 interrupt flag11UIFUpdate interrupt flag01EGREGRevent generation register0x140x20write-only0x0000BGBreak generation71COMGCapture/Compare control update generation51CC1GCapture/compare 1 generation11UGUpdate generation01CCMR1_OutputCCMR1_Outputcapture/compare mode register (output mode)0x180x20read-write0x00000000OC1M_3Output Compare 1 mode161OC1MOutput Compare 1 mode43OC1PEOutput Compare 1 preload enable31OC1FEOutput Compare 1 fast enable21CC1SCapture/Compare 1 selection02CCMR1_InputCCMR1_Inputcapture/compare mode register 1 (input mode)CCMR1_Output0x180x20read-write0x00000000IC1FInput capture 1 filter44IC1PSCInput capture 1 prescaler22CC1SCapture/Compare 1 selection02CCERCCERcapture/compare enable register0x200x20read-write0x0000CC1NPCapture/Compare 1 output Polarity31CC1NECapture/Compare 1 complementary output enable21CC1PCapture/Compare 1 output Polarity11CC1ECapture/Compare 1 output enable01CNTCNTcounter0x240x200x00000000CNTcounter value016read-writeUIFCPYUIF Copy311read-onlyPSCPSCprescaler0x280x20read-write0x0000PSCPrescaler value016ARRARRauto-reload register0x2C0x20read-write0xFFFFARRAuto-reload value016RCRRCRrepetition counter register0x300x20read-write0x0000REPRepetition counter value08CCR1CCR1capture/compare register 10x340x20read-write0x00000000CCR1Capture/Compare 1 value016BDTRBDTRbreak and dead-time register0x440x20read-write0x0000DTGDead-time generator setup08LOCKLock configuration82OSSIOff-state selection for Idle mode101OSSROff-state selection for Run mode111BKEBreak enable121BKPBreak polarity131AOEAutomatic output enable141MOEMain output enable151BKDSRMBreak Disarm261BKBIDBreak Bidirectional281DCRDCRDMA control register0x480x20read-write0x0000DBLDMA burst length85DBADMA base address05DMARDMARDMA address for full transfer0x4C0x20read-write0x0000DMABDMA register for burst accesses016OR1OR1TIM option register 10x500x20read-write0x0000TI1_RMPInput capture 1 remap02AF1AF1alternate function register 10x600x20read-write0x00000001BKINEBRK BKIN input enable01BKCMP1EBRK COMP1 enable11BKCMP2EBRK COMP2 enable21BKINPBRK BKIN input polarity91BKCMP1PBRK COMP1 input polarity101BKCMP2PBRK COMP2 input polarit111TISELTISELinput selection register0x680x20read-write0x00000000TI1SELselects TI1[0] to TI1[15] input04TIM17General purpose timersTIM0x400148000x00x400registersCR1CR1control register 10x00x20read-write0x0000CENCounter enable01UDISUpdate disable11URSUpdate request source21OPMOne-pulse mode31ARPEAuto-reload preload enable71CKDClock division82UIFREMAPUIF status bit remapping111CR2CR2control register 20x40x20read-write0x0000OIS1NOutput Idle state 191OIS1Output Idle state 181CCDSCapture/compare DMA selection31CCUSCapture/compare control update selection21CCPCCapture/compare preloaded control01DIERDIERDMA/Interrupt enable register0xC0x20read-write0x0000UIEUpdate interrupt enable01CC1IECapture/Compare 1 interrupt enable11COMIECOM interrupt enable51BIEBreak interrupt enable71UDEUpdate DMA request enable81CC1DECapture/Compare 1 DMA request enable91SRSRstatus register0x100x20read-write0x0000CC1OFCapture/Compare 1 overcapture flag91BIFBreak interrupt flag71COMIFCOM interrupt flag51CC1IFCapture/compare 1 interrupt flag11UIFUpdate interrupt flag01EGREGRevent generation register0x140x20write-only0x0000BGBreak generation71COMGCapture/Compare control update generation51CC1GCapture/compare 1 generation11UGUpdate generation01CCMR1_OutputCCMR1_Outputcapture/compare mode register (output mode)0x180x20read-write0x00000000OC1M_3Output Compare 1 mode161OC1MOutput Compare 1 mode43OC1PEOutput Compare 1 preload enable31OC1FEOutput Compare 1 fast enable21CC1SCapture/Compare 1 selection02CCMR1_InputCCMR1_Inputcapture/compare mode register 1 (input mode)CCMR1_Output0x180x20read-write0x00000000IC1FInput capture 1 filter44IC1PSCInput capture 1 prescaler22CC1SCapture/Compare 1 selection02CCERCCERcapture/compare enable register0x200x20read-write0x0000CC1NPCapture/Compare 1 output Polarity31CC1NECapture/Compare 1 complementary output enable21CC1PCapture/Compare 1 output Polarity11CC1ECapture/Compare 1 output enable01CNTCNTcounter0x240x200x00000000CNTcounter value016read-writeUIFCPYUIF Copy311read-onlyPSCPSCprescaler0x280x20read-write0x0000PSCPrescaler value016ARRARRauto-reload register0x2C0x20read-write0xFFFFARRAuto-reload value016RCRRCRrepetition counter register0x300x20read-write0x0000REPRepetition counter value08CCR1CCR1capture/compare register 10x340x20read-write0x00000000CCR1Capture/Compare 1 value016BDTRBDTRbreak and dead-time register0x440x20read-write0x0000DTGDead-time generator setup08LOCKLock configuration82OSSIOff-state selection for Idle mode101OSSROff-state selection for Run mode111BKEBreak enable121BKPBreak polarity131AOEAutomatic output enable141MOEMain output enable151BKDSRMBreak Disarm261BKBIDBreak Bidirectional281DCRDCRDMA control register0x480x20read-write0x0000DBLDMA burst length85DBADMA base address05DMARDMARDMA address for full transfer0x4C0x20read-write0x0000DMABDMA register for burst accesses016OR1OR1TIM option register 10x500x20read-write0x0000TI1_RMPInput capture 1 remap02AF1AF1alternate function register 10x600x20read-write0x00000001BKINEBRK BKIN input enable01BKCMP1EBRK COMP1 enable11BKCMP2EBRK COMP2 enable21BKINPBRK BKIN input polarity91BKCMP1PBRK COMP1 input polarity101BKCMP2PBRK COMP2 input polarit111TISELTISELinput selection register0x680x20read-write0x00000000TI1SELselects TI1[0] to TI1[15] input04TIM1Advanced-timersTIM0x40012C000x00x400registersTIM1_BRKTimer 1 break interrupt24TIM1_UPTimer 1 Update25TIM1_TRG_COM_TIM17TIM1 Trigger and Commutation interrupts and TIM17 global interrupt26TIM1_CCTIM1 Capture Compare interrupt27CR1CR1control register 10x00x20read-write0x0000CENCounter enable01OPMOne-pulse mode31UDISUpdate disable11URSUpdate request source21DIRDirection41CMSCenter-aligned mode selection52ARPEAuto-reload preload enable71CKDClock division82UIFREMAPUIF status bit remapping111CR2CR2control register 20x40x20read-write0x0000MMS2Master mode selection 2204OIS6Output Idle state 6 (OC6 output)181OIS5Output Idle state 5 (OC5 output)161OIS4Output Idle state 4141OIS3NOutput Idle state 3131OIS3Output Idle state 3121OIS2NOutput Idle state 2111OIS2Output Idle state 2101OIS1NOutput Idle state 191OIS1Output Idle state 181TI1STI1 selection71MMSMaster mode selection43CCDSCapture/compare DMA selection31CCUSCapture/compare control update selection21CCPCCapture/compare preloaded control01SMCRSMCRslave mode control register0x80x20read-write0x0000SMSSlave mode selection03OCCSOCREF clear selection31TSTrigger selection43MSMMaster/Slave mode71ETFExternal trigger filter84ETPSExternal trigger prescaler122ECEExternal clock enable141ETPExternal trigger polarity151SMS_3Slave mode selection - bit 3161DIERDIERDMA/Interrupt enable register0xC0x20read-write0x0000UIEUpdate interrupt enable01CC1IECapture/Compare 1 interrupt enable11CC2IECapture/Compare 2 interrupt enable21CC3IECapture/Compare 3 interrupt enable31CC4IECapture/Compare 4 interrupt enable41COMIECOM interrupt enable51TIETrigger interrupt enable61BIEBreak interrupt enable71UDEUpdate DMA request enable81CC1DECapture/Compare 1 DMA request enable91CC2DECapture/Compare 2 DMA request enable101CC3DECapture/Compare 3 DMA request enable111CC4DECapture/Compare 4 DMA request enable121COMDECOM DMA request enable131TDETrigger DMA request enable141SRSRstatus register0x100x20read-write0x0000UIFUpdate interrupt flag01CC1IFCapture/compare 1 interrupt flag11CC2IFCapture/Compare 2 interrupt flag21CC3IFCapture/Compare 3 interrupt flag31CC4IFCapture/Compare 4 interrupt flag41COMIFCOM interrupt flag51TIFTrigger interrupt flag61BIFBreak interrupt flag71B2IFBreak 2 interrupt flag81CC1OFCapture/Compare 1 overcapture flag91CC2OFCapture/compare 2 overcapture flag101CC3OFCapture/Compare 3 overcapture flag111CC4OFCapture/Compare 4 overcapture flag121SBIFSystem Break interrupt flag131CC5IFCompare 5 interrupt flag161CC6IFCompare 6 interrupt flag171EGREGRevent generation register0x140x20write-only0x0000UGUpdate generation01CC1GCapture/compare 1 generation11CC2GCapture/compare 2 generation21CC3GCapture/compare 3 generation31CC4GCapture/compare 4 generation41COMGCapture/Compare control update generation51TGTrigger generation61BGBreak generation71B2GBreak 2 generation81CCMR1_InputCCMR1_Inputcapture/compare mode register 1 (output mode)0x180x20read-write0x00000000CC1SCapture/Compare 1 selection02IC1PSCInput capture 1 prescaler22C1FInput capture 1 filter44CC2Scapture/Compare 2 selection82IC2PSCInput capture 2 prescaler102IC2FInput capture 2 filter124CCMR1_OutputCCMR1_Outputcapture/compare mode register 1 (output mode)CCMR1_Input0x180x20read-write0x00000000CC1SCapture/Compare 1 selection02OC1FEOutput Compare 1 fast enable21OC1PEOutput Compare 1 preload enable31OC1MOutput Compare 1 mode43OC1CEOutput Compare 1 clear enable71CC2SCapture/Compare 2 selection82OC2FEOutput Compare 2 fast enable101OC2PEOutput Compare 2 preload enable111OC2MOutput Compare 2 mode123OC2CEOutput Compare 2 clear enable151OC1M_3Output Compare 1 mode - bit 3161OC2M_3Output Compare 2 mode - bit 3241CCMR2_OutputCCMR2_Outputcapture/compare mode register 2 (output mode)0x1C0x20read-write0x00000000CC3SCapture/Compare 3 selection02OC3FEOutput compare 3 fast enable21OC3PEOutput compare 3 preload enable31OC3MOutput compare 3 mode43OC3CEOutput compare 3 clear enable71CC4SCapture/Compare 4 selection82OC4FEOutput compare 4 fast enable101OC4PEOutput compare 4 preload enable111OC4MOutput compare 4 mode123OC4CEOutput compare 4 clear enable151OC3M_3Output Compare 3 mode - bit 3161OC4M_3Output Compare 4 mode - bit 3241CCMR2_InputCCMR2_Inputcapture/compare mode register 2 (output mode)CCMR2_Output0x1C0x20read-write0x00000000CC3SCapture/Compare 3 selection02C3PSCInput capture 3 prescaler22IC3FInput capture 3 filter44CC4SCapture/Compare 4 selection82IC4PSCInput capture 4 prescaler102IC4FInput capture 4 filter124CCERCCERcapture/compare enable register0x200x20read-write0x0000CC1ECapture/Compare 1 output enable01CC1PCapture/Compare 1 output Polarity11CC1NECapture/Compare 1 complementary output enable21CC1NPCapture/Compare 1 output Polarity31CC2ECapture/Compare 2 output enable41CC2PCapture/Compare 2 output Polarity51CC2NECapture/Compare 2 complementary output enable61CC2NPCapture/Compare 2 output Polarity71CC3ECapture/Compare 3 output enable81CC3PCapture/Compare 3 output Polarity91CC3NECapture/Compare 3 complementary output enable101CC3NPCapture/Compare 3 output Polarity111CC4ECapture/Compare 4 output enable121CC4PCapture/Compare 3 output Polarity131CC4NPCapture/Compare 4 complementary output polarity151CC5ECapture/Compare 5 output enable161CC5PCapture/Compare 5 output polarity171CC6ECapture/Compare 6 output enable201CC6PCapture/Compare 6 output polarity211CNTCNTcounter0x240x200x00000000CNTcounter value016read-writeUIFCPYUIF copy311read-onlyPSCPSCprescaler0x280x20read-write0x0000PSCPrescaler value016ARRARRauto-reload register0x2C0x20read-write0x0000FFFFARRAuto-reload value016RCRRCRrepetition counter register0x300x20read-write0x0000REPRepetition counter value016CCR1CCR1capture/compare register 10x340x20read-write0x00000000CCR1Capture/Compare 1 value016CCR2CCR2capture/compare register 20x380x20read-write0x00000000CCR2Capture/Compare 2 value016CCR3CCR3capture/compare register 30x3C0x20read-write0x00000000CCR3Capture/Compare value016CCR4CCR4capture/compare register 40x400x20read-write0x00000000CCR4Capture/Compare value016BDTRBDTRbreak and dead-time register0x440x20read-write0x0000DTGDead-time generator setup08LOCKLock configuration82OSSIOff-state selection for Idle mode101OSSROff-state selection for Run mode111BKEBreak enable121BKPBreak polarity131AOEAutomatic output enable141MOEMain output enable151BKFBreak filter164BK2FBreak 2 filter204BK2EBreak 2 enable241BK2PBreak 2 polarity251DCRDCRDMA control register0x480x20read-write0x0000DBLDMA burst length85DBADMA base address05DMARDMARDMA address for full transfer0x4C0x20read-write0x0000DMABDMA register for burst accesses016ORORDMA address for full transfer0x500x20read-write0x0000TIM1_ETR_ADC1_RMPTIM1_ETR_ADC1 remapping capability02TI1_RMPInput Capture 1 remap41CCMR3_OutputCCMR3_Outputcapture/compare mode register 2 (output mode)0x540x20read-write0x00000000OC6M_bit3Output Compare 6 mode bit 3241OC5M_bit3Output Compare 5 mode bit 3161OC6CEOutput compare 6 clear enable151OC6MOutput compare 6 mode123OC6PEOutput compare 6 preload enable111OC6FEOutput compare 6 fast enable101OC5CEOutput compare 5 clear enable71OC5MOutput compare 5 mode43OC5PEOutput compare 5 preload enable31OC5FEOutput compare 5 fast enable21CCR5CCR5capture/compare register 40x580x20read-write0x00000000CCR5Capture/Compare value016GC5C1Group Channel 5 and Channel 1291GC5C2Group Channel 5 and Channel 2301GC5C3Group Channel 5 and Channel 3311CCR6CCR6capture/compare register 40x5C0x20read-write0x00000000CCR6Capture/Compare value016AF1AF1DMA address for full transfer0x600x20read-write0x00000001BKINEBRK BKIN input enable01BKCMP1EBRK COMP1 enable11BKCMP2EBRK COMP2 enable21BKINPBRK BKIN input polarity91BKCMP1PBRK COMP1 input polarity101BKCMP2PBRK COMP2 input polarity111ETRSELETR source selection143AF2AF2DMA address for full transfer0x640x20read-write0x00000001BK2INEBRK2 BKIN input enable01BK2CMP1EBRK2 COMP1 enable11BK2CMP2EBRK2 COMP2 enable21BK2DFBK0EBRK2 DFSDM_BREAK0 enable81BK2INPBRK2 BKIN input polarity91BK2CMP1PBRK2 COMP1 input polarity101BK2CMP2PBRK2 COMP2 input polarity111LPTIM1Low power timerLPTIM0x40007C000x00x400registersLPTIM1LPtimer 1 global interrupt47ISRISRInterrupt and Status Register0x00x20read-only0x00000000DOWNCounter direction change up to down61UPCounter direction change down to up51ARROKAutoreload register update OK41CMPOKCompare register update OK31EXTTRIGExternal trigger edge event21ARRMAutoreload match11CMPMCompare match01ICRICRInterrupt Clear Register0x40x20write-only0x00000000DOWNCFDirection change to down Clear Flag61UPCFDirection change to UP Clear Flag51ARROKCFAutoreload register update OK Clear Flag41CMPOKCFCompare register update OK Clear Flag31EXTTRIGCFExternal trigger valid edge Clear Flag21ARRMCFAutoreload match Clear Flag11CMPMCFcompare match Clear Flag01IERIERInterrupt Enable Register0x80x20read-write0x00000000DOWNIEDirection change to down Interrupt Enable61UPIEDirection change to UP Interrupt Enable51ARROKIEAutoreload register update OK Interrupt Enable41CMPOKIECompare register update OK Interrupt Enable31EXTTRIGIEExternal trigger valid edge Interrupt Enable21ARRMIEAutoreload match Interrupt Enable11CMPMIECompare match Interrupt Enable01CFGRCFGRConfiguration Register0xC0x20read-write0x00000000ENCEncoder mode enable241COUNTMODEcounter mode enabled231PRELOADRegisters update mode221WAVPOLWaveform shape polarity211WAVEWaveform shape201TIMOUTTimeout enable191TRIGENTrigger enable and polarity172TRIGSELTrigger selector133PRESCClock prescaler93TRGFLTConfigurable digital filter for trigger62CKFLTConfigurable digital filter for external clock32CKPOLClock Polarity12CKSELClock selector01CRCRControl Register0x100x20read-write0x00000000RSTAREReset after read enable41COUNTRSTCounter reset31CNTSTRTTimer start in continuous mode21SNGSTRTLPTIM start in single mode11ENABLELPTIM Enable01CMPCMPCompare Register0x140x20read-write0x00000000CMPCompare value016ARRARRAutoreload Register0x180x20read-write0x00000001ARRAuto reload value016CNTCNTCounter Register0x1C0x20read-only0x00000000CNTCounter value016OROROption Register0x200x20read-write0x00000000OR1Option register bit 101OR2Option register bit 211LPTIM20x40009400LPTIM2LPtimer 2 global interrupt48USART1Universal synchronous asynchronous receiver transmitterUSART0x400138000x00x400registersUSART1USART1 global interrupt36CR1CR1Control register 10x00x20read-write0x0000RXFFIERXFIFO Full interrupt enable311TXFEIETXFIFO empty interrupt enable301FIFOENFIFO mode enable291M1Word length281EOBIEEnd of Block interrupt enable271RTOIEReceiver timeout interrupt enable261DEAT4Driver Enable assertion time251DEAT3DEAT3241DEAT2DEAT2231DEAT1DEAT1221DEAT0DEAT0211DEDT4Driver Enable de-assertion time201DEDT3DEDT3191DEDT2DEDT2181DEDT1DEDT1171DEDT0DEDT0161OVER8Oversampling mode151CMIECharacter match interrupt enable141MMEMute mode enable131M0Word length121WAKEReceiver wakeup method111PCEParity control enable101PSParity selection91PEIEPE interrupt enable81TXEIEinterrupt enable71TCIETransmission complete interrupt enable61RXNEIERXNE interrupt enable51IDLEIEIDLE interrupt enable41TETransmitter enable31REReceiver enable21UESMUSART enable in Stop mode11UEUSART enable01CR2CR2Control register 20x40x20read-write0x0000ADD4_7Address of the USART node284ADD0_3Address of the USART node244RTOENReceiver timeout enable231ABRMOD1Auto baud rate mode221ABRMOD0ABRMOD0211ABRENAuto baud rate enable201MSBFIRSTMost significant bit first191TAINVBinary data inversion181TXINVTX pin active level inversion171RXINVRX pin active level inversion161SWAPSwap TX/RX pins151LINENLIN mode enable141STOPSTOP bits122CLKENClock enable111CPOLClock polarity101CPHAClock phase91LBCLLast bit clock pulse81LBDIELIN break detection interrupt enable61LBDLLIN break detection length51ADDM77-bit Address Detection/4-bit Address Detection41DIS_NSSWhen the DSI_NSS bit is set, the NSS pin input will be ignored31SLVENSynchronous Slave mode enable01CR3CR3Control register 30x80x20read-write0x0000TXFTCFGTXFIFO threshold configuration293RXFTIERXFIFO threshold interrupt enable281RXFTCFGReceive FIFO threshold configuration253TCBGTIETr Complete before guard time, interrupt enable241TXFTIEthreshold interrupt enable231WUFIEWakeup from Stop mode interrupt enable221WUSWakeup from Stop mode interrupt flag selection202SCARCNTSmartcard auto-retry count173DEPDriver enable polarity selection151DEMDriver enable mode141DDREDMA Disable on Reception Error131OVRDISOverrun Disable121ONEBITOne sample bit method enable111CTSIECTS interrupt enable101CTSECTS enable91RTSERTS enable81DMATDMA enable transmitter71DMARDMA enable receiver61SCENSmartcard mode enable51NACKSmartcard NACK enable41HDSELHalf-duplex selection31IRLPIr low-power21IRENIr mode enable11EIEError interrupt enable01BRRBRRBaud rate register0xC0x20read-write0x0000BRRBRR_4_15016GTPRGTPRGuard time and prescaler register0x100x20read-write0x0000GTGuard time value88PSCPrescaler value08RTORRTORReceiver timeout register0x140x20read-write0x0000BLENBlock Length248RTOReceiver timeout value024RQRRQRRequest register0x180x20write-only0x0000TXFRQTransmit data flush request41RXFRQReceive data flush request31MMRQMute mode request21SBKRQSend break request11ABRRQAuto baud rate request01ISRISRInterrupt & status register0x1C0x20read-only0x00C0TXFTTXFIFO threshold flag271RXFTRXFIFO threshold flag261TCBGTTransmission complete before guard time flag251RXFFRXFIFO Full241TXFETXFIFO Empty231REACKREACK221TEACKTEACK211WUFWUF201RWURWU191SBKFSBKF181CMFCMF171BUSYBUSY161ABRFABRF151ABREABRE141UDRSPI slave underrun error flag131EOBFEOBF121RTOFRTOF111CTSCTS101CTSIFCTSIF91LBDFLBDF81TXETXE71TCTC61RXNERXNE51IDLEIDLE41OREORE31NFNF21FEFE11PEPE01ICRICRInterrupt flag clear register0x200x20write-only0x0000WUCFWakeup from Stop mode clear flag201CMCFCharacter match clear flag171UDRCFSPI slave underrun clear flag131EOBCFEnd of block clear flag121RTOCFReceiver timeout clear flag111CTSCFCTS clear flag91LBDCFLIN break detection clear flag81TCBGTCFTransmission complete before Guard time clear flag71TCCFTransmission complete clear flag61TXFECFTXFIFO empty clear flag51IDLECFIdle line detected clear flag41ORECFOverrun error clear flag31NCFNoise detected clear flag21FECFFraming error clear flag11PECFParity error clear flag01RDRRDRReceive data register0x240x20read-only0x0000RDRReceive data value09TDRTDRTransmit data register0x280x20read-write0x0000TDRTransmit data value09PRESCPRESCPrescaler register0x2C0x20read-write0x0000PRESCALERClock prescaler04LPUART10x40008000LPUART1LPUART1 global interrupt37SPI1Serial peripheral interface/Inter-IC soundSPI0x400130000x00x400registersSPI1SPI 1 global interrupt34CR1CR1control register 10x00x20read-write0x00000000BIDIMODEBidirectional data mode enable151BIDIOEOutput enable in bidirectional mode141CRCENHardware CRC calculation enable131CRCNEXTCRC transfer next121CRCLCRC length111RXONLYReceive only101SSMSoftware slave management91SSIInternal slave select81LSBFIRSTFrame format71SPESPI enable61BRBaud rate control33MSTRMaster selection21CPOLClock polarity11CPHAClock phase01CR2CR2control register 20x40x20read-write0x00000700RXDMAENRx buffer DMA enable01TXDMAENTx buffer DMA enable11SSOESS output enable21NSSPNSS pulse management31FRFFrame format41ERRIEError interrupt enable51RXNEIERX buffer not empty interrupt enable61TXEIETx buffer empty interrupt enable71DSData size84FRXTHFIFO reception threshold121LDMA_RXLast DMA transfer for reception131LDMA_TXLast DMA transfer for transmission141SRSRstatus register0x80x200x00000002RXNEReceive buffer not empty01read-onlyTXETransmit buffer empty11read-onlyCRCERRCRC error flag41read-writeMODFMode fault51read-onlyOVROverrun flag61read-onlyBSYBusy flag71read-onlyTIFRFETI frame format error81read-onlyFRLVLFIFO reception level92read-onlyFTLVLFIFO transmission level112read-onlyDRDRdata register0xC0x20read-write0x00000000DRData register016CRCPRCRCPRCRC polynomial register0x100x20read-write0x00000007CRCPOLYCRC polynomial register016RXCRCRRXCRCRRX CRC register0x140x20read-only0x00000000RxCRCRx CRC register016TXCRCRTXCRCRTX CRC register0x180x20read-only0x00000000TxCRCTx CRC register016SPI20x40003800SPI2SPI1 global interrupt35RTCReal-time clockRTC0x400028000x00x400registersRTC_TAMPRTC/TAMP/CSS on LSE through EXTI line 19 interrupt2RTC_WKUPRTC wakeup interrupt through EXTI[19]3RTC_ALARMRTC Alarms (A and B) interrupt through AIEC41TRTRtime register0x00x20read-write0x00000000PMAM/PM notation221HTHour tens in BCD format202HUHour units in BCD format164MNTMinute tens in BCD format123MNUMinute units in BCD format84STSecond tens in BCD format43SUSecond units in BCD format04DRDRdate register0x40x20read-write0x00002101YTYear tens in BCD format204YUYear units in BCD format164WDUWeek day units133MTMonth tens in BCD format121MUMonth units in BCD format84DTDate tens in BCD format42DUDate units in BCD format04CRCRcontrol register0x80x20read-write0x00000000WCKSELWakeup clock selection03TSEDGETime-stamp event active edge31REFCKONReference clock detection enable (50 or 60 Hz)41BYPSHADBypass the shadow registers51FMTHour format61ALRAEAlarm A enable81ALRBEAlarm B enable91WUTEWakeup timer enable101TSETime stamp enable111ALRAIEAlarm A interrupt enable121ALRBIEAlarm B interrupt enable131WUTIEWakeup timer interrupt enable141TSIETime-stamp interrupt enable151ADD1HAdd 1 hour (summer time change)161SUB1HSubtract 1 hour (winter time change)171BKPBackup181COSELCalibration output selection191POLOutput polarity201OSELOutput selection212COECalibration output enable231ITSEtimestamp on internal event enable241ISRISRinitialization and status register0xC0x200x00000007ALRAWFAlarm A write flag01read-onlyALRBWFAlarm B write flag11read-onlyWUTWFWakeup timer write flag21read-onlySHPFShift operation pending31read-writeINITSInitialization status flag41read-onlyRSFRegisters synchronization flag51read-writeINITFInitialization flag61read-onlyINITInitialization mode71read-writeALRAFAlarm A flag81read-writeALRBFAlarm B flag91read-writeWUTFWakeup timer flag101read-writeTSFTime-stamp flag111read-writeTSOVFTime-stamp overflow flag121read-writeTAMP1FTamper detection flag131read-writeTAMP2FRTC_TAMP2 detection flag141read-writeTAMP3FRTC_TAMP3 detection flag151read-writeRECALPFRecalibration pending Flag161read-onlyITSFINTERNAL TIME-STAMP FLAG171read-writePRERPRERprescaler register0x100x20read-write0x007F00FFPREDIV_AAsynchronous prescaler factor167PREDIV_SSynchronous prescaler factor015WUTRWUTRwakeup timer register0x140x20read-write0x0000FFFFWUTWakeup auto-reload value bits016ALRMARALRMARalarm A register0x1C0x20read-write0x00000000MSK4Alarm A date mask311WDSELWeek day selection301DTDate tens in BCD format282DUDate units or day in BCD format244MSK3Alarm A hours mask231PMAM/PM notation221HTHour tens in BCD format202HUHour units in BCD format164MSK2Alarm A minutes mask151MNTMinute tens in BCD format123MNUMinute units in BCD format84MSK1Alarm A seconds mask71STSecond tens in BCD format43SUSecond units in BCD format04ALRMBRALRMBRalarm B register0x200x20read-write0x00000000MSK4Alarm B date mask311WDSELWeek day selection301DTDate tens in BCD format282DUDate units or day in BCD format244MSK3Alarm B hours mask231PMAM/PM notation221HTHour tens in BCD format202HUHour units in BCD format164MSK2Alarm B minutes mask151MNTMinute tens in BCD format123MNUMinute units in BCD format84MSK1Alarm B seconds mask71STSecond tens in BCD format43SUSecond units in BCD format04WPRWPRwrite protection register0x240x20write-only0x00000000KEYWrite protection key08SSRSSRsub second register0x280x20read-only0x00000000SSSub second value016SHIFTRSHIFTRshift control register0x2C0x20write-only0x00000000ADD1SAdd one second311SUBFSSubtract a fraction of a second015TSTRTSTRtime stamp time register0x300x20read-only0x00000000SUSecond units in BCD format04STSecond tens in BCD format43MNUMinute units in BCD format84MNTMinute tens in BCD format123HUHour units in BCD format164HTHour tens in BCD format202PMAM/PM notation221TSDRTSDRtime stamp date register0x340x20read-only0x00000000WDUWeek day units133MTMonth tens in BCD format121MUMonth units in BCD format84DTDate tens in BCD format42DUDate units in BCD format04TSSSRTSSSRtimestamp sub second register0x380x20read-only0x00000000SSSub second value016CALRCALRcalibration register0x3C0x20read-write0x00000000CALPIncrease frequency of RTC by 488.5 ppm151CALW8Use an 8-second calibration cycle period141CALW16Use a 16-second calibration cycle period131CALMCalibration minus09TAMPCRTAMPCRtamper configuration register0x400x20read-write0x00000000TAMP1ETamper 1 detection enable01TAMP1TRGActive level for tamper 111TAMPIETamper interrupt enable21TAMP2ETamper 2 detection enable31TAMP2TRGActive level for tamper 241TAMP3ETamper 3 detection enable51TAMP3TRGActive level for tamper 361TAMPTSActivate timestamp on tamper detection event71TAMPFREQTamper sampling frequency83TAMPFLTTamper filter count112TAMPPRCHTamper precharge duration132TAMPPUDISTAMPER pull-up disable151TAMP1IETamper 1 interrupt enable161TAMP1NOERASETamper 1 no erase171TAMP1MFTamper 1 mask flag181TAMP2IETamper 2 interrupt enable191TAMP2NOERASETamper 2 no erase201TAMP2MFTamper 2 mask flag211TAMP3IETamper 3 interrupt enable221TAMP3NOERASETamper 3 no erase231TAMP3MFTamper 3 mask flag241ALRMASSRALRMASSRalarm A sub second register0x440x20read-write0x00000000MASKSSMask the most-significant bits starting at this bit244SSSub seconds value015ALRMBSSRALRMBSSRalarm B sub second register0x480x20read-write0x00000000MASKSSMask the most-significant bits starting at this bit244SSSub seconds value015ORORoption register0x4C0x20read-write0x00000000RTC_ALARM_TYPERTC_ALARM on PC13 output type01RTC_OUT_RMPRTC_OUT remap11BKP0RBKP0Rbackup register0x500x20read-write0x00000000BKPBKP032BKP1RBKP1Rbackup register0x540x20read-write0x00000000BKPBKP032BKP2RBKP2Rbackup register0x580x20read-write0x00000000BKPBKP032BKP3RBKP3Rbackup register0x5C0x20read-write0x00000000BKPBKP032BKP4RBKP4Rbackup register0x600x20read-write0x00000000BKPBKP032BKP5RBKP5Rbackup register0x640x20read-write0x00000000BKPBKP032BKP6RBKP6Rbackup register0x680x20read-write0x00000000BKPBKP032BKP7RBKP7Rbackup register0x6C0x20read-write0x00000000BKPBKP032BKP8RBKP8Rbackup register0x700x20read-write0x00000000BKPBKP032BKP9RBKP9Rbackup register0x740x20read-write0x00000000BKPBKP032BKP10RBKP10Rbackup register0x780x20read-write0x00000000BKPBKP032BKP11RBKP11Rbackup register0x7C0x20read-write0x00000000BKPBKP032BKP12RBKP12Rbackup register0x800x20read-write0x00000000BKPBKP032BKP13RBKP13Rbackup register0x840x20read-write0x00000000BKPBKP032BKP14RBKP14Rbackup register0x880x20read-write0x00000000BKPBKP032BKP15RBKP15Rbackup register0x8C0x20read-write0x00000000BKPBKP032BKP16RBKP16Rbackup register0x900x20read-write0x00000000BKPBKP032BKP17RBKP17Rbackup register0x940x20read-write0x00000000BKPBKP032BKP18RBKP18Rbackup register0x980x20read-write0x00000000BKPBKP032BKP19RBKP19Rbackup register0x9C0x20read-write0x00000000BKPBKP032DBGMCUDebug supportDBGMCU0xE00420000x00x400registersIDCODEIDCODEMCU Device ID Code Register0x00x20read-only0x0DEV_IDDevice Identifier012REV_IDRevision Identifier1616CRCRDebug MCU Configuration Register0x40x20read-write0x0DBG_SLEEPDebug Sleep Mode01DBG_STOPDebug Stop Mode11DBG_STANDBYDebug Standby Mode21TRACE_IOENTrace port and clock enable51TRGOENExternal trigger output enable281APB1FZR1APB1FZR1APB1 Low Freeze Register CPU10x3C0x20read-write0x0DBG_TIMER2_STOPDebug Timer 2 stopped when Core is halted01DBG_RTC_STOPRTC counter stopped when core is halted101DBG_WWDG_STOPWWDG counter stopped when core is halted111DBG_IWDG_STOPIWDG counter stopped when core is halted121DBG_I2C1_STOPDebug I2C1 SMBUS timeout stopped when Core is halted211DBG_I2C3_STOPDebug I2C3 SMBUS timeout stopped when core is halted231DBG_LPTIM1_STOPDebug LPTIM1 stopped when Core is halted311C2AP_B1FZR1C2AP_B1FZR1APB1 Low Freeze Register CPU20x400x20read-write0x0DBG_LPTIM2_STOPLPTIM2 counter stopped when core is halted01DBG_RTC_STOPRTC counter stopped when core is halted101DBG_IWDG_STOPIWDG stopped when core is halted121DBG_I2C1_STOPI2C1 SMBUS timeout stopped when core is halted211DBG_I2C3_STOPI2C3 SMBUS timeout stopped when core is halted231DBG_LPTIM1_STOPLPTIM1 counter stopped when core is halted311APB1FZR2APB1FZR2APB1 High Freeze Register CPU10x440x20read-write0x0DBG_LPTIM2_STOPLPTIM2 counter stopped when core is halted51C2APB1FZR2C2APB1FZR2APB1 High Freeze Register CPU20x480x20read-write0x0DBG_LPTIM2_STOPLPTIM2 counter stopped when core is halted51APB2FZRAPB2FZRAPB2 Freeze Register CPU10x4C0x20read-write0x0DBG_TIM1_STOPTIM1 counter stopped when core is halted111DBG_TIM16_STOPTIM16 counter stopped when core is halted171DBG_TIM17_STOPTIM17 counter stopped when core is halted181C2APB2FZRC2APB2FZRAPB2 Freeze Register CPU2C2APB1FZR20x480x20read-write0x0DBG_TIM1_STOPTIM1 counter stopped when core is halted111DBG_TIM16_STOPTIM16 counter stopped when core is halted171DBG_TIM17_STOPTIM17 counter stopped when core is halted181PKAPKAPKA0x580020000x00x2000registersPKAPrivate key accelerator interrupt29CRCRControl register0x00x20read-write0x00000000ADDRERRIEAddress error interrupt enable201RAMERRIERAM error interrupt enable191PROCENDIEEnd of operation interrupt enable171MODEPKA Operation Mode86SECLVLSecurity Enable21STARTStart the operation11ENPeripheral Enable01SRSRPKA status register0x40x20read-only0x00000000ADDRERRFAddress error flag201RAMERRFRAM error flag191PROCENDFPKA End of Operation flag171BUSYPKA Operation in progress161CLRFRCLRFRPKA clear flag register0x80x20read-write0x00000000ADDRERRFCClear Address error flag201RAMERRFCClear RAM error flag191PROCENDFCClear PKA End of Operation flag171VERRVERRPKA version register0x1FF40x20read-only0x00000010MINREVMinor revision04MAJREVMajor revision44IPIDRIPIDRPKA identification register0x1FF80x20read-only0x00170061IDIdentification Code032SIDRSIDRPKA size ID register0x1FFC0x20read-only0xA3C5DD08SIDSide Identification Code032IPCCIPCCIPCC0x58000C000x00x400registersIPCC_C1_RX_ITIPCC CPU1 RX occupied interrupt44IPCC_C1_TX_ITIPCC CPU1 TX free interrupt45C1CRC1CRControl register CPU10x00x20read-write0x00000000TXFIEprocessor 1 Transmit channel free interrupt enable161RXOIEprocessor 1 Receive channel occupied interrupt enable01C1MRC1MRMask register CPU10x40x20read-write0xFFFFFFFFCH6FMprocessor 1 Transmit channel 6 free interrupt mask211CH5FMprocessor 1 Transmit channel 5 free interrupt mask201CH4FMprocessor 1 Transmit channel 4 free interrupt mask191CH3FMprocessor 1 Transmit channel 3 free interrupt mask181CH2FMprocessor 1 Transmit channel 2 free interrupt mask171CH1FMprocessor 1 Transmit channel 1 free interrupt mask161CH6OMprocessor 1 Receive channel 6 occupied interrupt enable51CH5OMprocessor 1 Receive channel 5 occupied interrupt enable41CH4OMprocessor 1 Receive channel 4 occupied interrupt enable31CH3OMprocessor 1 Receive channel 3 occupied interrupt enable21CH2OMprocessor 1 Receive channel 2 occupied interrupt enable11CH1OMprocessor 1 Receive channel 1 occupied interrupt enable01C1SCRC1SCRStatus Set or Clear register CPU10x80x20write-only0x00000000CH6Sprocessor 1 Transmit channel 6 status set211CH5Sprocessor 1 Transmit channel 5 status set201CH4Sprocessor 1 Transmit channel 4 status set191CH3Sprocessor 1 Transmit channel 3 status set181CH2Sprocessor 1 Transmit channel 2 status set171CH1Sprocessor 1 Transmit channel 1 status set161CH6Cprocessor 1 Receive channel 6 status clear51CH5Cprocessor 1 Receive channel 5 status clear41CH4Cprocessor 1 Receive channel 4 status clear31CH3Cprocessor 1 Receive channel 3 status clear21CH2Cprocessor 1 Receive channel 2 status clear11CH1Cprocessor 1 Receive channel 1 status clear01C1TO2SRC1TO2SRCPU1 to CPU2 status register0xC0x20read-only0x00000000CH6Fprocessor 1 transmit to process 2 Receive channel 6 status flag51CH5Fprocessor 1 transmit to process 2 Receive channel 5 status flag41CH4Fprocessor 1 transmit to process 2 Receive channel 4 status flag31CH3Fprocessor 1 transmit to process 2 Receive channel 3 status flag21CH2Fprocessor 1 transmit to process 2 Receive channel 2 status flag11CH1Fprocessor 1 transmit to process 2 Receive channel 1 status flag01C2CRC2CRControl register CPU20x100x20read-write0x00000000TXFIEprocessor 2 Transmit channel free interrupt enable161RXOIEprocessor 2 Receive channel occupied interrupt enable01C2MRC2MRMask register CPU20x140x20read-write0xFFFFFFFFCH6FMprocessor 2 Transmit channel 6 free interrupt mask211CH5FMprocessor 2 Transmit channel 5 free interrupt mask201CH4FMprocessor 2 Transmit channel 4 free interrupt mask191CH3FMprocessor 2 Transmit channel 3 free interrupt mask181CH2FMprocessor 2 Transmit channel 2 free interrupt mask171CH1FMprocessor 2 Transmit channel 1 free interrupt mask161CH6OMprocessor 2 Receive channel 6 occupied interrupt enable51CH5OMprocessor 2 Receive channel 5 occupied interrupt enable41CH4OMprocessor 2 Receive channel 4 occupied interrupt enable31CH3OMprocessor 2 Receive channel 3 occupied interrupt enable21CH2OMprocessor 2 Receive channel 2 occupied interrupt enable11CH1OMprocessor 2 Receive channel 1 occupied interrupt enable01C2SCRC2SCRStatus Set or Clear register CPU20x180x20write-only0x00000000CH6Sprocessor 2 Transmit channel 6 status set211CH5Sprocessor 2 Transmit channel 5 status set201CH4Sprocessor 2 Transmit channel 4 status set191CH3Sprocessor 2 Transmit channel 3 status set181CH2Sprocessor 2 Transmit channel 2 status set171CH1Sprocessor 2 Transmit channel 1 status set161CH6Cprocessor 2 Receive channel 6 status clear51CH5Cprocessor 2 Receive channel 5 status clear41CH4Cprocessor 2 Receive channel 4 status clear31CH3Cprocessor 2 Receive channel 3 status clear21CH2Cprocessor 2 Receive channel 2 status clear11CH1Cprocessor 2 Receive channel 1 status clear01C2TOC1SRC2TOC1SRCPU2 to CPU1 status register0x1C0x20read-only0x00000000CH6Fprocessor 2 transmit to process 1 Receive channel 6 status flag51CH5Fprocessor 2 transmit to process 1 Receive channel 5 status flag41CH4Fprocessor 2 transmit to process 1 Receive channel 4 status flag31CH3Fprocessor 2 transmit to process 1 Receive channel 3 status flag21CH2Fprocessor 2 transmit to process 1 Receive channel 2 status flag11CH1Fprocessor 2 transmit to process 1 Receive channel 1 status flag01HWCFGRHWCFGRIPCC Hardware configuration register0x3F00x20read-only0x00000006CHANNELSNumber of channels per CPU supported by the IP, range 1 to 1608VERRVERRIPCC version register0x3F40x20read-only0x00000010MAJREVMajor Revision44MINREVMinor Revision04IPIDRIPIDRIPCC indentification register0x3F80x20read-only0x00100071IPIDIdentification Code032SIDRSIDRIPCC size indentification register0x3FC0x20read-only0xA3C5DD01SIDSize Identification Code032EXTIExternal interrupt/event controllerEXTI0x580008000x00x400registersPVDPVD through EXTI[16] (C1IMR2[20])1EXTI0EXTI line 0 interrupt through EXTI[0]6EXTI1EXTI line 0 interrupt through EXTI[1]7EXTI2EXTI line 0 interrupt through EXTI[2]8EXTI3EXTI line 0 interrupt through EXTI[3]9EXTI4EXTI line 0 interrupt through EXTI[4]10C2SEVCPU2 SEV through EXTI[40]21EXTI5_9EXTI line [9:5] interrupt through EXTI[9:5]23EXTI10_15EXTI line [15:10] interrupt through EXTI[15:10]40RTSR1RTSR1rising trigger selection register0x00x20read-write0x00000000RTRising trigger event configuration bit of Configurable Event input022RT_31Rising trigger event configuration bit of Configurable Event input311FTSR1FTSR1falling trigger selection register0x40x20read-write0x00000000FTFalling trigger event configuration bit of Configurable Event input022FT_31Falling trigger event configuration bit of Configurable Event input311SWIER1SWIER1software interrupt event register0x80x20read-write0x00000000SWISoftware interrupt on event022SWI_31Software interrupt on event311PR1PR1EXTI pending register0xC0x20read-write0x00000000PIFConfigurable event inputs Pending bit022PIF_31Configurable event inputs Pending bit311RTSR2RTSR2rising trigger selection register0x200x20read-write0x00000000RT33Rising trigger event configuration bit of Configurable Event input11RT40_41Rising trigger event configuration bit of Configurable Event input82FTSR2FTSR2falling trigger selection register0x240x20read-write0x00000000FT33Falling trigger event configuration bit of Configurable Event input11FT40_41Falling trigger event configuration bit of Configurable Event input82SWIER2SWIER2software interrupt event register0x280x20read-write0x00000000SWI33Software interrupt on event11SWI40_41Software interrupt on event82PR2PR2pending register0x2C0x20read-write0x00000000PIF33Configurable event inputs x+32 Pending bit.11PIF40_41Configurable event inputs x+32 Pending bit.82C1IMR1C1IMR1CPUm wakeup with interrupt mask register0x800x20read-write0x7FC00000IMCPU(m) wakeup with interrupt Mask on Event input032C2IMR1C2IMR1CPUm wakeup with interrupt mask register0xC00x20read-write0x7FC00000IMCPU(m) wakeup with interrupt Mask on Event input032C1EMR1C1EMR1CPUm wakeup with event mask register0x840x20read-write0x00000000EM0_15CPU(m) Wakeup with event generation Mask on Event input016EM17_21CPU(m) Wakeup with event generation Mask on Event input175C2EMR1C2EMR1CPUm wakeup with event mask register0xC40x20read-write0x00000000EM0_15CPU(m) Wakeup with event generation Mask on Event input016EM17_21CPU(m) Wakeup with event generation Mask on Event input175C1IMR2C1IMR2CPUm wakeup with interrupt mask register0x900x20read-write0x0001FCFDIMCPUm Wakeup with interrupt Mask on Event input017C2IMR2C2IMR2CPUm wakeup with interrupt mask register0xD00x20read-write0x0001FCFDIMCPUm Wakeup with interrupt Mask on Event input017C1EMR2C1EMR2CPUm wakeup with event mask register0x940x20read-write0x00000000EMCPU(m) Wakeup with event generation Mask on Event input82C2EMR2C2EMR2CPUm wakeup with event mask register0xD40x20read-write0x00000000EMCPU(m) Wakeup with event generation Mask on Event input82HWCFGR5HWCFGR5Hardware configuration registers0x3E00x20read-only0x003EFFFFCPUEVENTHW configuration CPU event generation032HWCFGR6HWCFGR6Hardware configuration registers0x3DC0x20read-only0x00000300CPUEVENTHW configuration CPU event generation032HWCFGR7HWCFGR7EXTI Hardware configuration registers0x3D80x20read-only0x00000000CPUEVENTHW configuration CPU event generation032HWCFGR2HWCFGR2Hardware configuration registers0x3EC0x20read-only0x803FFFFFEVENT_TRGHW configuration event trigger type032HWCFGR3HWCFGR3Hardware configuration registers0x3E80x20read-only0x00000302EVENT_TRGHW configuration event trigger type032HWCFGR4HWCFGR4Hardware configuration registers0x3E40x20read-only0x00000000EVENT_TRGHW configuration event trigger type032HWCFGR1HWCFGR1Hardware configuration register 10x3F00x20read-only0x00003130NBEVENTSHW configuration number of event08NBCPUSHW configuration number of CPUs84CPUEVTENHW configuration of CPU(m) event output enable124VERRVERREXTI IP Version register0x3F40x20read-only0X00000020MINREVMinor Revision number04MAJREVMajor Revision number44IPIDRIPIDRIdentification register0x3F80x20read-only0x000E0001IPIDIP Identification032SIDRSIDRSize ID register0x3FC0x20read-only0xA3C5DD01SIDSize Identification032CRSClock recovery systemCRS0x400060000x00x400registersCRS_ITCRS interrupt42CRCRCRS control register0x00x20read-write0x00002000SYNCOKIESYNC event OK interrupt enable01SYNCWARNIESYNC warning interrupt enable11ERRIESynchronization or trimming error interrupt enable21ESYNCIEExpected SYNC interrupt enable31CENFrequency error counter enable51AUTOTRIMENAutomatic trimming enable61SWSYNCAutomatic trimming enable71TRIMHSI48 oscillator smooth trimming86CFGRCFGRCRS configuration register0x40x20read-write0x2022BB7FRELOADCounter reload value016FELIMFrequency error limit168SYNCDIVSYNCDIV243SYNCSRCSYNC signal source selection282SYNCPOLSYNC polarity selection311ISRISRCRS interrupt and status register0x80x20read-only0x00000000SYNCOKFSYNC event OK flag01SYNCWARNFSYNC warning flag11ERRFError flag21ESYNCFExpected SYNC flag31SYNCERRSYNC error81SYNCMISSSYNC missed91TRIMOVFTrimming overflow or underflow101FEDIRFrequency error direction151FECAPFrequency error capture1616ICRICRCRS interrupt flag clear register0xC0x20read-write0x00000000SYNCOKCSYNC event OK clear flag01SYNCWARNCwarning clear flag11ERRCError clear flag21ESYNCCExpected SYNC clear flag31USBUniversal serial bus full-speed device interfaceUSB0x400068000x00x800registersUSB_HPUSB high priority interrupt19USB_LPUSB low priority interrupt (including USB wakeup)20EP0REP0Rendpoint 0 register0x00x10read-write0x00000000EAEndpoint address04STAT_TXStatus bits, for transmission transfers42DTOG_TXData Toggle, for transmission transfers61CTR_TXCorrect Transfer for transmission71EP_KINDEndpoint kind81EP_TYPEEndpoint type92SETUPSetup transaction completed111STAT_RXStatus bits, for reception transfers122DTOG_RXData Toggle, for reception transfers141CTR_RXCorrect transfer for reception151EP1REP1Rendpoint 1 register0x40x10read-write0x00000000EAEndpoint address04STAT_TXStatus bits, for transmission transfers42DTOG_TXData Toggle, for transmission transfers61CTR_TXCorrect Transfer for transmission71EP_KINDEndpoint kind81EP_TYPEEndpoint type92SETUPSetup transaction completed111STAT_RXStatus bits, for reception transfers122DTOG_RXData Toggle, for reception transfers141CTR_RXCorrect transfer for reception151EP2REP2Rendpoint 2 register0x80x10read-write0x00000000EAEndpoint address04STAT_TXStatus bits, for transmission transfers42DTOG_TXData Toggle, for transmission transfers61CTR_TXCorrect Transfer for transmission71EP_KINDEndpoint kind81EP_TYPEEndpoint type92SETUPSetup transaction completed111STAT_RXStatus bits, for reception transfers122DTOG_RXData Toggle, for reception transfers141CTR_RXCorrect transfer for reception151EP3REP3Rendpoint 3 register0xC0x10read-write0x00000000EAEndpoint address04STAT_TXStatus bits, for transmission transfers42DTOG_TXData Toggle, for transmission transfers61CTR_TXCorrect Transfer for transmission71EP_KINDEndpoint kind81EP_TYPEEndpoint type92SETUPSetup transaction completed111STAT_RXStatus bits, for reception transfers122DTOG_RXData Toggle, for reception transfers141CTR_RXCorrect transfer for reception151EP4REP4Rendpoint 4 register0x100x10read-write0x00000000EAEndpoint address04STAT_TXStatus bits, for transmission transfers42DTOG_TXData Toggle, for transmission transfers61CTR_TXCorrect Transfer for transmission71EP_KINDEndpoint kind81EP_TYPEEndpoint type92SETUPSetup transaction completed111STAT_RXStatus bits, for reception transfers122DTOG_RXData Toggle, for reception transfers141CTR_RXCorrect transfer for reception151EP5REP5Rendpoint 5 register0x140x10read-write0x00000000EAEndpoint address04STAT_TXStatus bits, for transmission transfers42DTOG_TXData Toggle, for transmission transfers61CTR_TXCorrect Transfer for transmission71EP_KINDEndpoint kind81EP_TYPEEndpoint type92SETUPSetup transaction completed111STAT_RXStatus bits, for reception transfers122DTOG_RXData Toggle, for reception transfers141CTR_RXCorrect transfer for reception151EP6REP6Rendpoint 6 register0x180x10read-write0x00000000EAEndpoint address04STAT_TXStatus bits, for transmission transfers42DTOG_TXData Toggle, for transmission transfers61CTR_TXCorrect Transfer for transmission71EP_KINDEndpoint kind81EP_TYPEEndpoint type92SETUPSetup transaction completed111STAT_RXStatus bits, for reception transfers122DTOG_RXData Toggle, for reception transfers141CTR_RXCorrect transfer for reception151EP7REP7Rendpoint 7 register0x1C0x10read-write0x00000000EAEndpoint address04STAT_TXStatus bits, for transmission transfers42DTOG_TXData Toggle, for transmission transfers61CTR_TXCorrect Transfer for transmission71EP_KINDEndpoint kind81EP_TYPEEndpoint type92SETUPSetup transaction completed111STAT_RXStatus bits, for reception transfers122DTOG_RXData Toggle, for reception transfers141CTR_RXCorrect transfer for reception151CNTRCNTRcontrol register0x400x10read-write0x00000003FRESForce USB Reset01PDWNPower down11LPMODELow-power mode21FSUSPForce suspend31RESUMEResume request41L1RESUMELPM L1 Resume request51L1REQMLPM L1 state request interrupt mask71ESOFMExpected start of frame interrupt mask81SOFMStart of frame interrupt mask91RESETMUSB reset interrupt mask101SUSPMSuspend mode interrupt mask111WKUPMWakeup interrupt mask121ERRMError interrupt mask131PMAOVRMPacket memory area over / underrun interrupt mask141CTRMCorrect transfer interrupt mask151ISTRISTRinterrupt status register0x440x100x00000000EP_IDEndpoint Identifier04read-onlyDIRDirection of transaction41read-onlyL1REQLPM L1 state request71read-writeESOFExpected start frame81read-writeSOFstart of frame91read-writeRESETreset request101read-writeSUSPSuspend mode request111read-writeWKUPWakeup121read-writeERRError131read-writePMAOVRPacket memory area over / underrun141read-writeCTRCorrect transfer151read-onlyFNRFNRframe number register0x480x10read-only0x0000FNFrame number011LSOFLost SOF112LCKLocked131RXDMReceive data - line status141RXDPReceive data + line status151DADDRDADDRdevice address0x4C0x10read-write0x0000ADDDevice address07EFEnable function71BTABLEBTABLEBuffer table address0x500x10read-write0x0000BTABLEBuffer table313COUNT0_TXCOUNT0_TXTransmission byte count 00x520x10read-write0x0000COUNT0_TXTransmission byte count010COUNT1_TXCOUNT1_TXTransmission byte count 00x5A0x10read-write0x0000COUNT1_TXTransmission byte count010COUNT2_TXCOUNT2_TXTransmission byte count 00x620x10read-write0x0000COUNT2_TXTransmission byte count010COUNT3_TXCOUNT3_TXTransmission byte count 00x6A0x10read-write0x0000COUNT3_TXTransmission byte count010COUNT4_TXCOUNT4_TXTransmission byte count 00x720x10read-write0x0000COUNT4_TXTransmission byte count010COUNT5_TXCOUNT5_TXTransmission byte count 00x7A0x10read-write0x0000COUNT5_TXTransmission byte count010COUNT6_TXCOUNT6_TXTransmission byte count 00x820x10read-write0x0000COUNT6_TXTransmission byte count010COUNT7_TXCOUNT7_TXTransmission byte count 00x8A0x10read-write0x0000COUNT7_TXTransmission byte count010ADDR0_RXADDR0_RXReception buffer address 00x540x10read-write0x0000ADDR0_RXReception buffer address115ADDR1_RXADDR1_RXReception buffer address 00x5C0x10read-write0x0000ADDR1_RXReception buffer address115ADDR2_RXADDR2_RXReception buffer address 00x640x10read-write0x0000ADDR2_RXReception buffer address115ADDR3_RXADDR3_RXReception buffer address 00x6C0x10read-write0x0000ADDR3_RXReception buffer address115ADDR4_RXADDR4_RXReception buffer address 00x740x10read-write0x0000ADDR4_RXReception buffer address115ADDR5_RXADDR5_RXReception buffer address 00x7C0x10read-write0x0000ADDR5_RXReception buffer address115ADDR6_RXADDR6_RXReception buffer address 00x840x10read-write0x0000ADDR6_RXReception buffer address115ADDR7_RXADDR7_RXReception buffer address 00x8C0x10read-write0x0000ADDR7_RXReception buffer address115COUNT0_RXCOUNT0_RXReception byte count 00x560x100x0000COUNT0_RXReception byte count010read-onlyNUM_BLOCKNumber of blocks105read-writeBL_SIZEBlock size151read-writeCOUNT1_RXCOUNT1_RXReception byte count 00x5E0x100x0000COUNT1_RXReception byte count010read-onlyNUM_BLOCKNumber of blocks105read-writeBL_SIZEBlock size151read-writeCOUNT2_RXCOUNT2_RXReception byte count 00x660x100x0000COUNT2_RXReception byte count010read-onlyNUM_BLOCKNumber of blocks105read-writeBL_SIZEBlock size151read-writeCOUNT3_RXCOUNT3_RXReception byte count 00x6E0x100x0000COUNT3_RXReception byte count010read-onlyNUM_BLOCKNumber of blocks105read-writeBL_SIZEBlock size151read-writeCOUNT4_RXCOUNT4_RXReception byte count 00x760x100x0000COUNT4_RXReception byte count010read-onlyNUM_BLOCKNumber of blocks105read-writeBL_SIZEBlock size151read-writeCOUNT5_RXCOUNT5_RXReception byte count 00x7E0x100x0000COUNT5_RXReception byte count010read-onlyNUM_BLOCKNumber of blocks105read-writeBL_SIZEBlock size151read-writeCOUNT6_RXCOUNT6_RXReception byte count 00x860x100x0000COUNT6_RXReception byte count010read-onlyNUM_BLOCKNumber of blocks105read-writeBL_SIZEBlock size151read-writeCOUNT7_RXCOUNT7_RXReception byte count 00x8E0x100x0000COUNT7_RXReception byte count010read-onlyNUM_BLOCKNumber of blocks105read-writeBL_SIZEBlock size151read-writeLPMCSRLPMCSRcontrol and status registerADDR0_RX0x540x100x0000LPMENLPM support enable01read-writeLPMACKLPM Token acknowledge enable11read-writeREMWAKERemoteWake value31read-writeBESLBESL value44read-onlyBCDRBCDRBattery charging detector(0x580x100x0000BCDENBattery charging detector (BCD) enable01read-writeDCDENData contact detection (DCD) mode enable11read-writePDENPrimary detection (PD) mode enable21read-writeSDENSecondary detection (SD) mode enable31read-writeDCDETData contact detection (DCD) status41read-onlyPDETPrimary detection (PD) status51read-onlySDETSecondary detection (SD) status61read-onlyPS2DETDM pull-up detection status71read-onlyDPPUDP pull-up control151read-writeSCBSystem control blockSCB0xE000ED000x00x41registersCPUIDCPUIDCPUID base register0x00x20read-only0x410FC241RevisionRevision number04PartNoPart number of the processor412ConstantReads as 0xF164VariantVariant number204ImplementerImplementer code248ICSRICSRInterrupt control and state register0x40x20read-write0x00000000VECTACTIVEActive vector09RETTOBASEReturn to base level111VECTPENDINGPending vector127ISRPENDINGInterrupt pending flag221PENDSTCLRSysTick exception clear-pending bit251PENDSTSETSysTick exception set-pending bit261PENDSVCLRPendSV clear-pending bit271PENDSVSETPendSV set-pending bit281NMIPENDSETNMI set-pending bit.311VTORVTORVector table offset register0x80x20read-write0x00000000TBLOFFVector table base offset field921AIRCRAIRCRApplication interrupt and reset control register0xC0x20read-write0x00000000VECTRESETVECTRESET01VECTCLRACTIVEVECTCLRACTIVE11SYSRESETREQSYSRESETREQ21PRIGROUPPRIGROUP83ENDIANESSENDIANESS151VECTKEYSTATRegister key1616SCRSCRSystem control register0x100x20read-write0x00000000SLEEPONEXITSLEEPONEXIT11SLEEPDEEPSLEEPDEEP21SEVEONPENDSend Event on Pending bit41CCRCCRConfiguration and control register0x140x20read-write0x00000000NONBASETHRDENAConfigures how the processor enters Thread mode01USERSETMPENDUSERSETMPEND11UNALIGN__TRPUNALIGN_ TRP31DIV_0_TRPDIV_0_TRP41BFHFNMIGNBFHFNMIGN81STKALIGNSTKALIGN91SHPR1SHPR1System handler priority registers0x180x20read-write0x00000000PRI_4Priority of system handler 408PRI_5Priority of system handler 588PRI_6Priority of system handler 6168SHPR2SHPR2System handler priority registers0x1C0x20read-write0x00000000PRI_11Priority of system handler 11248SHPR3SHPR3System handler priority registers0x200x20read-write0x00000000PRI_14Priority of system handler 14168PRI_15Priority of system handler 15248SHCSRSHCSRSystem handler control and state register0x240x20read-write0x00000000MEMFAULTACTMemory management fault exception active bit01BUSFAULTACTBus fault exception active bit11USGFAULTACTUsage fault exception active bit31SVCALLACTSVC call active bit71MONITORACTDebug monitor active bit81PENDSVACTPendSV exception active bit101SYSTICKACTSysTick exception active bit111USGFAULTPENDEDUsage fault exception pending bit121MEMFAULTPENDEDMemory management fault exception pending bit131BUSFAULTPENDEDBus fault exception pending bit141SVCALLPENDEDSVC call pending bit151MEMFAULTENAMemory management fault enable bit161BUSFAULTENABus fault enable bit171USGFAULTENAUsage fault enable bit181CFSR_UFSR_BFSR_MMFSRCFSR_UFSR_BFSR_MMFSRConfigurable fault status register0x280x20read-write0x00000000IACCVIOLInstruction access violation flag11MUNSTKERRMemory manager fault on unstacking for a return from exception31MSTKERRMemory manager fault on stacking for exception entry.41MLSPERRMLSPERR51MMARVALIDMemory Management Fault Address Register (MMAR) valid flag71IBUSERRInstruction bus error81PRECISERRPrecise data bus error91IMPRECISERRImprecise data bus error101UNSTKERRBus fault on unstacking for a return from exception111STKERRBus fault on stacking for exception entry121LSPERRBus fault on floating-point lazy state preservation131BFARVALIDBus Fault Address Register (BFAR) valid flag151UNDEFINSTRUndefined instruction usage fault161INVSTATEInvalid state usage fault171INVPCInvalid PC load usage fault181NOCPNo coprocessor usage fault.191UNALIGNEDUnaligned access usage fault241DIVBYZERODivide by zero usage fault251HFSRHFSRHard fault status register0x2C0x20read-write0x00000000VECTTBLVector table hard fault11FORCEDForced hard fault301DEBUG_VTReserved for Debug use311MMFARMMFARMemory management fault address register0x340x20read-write0x00000000MMFARMemory management fault address032BFARBFARBus fault address register0x380x20read-write0x00000000BFARBus fault address032AFSRAFSRAuxiliary fault status register0x3C0x20read-write0x00000000IMPDEFImplementation defined032STKSysTick timerSTK0xE000E0100x00x11registersCTRLCTRLSysTick control and status register0x00x20read-write0X00000000ENABLECounter enable01TICKINTSysTick exception request enable11CLKSOURCEClock source selection21COUNTFLAGCOUNTFLAG161LOADLOADSysTick reload value register0x40x20read-write0X00000000RELOADRELOAD value024VALVALSysTick current value register0x80x20read-write0X00000000CURRENTCurrent counter value024CALIBCALIBSysTick calibration value register0xC0x20read-write0X00000000TENMSCalibration value024SKEWSKEW flag: Indicates whether the TENMS value is exact301NOREFNOREF flag. Reads as zero311MPUMemory protection unitMPU0xE000ED900x00x15registersMPU_TYPERMPU_TYPERMPU type register0x00x20read-only0X00000800SEPARATESeparate flag01DREGIONNumber of MPU data regions88IREGIONNumber of MPU instruction regions168MPU_CTRLMPU_CTRLMPU control register0x40x20read-only0X00000000ENABLEEnables the MPU01HFNMIENAEnables the operation of MPU during hard fault11PRIVDEFENAEnable priviliged software access to default memory map21MPU_RNRMPU_RNRMPU region number register0x80x20read-write0X00000000REGIONMPU region08MPU_RBARMPU_RBARMPU region base address register0xC0x20read-write0X00000000REGIONMPU region field04VALIDMPU region number valid41ADDRRegion base address field527MPU_RASRMPU_RASRMPU region attribute and size register0x100x20read-write0X00000000ENABLERegion enable bit.01SIZESize of the MPU protection region15SRDSubregion disable bits88Bmemory attribute161Cmemory attribute171SShareable memory attribute181TEXmemory attribute193APAccess permission243XNInstruction access disable bit281FPUFloting point unitFPU0xE000EF340x00xDregistersFPUFloating point unit interrupt54FPCCRFPCCRFloating-point context control register0x00x20read-write0x00000000LSPACTLSPACT01USERUSER11THREADTHREAD31HFRDYHFRDY41MMRDYMMRDY51BFRDYBFRDY61MONRDYMONRDY81LSPENLSPEN301ASPENASPEN311FPCARFPCARFloating-point context address register0x40x20read-write0x00000000ADDRESSLocation of unpopulated floating-point329FPSCRFPSCRFloating-point status control register0x80x20read-write0x00000000IOCInvalid operation cumulative exception bit01DZCDivision by zero cumulative exception bit.11OFCOverflow cumulative exception bit21UFCUnderflow cumulative exception bit31IXCInexact cumulative exception bit41IDCInput denormal cumulative exception bit.71RModeRounding Mode control field222FZFlush-to-zero mode control bit:241DNDefault NaN mode control bit251AHPAlternative half-precision control bit261VOverflow condition code flag281CCarry condition code flag291ZZero condition code flag301NNegative condition code flag311NVICNested Vectored Interrupt ControllerNVIC0xE000E1000x00x351registersISER0ISER0Interrupt Set-Enable Register0x00x20read-write0x00000000SETENASETENA032ISER1ISER1Interrupt Set-Enable Register0x40x20read-write0x00000000SETENASETENA032ICER0ICER0Interrupt Clear-Enable Register0x800x20read-write0x00000000CLRENACLRENA032ICER1ICER1Interrupt Clear-Enable Register0x840x20read-write0x00000000CLRENACLRENA032ISPR0ISPR0Interrupt Set-Pending Register0x1000x20read-write0x00000000SETPENDSETPEND032ISPR1ISPR1Interrupt Set-Pending Register0x1040x20read-write0x00000000SETPENDSETPEND032ICPR0ICPR0Interrupt Clear-Pending Register0x1800x20read-write0x00000000CLRPENDCLRPEND032ICPR1ICPR1Interrupt Clear-Pending Register0x1840x20read-write0x00000000CLRPENDCLRPEND032IABR0IABR0Interrupt Active Bit Register0x2000x20read-only0x00000000ACTIVEACTIVE032IABR1IABR1Interrupt Active Bit Register0x2040x20read-only0x00000000ACTIVEACTIVE032IPR0IPR0Interrupt Priority Register0x3000x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR1IPR1Interrupt Priority Register0x3040x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR2IPR2Interrupt Priority Register0x3080x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR3IPR3Interrupt Priority Register0x30C0x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR4IPR4Interrupt Priority Register0x3100x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR5IPR5Interrupt Priority Register0x3140x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR6IPR6Interrupt Priority Register0x3180x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR7IPR7Interrupt Priority Register0x31C0x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR8IPR8Interrupt Priority Register0x3200x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR9IPR9Interrupt Priority Register0x3240x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR10IPR10Interrupt Priority Register0x3280x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR11IPR11Interrupt Priority Register0x32C0x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR12IPR12Interrupt Priority Register0x3300x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR13IPR13Interrupt Priority Register0x3340x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR14IPR14Interrupt Priority Register0x3380x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR15IPR15Interrupt Priority Register0x33C0x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR16IPR16Interrupt Priority Register0x3400x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248IPR17IPR17Interrupt Priority Register0x3440x20read-write0x00000000IPR_N0IPR_N008IPR_N1IPR_N188IPR_N2IPR_N2168IPR_N3IPR_N3248NVIC_STIRNested vectored interrupt controllerNVIC0xE000EF000x00x5registersSTIRSTIRSoftware trigger interrupt register0x00x20read-write0x00000000INTIDSoftware generated interrupt ID09SCB_ACTRLSystem control block ACTLRSCB0xE000E0080x00x5registersACTRLACTRLAuxiliary control register0x00x20read-write0x00000000DISMCYCINTDISMCYCINT01DISDEFWBUFDISDEFWBUF11DISFOLDDISFOLD21DISFPCADISFPCA81DISOOFPDISOOFP91FPU_CPACRFloating point unit CPACRFPU0xE000ED880x00x5registersCPACRCPACRCoprocessor access control register0x00x20read-write0x0000000CPCP204