d92b0a82cc
"A long time ago in a galaxy far, far away...." we started NFC subsystem refactoring. Starring: - @gornekich - NFC refactoring project lead, architect, senior developer - @gsurkov - architect, senior developer - @RebornedBrain - senior developer Supporting roles: - @skotopes, @DrZlo13, @hedger - general architecture advisors, code review - @Astrrra, @doomwastaken, @Hellitron, @ImagineVagon333 - quality assurance Special thanks: @bettse, @pcunning, @nxv, @noproto, @AloneLiberty and everyone else who has been helping us all this time and contributing valuable knowledges, ideas and source code.
382 lines
14 KiB
C
382 lines
14 KiB
C
#include "digital_sequence.h"
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#include "digital_signal_i.h"
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#include <furi.h>
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#include <furi_hal_bus.h>
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#include <stm32wbxx_ll_dma.h>
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#include <stm32wbxx_ll_tim.h>
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/**
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* To enable debug output on an additional pin, set DIGITAL_SIGNAL_DEBUG_OUTPUT_PIN to the required
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* GpioPin variable. It can be passed at compile time via the --extra-define fbt switch.
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* NOTE: This pin must be on the same GPIO port as the main pin.
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*
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* Example:
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* ./fbt --extra-define=DIGITAL_SIGNAL_DEBUG_OUTPUT_PIN=gpio_ext_pb3
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*/
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#define TAG "DigitalSequence"
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/* Special value used to indicate the end of DMA ring buffer. */
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#define DIGITAL_SEQUENCE_TIMER_MAX 0xFFFFFFFFUL
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/* Time to wait in loops before returning */
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#define DIGITAL_SEQUENCE_LOCK_WAIT_MS 10UL
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#define DIGITAL_SEQUENCE_LOCK_WAIT_TICKS (DIGITAL_SEQUENCE_LOCK_WAIT_MS * 1000 * 64)
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#define DIGITAL_SEQUENCE_GPIO_BUFFER_SIZE 2
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/* Maximum capacity of the DMA ring buffer. */
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#define DIGITAL_SEQUENCE_RING_BUFFER_SIZE 128
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#define DIGITAL_SEQUENCE_RING_BUFFER_MIN_FREE_SIZE 2
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/* Maximum amount of registered signals. */
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#define DIGITAL_SEQUENCE_BANK_SIZE 32
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typedef enum {
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DigitalSequenceStateIdle,
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DigitalSequenceStateActive,
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} DigitalSequenceState;
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typedef struct {
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uint32_t data[DIGITAL_SEQUENCE_RING_BUFFER_SIZE];
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uint32_t write_pos;
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uint32_t read_pos;
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} DigitalSequenceRingBuffer;
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typedef uint32_t DigitalSequenceGpioBuffer[DIGITAL_SEQUENCE_GPIO_BUFFER_SIZE];
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typedef const DigitalSignal* DigitalSequenceSignalBank[DIGITAL_SEQUENCE_BANK_SIZE];
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struct DigitalSequence {
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const GpioPin* gpio;
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uint32_t size;
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uint32_t max_size;
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uint8_t* data;
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LL_DMA_InitTypeDef dma_config_gpio;
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LL_DMA_InitTypeDef dma_config_timer;
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DigitalSequenceGpioBuffer gpio_buf;
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DigitalSequenceRingBuffer timer_buf;
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DigitalSequenceSignalBank signals;
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DigitalSequenceState state;
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};
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DigitalSequence* digital_sequence_alloc(uint32_t size, const GpioPin* gpio) {
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furi_assert(size);
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furi_assert(gpio);
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DigitalSequence* sequence = malloc(sizeof(DigitalSequence));
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sequence->gpio = gpio;
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sequence->max_size = size;
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sequence->data = malloc(sequence->max_size);
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sequence->dma_config_gpio.PeriphOrM2MSrcAddress = (uint32_t)&gpio->port->BSRR;
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sequence->dma_config_gpio.MemoryOrM2MDstAddress = (uint32_t)sequence->gpio_buf;
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sequence->dma_config_gpio.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
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sequence->dma_config_gpio.Mode = LL_DMA_MODE_CIRCULAR;
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sequence->dma_config_gpio.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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sequence->dma_config_gpio.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
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sequence->dma_config_gpio.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
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sequence->dma_config_gpio.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD;
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sequence->dma_config_gpio.NbData = DIGITAL_SEQUENCE_GPIO_BUFFER_SIZE;
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sequence->dma_config_gpio.PeriphRequest = LL_DMAMUX_REQ_TIM2_UP;
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sequence->dma_config_gpio.Priority = LL_DMA_PRIORITY_VERYHIGH;
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sequence->dma_config_timer.PeriphOrM2MSrcAddress = (uint32_t)&TIM2->ARR;
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sequence->dma_config_timer.MemoryOrM2MDstAddress = (uint32_t)sequence->timer_buf.data;
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sequence->dma_config_timer.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
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sequence->dma_config_timer.Mode = LL_DMA_MODE_CIRCULAR;
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sequence->dma_config_timer.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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sequence->dma_config_timer.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
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sequence->dma_config_timer.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
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sequence->dma_config_timer.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD;
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sequence->dma_config_timer.NbData = DIGITAL_SEQUENCE_RING_BUFFER_SIZE;
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sequence->dma_config_timer.PeriphRequest = LL_DMAMUX_REQ_TIM2_UP;
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sequence->dma_config_timer.Priority = LL_DMA_PRIORITY_HIGH;
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return sequence;
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}
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void digital_sequence_free(DigitalSequence* sequence) {
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furi_assert(sequence);
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free(sequence->data);
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free(sequence);
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}
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void digital_sequence_register_signal(
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DigitalSequence* sequence,
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uint8_t signal_index,
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const DigitalSignal* signal) {
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furi_assert(sequence);
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furi_assert(signal);
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furi_assert(signal_index < DIGITAL_SEQUENCE_BANK_SIZE);
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sequence->signals[signal_index] = signal;
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}
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void digital_sequence_add_signal(DigitalSequence* sequence, uint8_t signal_index) {
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furi_assert(sequence);
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furi_assert(signal_index < DIGITAL_SEQUENCE_BANK_SIZE);
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furi_assert(sequence->size < sequence->max_size);
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sequence->data[sequence->size++] = signal_index;
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}
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static inline void digital_sequence_start_dma(DigitalSequence* sequence) {
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furi_assert(sequence);
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LL_DMA_Init(DMA1, LL_DMA_CHANNEL_1, &sequence->dma_config_gpio);
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LL_DMA_Init(DMA1, LL_DMA_CHANNEL_2, &sequence->dma_config_timer);
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LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
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LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
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}
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static inline void digital_sequence_stop_dma() {
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LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
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LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_2);
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LL_DMA_ClearFlag_TC1(DMA1);
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LL_DMA_ClearFlag_TC2(DMA1);
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}
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static inline void digital_sequence_start_timer() {
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furi_hal_bus_enable(FuriHalBusTIM2);
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LL_TIM_SetCounterMode(TIM2, LL_TIM_COUNTERMODE_UP);
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LL_TIM_SetClockDivision(TIM2, LL_TIM_CLOCKDIVISION_DIV1);
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LL_TIM_SetPrescaler(TIM2, 0);
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LL_TIM_SetAutoReload(TIM2, DIGITAL_SEQUENCE_TIMER_MAX);
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LL_TIM_SetCounter(TIM2, 0);
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LL_TIM_EnableCounter(TIM2);
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LL_TIM_EnableUpdateEvent(TIM2);
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LL_TIM_EnableDMAReq_UPDATE(TIM2);
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LL_TIM_GenerateEvent_UPDATE(TIM2);
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}
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static void digital_sequence_stop_timer() {
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LL_TIM_DisableCounter(TIM2);
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LL_TIM_DisableUpdateEvent(TIM2);
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LL_TIM_DisableDMAReq_UPDATE(TIM2);
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furi_hal_bus_disable(FuriHalBusTIM2);
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}
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static inline void digital_sequence_init_gpio_buffer(
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DigitalSequence* sequence,
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const DigitalSignal* first_signal) {
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const uint32_t bit_set = sequence->gpio->pin << GPIO_BSRR_BS0_Pos
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#ifdef DIGITAL_SIGNAL_DEBUG_OUTPUT_PIN
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| DIGITAL_SIGNAL_DEBUG_OUTPUT_PIN.pin << GPIO_BSRR_BS0_Pos
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#endif
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;
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const uint32_t bit_reset = sequence->gpio->pin << GPIO_BSRR_BR0_Pos
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#ifdef DIGITAL_SIGNAL_DEBUG_OUTPUT_PIN
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| DIGITAL_SIGNAL_DEBUG_OUTPUT_PIN.pin << GPIO_BSRR_BR0_Pos
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#endif
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;
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if(first_signal->start_level) {
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sequence->gpio_buf[0] = bit_set;
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sequence->gpio_buf[1] = bit_reset;
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} else {
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sequence->gpio_buf[0] = bit_reset;
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sequence->gpio_buf[1] = bit_set;
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}
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}
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static inline void digital_sequence_finish(DigitalSequence* sequence) {
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if(sequence->state == DigitalSequenceStateActive) {
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const uint32_t prev_timer = DWT->CYCCNT;
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do {
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/* Special value has been loaded into the timer, signaling the end of transmission. */
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if(TIM2->ARR == DIGITAL_SEQUENCE_TIMER_MAX) {
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break;
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}
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if(DWT->CYCCNT - prev_timer > DIGITAL_SEQUENCE_LOCK_WAIT_TICKS) {
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DigitalSequenceRingBuffer* dma_buffer = &sequence->timer_buf;
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dma_buffer->read_pos = DIGITAL_SEQUENCE_RING_BUFFER_SIZE -
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LL_DMA_GetDataLength(DMA1, LL_DMA_CHANNEL_2);
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FURI_LOG_D(
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TAG,
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"[SEQ] hung %lu ms in finish (ARR 0x%08lx, read %lu, write %lu)",
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DIGITAL_SEQUENCE_LOCK_WAIT_MS,
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TIM2->ARR,
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dma_buffer->read_pos,
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dma_buffer->write_pos);
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break;
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}
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} while(true);
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}
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digital_sequence_stop_timer();
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digital_sequence_stop_dma();
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}
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static inline void digital_sequence_enqueue_period(DigitalSequence* sequence, uint32_t length) {
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DigitalSequenceRingBuffer* dma_buffer = &sequence->timer_buf;
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if(sequence->state == DigitalSequenceStateActive) {
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const uint32_t prev_timer = DWT->CYCCNT;
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do {
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dma_buffer->read_pos =
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DIGITAL_SEQUENCE_RING_BUFFER_SIZE - LL_DMA_GetDataLength(DMA1, LL_DMA_CHANNEL_2);
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const uint32_t size_free = (DIGITAL_SEQUENCE_RING_BUFFER_SIZE + dma_buffer->read_pos -
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dma_buffer->write_pos) %
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DIGITAL_SEQUENCE_RING_BUFFER_SIZE;
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if(size_free > DIGITAL_SEQUENCE_RING_BUFFER_MIN_FREE_SIZE) {
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break;
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}
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if(DWT->CYCCNT - prev_timer > DIGITAL_SEQUENCE_LOCK_WAIT_TICKS) {
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FURI_LOG_D(
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TAG,
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"[SEQ] hung %lu ms in queue (ARR 0x%08lx, read %lu, write %lu)",
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DIGITAL_SEQUENCE_LOCK_WAIT_MS,
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TIM2->ARR,
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dma_buffer->read_pos,
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dma_buffer->write_pos);
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break;
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}
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if(TIM2->ARR == DIGITAL_SEQUENCE_TIMER_MAX) {
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FURI_LOG_D(
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TAG,
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"[SEQ] buffer underrun in queue (ARR 0x%08lx, read %lu, write %lu)",
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TIM2->ARR,
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dma_buffer->read_pos,
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dma_buffer->write_pos);
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break;
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}
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} while(true);
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}
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dma_buffer->data[dma_buffer->write_pos] = length;
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dma_buffer->write_pos += 1;
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dma_buffer->write_pos %= DIGITAL_SEQUENCE_RING_BUFFER_SIZE;
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dma_buffer->data[dma_buffer->write_pos] = DIGITAL_SEQUENCE_TIMER_MAX;
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}
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static inline void digital_sequence_timer_buffer_reset(DigitalSequence* sequence) {
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sequence->timer_buf.data[0] = DIGITAL_SEQUENCE_TIMER_MAX;
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sequence->timer_buf.read_pos = 0;
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sequence->timer_buf.write_pos = 0;
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}
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void digital_sequence_transmit(DigitalSequence* sequence) {
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furi_assert(sequence);
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furi_assert(sequence->size);
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furi_assert(sequence->state == DigitalSequenceStateIdle);
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FURI_CRITICAL_ENTER();
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furi_hal_gpio_init(sequence->gpio, GpioModeOutputPushPull, GpioPullNo, GpioSpeedVeryHigh);
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#ifdef DIGITAL_SIGNAL_DEBUG_OUTPUT_PIN
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furi_hal_gpio_init(
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&DIGITAL_SIGNAL_DEBUG_OUTPUT_PIN, GpioModeOutputPushPull, GpioPullNo, GpioSpeedVeryHigh);
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#endif
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const DigitalSignal* signal_current = sequence->signals[sequence->data[0]];
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digital_sequence_init_gpio_buffer(sequence, signal_current);
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int32_t remainder_ticks = 0;
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uint32_t reload_value_carry = 0;
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uint32_t next_signal_index = 1;
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for(;;) {
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const DigitalSignal* signal_next =
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(next_signal_index < sequence->size) ?
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sequence->signals[sequence->data[next_signal_index++]] :
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NULL;
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for(uint32_t i = 0; i < signal_current->size; i++) {
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const bool is_last_value = (i == signal_current->size - 1);
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const uint32_t reload_value = signal_current->data[i] + reload_value_carry;
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reload_value_carry = 0;
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if(is_last_value) {
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if(signal_next != NULL) {
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/* Special case: signal boundary. Depending on whether the adjacent levels are equal or not,
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* they will be combined to a single one or handled separately. */
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const bool end_level = signal_current->start_level ^
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((signal_current->size % 2) == 0);
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/* If the adjacent levels are equal, carry the current period duration over to the next signal. */
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if(end_level == signal_next->start_level) {
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reload_value_carry = reload_value;
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}
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} else {
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/** Special case: during the last period of the last signal, hold the output level indefinitely.
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* @see digital_signal.h
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*
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* Setting reload_value_carry to a non-zero value will prevent the respective period from being
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* added to the DMA ring buffer. */
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reload_value_carry = 1;
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}
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}
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/* A non-zero reload_value_carry means that the level was the same on the both sides of the signal boundary
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* and the two respective periods were combined to one. */
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if(reload_value_carry == 0) {
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digital_sequence_enqueue_period(sequence, reload_value);
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}
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if(sequence->state == DigitalSequenceStateIdle) {
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const bool is_buffer_filled = sequence->timer_buf.write_pos >=
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(DIGITAL_SEQUENCE_RING_BUFFER_SIZE -
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DIGITAL_SEQUENCE_RING_BUFFER_MIN_FREE_SIZE);
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const bool is_end_of_data = (signal_next == NULL) && is_last_value;
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if(is_buffer_filled || is_end_of_data) {
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digital_sequence_start_dma(sequence);
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digital_sequence_start_timer();
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sequence->state = DigitalSequenceStateActive;
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}
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}
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}
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/* Exit the loop here when no further signals are available */
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if(signal_next == NULL) break;
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/* Prevent the rounding error from accumulating by distributing it across multiple periods. */
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remainder_ticks += signal_current->remainder;
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if(remainder_ticks >= DIGITAL_SIGNAL_T_TIM_DIV2) {
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remainder_ticks -= DIGITAL_SIGNAL_T_TIM;
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reload_value_carry += 1;
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}
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signal_current = signal_next;
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};
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digital_sequence_finish(sequence);
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digital_sequence_timer_buffer_reset(sequence);
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FURI_CRITICAL_EXIT();
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sequence->state = DigitalSequenceStateIdle;
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}
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void digital_sequence_clear(DigitalSequence* sequence) {
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furi_assert(sequence);
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sequence->size = 0;
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}
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