389ff92cc1
* Makefile, Scripts: new linter * About: remove ID from IC * Firmware: remove double define for DIVC/DIVR * Scripts: check folder names too. Docker: replace syntax check with make lint. * Reformat Sources and Migrate to new file naming convention * Docker: symlink clang-format-12 to clang-format * Add coding style guide
232 lines
11 KiB
C
232 lines
11 KiB
C
/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file hw_conf.h
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* @author MCD Application Team
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* @brief Configuration of hardware interface
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under Ultimate Liberty license
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* SLA0044, the "License"; You may not use this file except in compliance with
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* the License. You may obtain a copy of the License at:
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* www.st.com/SLA0044
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef HW_CONF_H
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#define HW_CONF_H
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#include "FreeRTOSConfig.h"
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/******************************************************************************
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* Semaphores
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* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
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*****************************************************************************/
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/**
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* Index of the semaphore used the prevent conflicts after standby sleep.
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* Each CPUs takes this semaphore at standby wakeup until conclicting elements are restored.
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*/
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#define CFG_HW_PWR_STANDBY_SEMID 10
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/**
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* The CPU2 may be configured to store the Thread persistent data either in internal NVM storage on CPU2 or in
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* SRAM2 buffer provided by the user application. This can be configured with the system command SHCI_C2_Config()
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* When the CPU2 is requested to store persistent data in SRAM2, it can write data in this buffer at any time when needed.
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* In order to read consistent data with the CPU1 from the SRAM2 buffer, the flow should be:
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* + CPU1 takes CFG_HW_THREAD_NVM_SRAM_SEMID semaphore
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* + CPU1 reads all persistent data from SRAM2 (most of the time, the goal is to write these data into an NVM managed by CPU1)
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* + CPU1 releases CFG_HW_THREAD_NVM_SRAM_SEMID semaphore
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* CFG_HW_THREAD_NVM_SRAM_SEMID semaphore makes sure CPU2 does not update the persistent data in SRAM2 at the same time CPU1 is reading them.
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* There is no timing constraint on how long this semaphore can be kept.
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*/
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#define CFG_HW_THREAD_NVM_SRAM_SEMID 9
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/**
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* The CPU2 may be configured to store the BLE persistent data either in internal NVM storage on CPU2 or in
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* SRAM2 buffer provided by the user application. This can be configured with the system command SHCI_C2_Config()
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* When the CPU2 is requested to store persistent data in SRAM2, it can write data in this buffer at any time when needed.
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* In order to read consistent data with the CPU1 from the SRAM2 buffer, the flow should be:
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* + CPU1 takes CFG_HW_BLE_NVM_SRAM_SEMID semaphore
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* + CPU1 reads all persistent data from SRAM2 (most of the time, the goal is to write these data into an NVM managed by CPU1)
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* + CPU1 releases CFG_HW_BLE_NVM_SRAM_SEMID semaphore
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* CFG_HW_BLE_NVM_SRAM_SEMID semaphore makes sure CPU2 does not update the persistent data in SRAM2 at the same time CPU1 is reading them.
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* There is no timing constraint on how long this semaphore can be kept.
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*/
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#define CFG_HW_BLE_NVM_SRAM_SEMID 8
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/**
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* Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
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* The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
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* When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
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* after writing a raw (64bits data) or erasing one sector.
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* Once the Semaphore has been released, there shall be at least 1us before it can be taken again. This is required
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* to give the opportunity to CPU2 to take it.
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* On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
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* By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
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* instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
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*/
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#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID 7
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/**
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* Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
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* In order to protect its timing, the CPU1 may get this semaphore to prevent the CPU2 to either
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* write or erase in flash (as this will stall both CPUs)
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* The PES bit shall not be used as this may stall the CPU2 in some cases.
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*/
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#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID 6
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/**
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* Index of the semaphore used to manage the CLK48 clock configuration
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* When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
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* and should be released after the application switch OFF the clock when the USB is not used anymore
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* When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
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* More details in AN5289
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*/
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#define CFG_HW_CLK48_CONFIG_SEMID 5
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/* Index of the semaphore used to manage the entry Stop Mode procedure */
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#define CFG_HW_ENTRY_STOP_MODE_SEMID 4
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/* Index of the semaphore used to access the RCC */
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#define CFG_HW_RCC_SEMID 3
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/* Index of the semaphore used to access the FLASH */
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#define CFG_HW_FLASH_SEMID 2
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/* Index of the semaphore used to access the PKA */
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#define CFG_HW_PKA_SEMID 1
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/* Index of the semaphore used to access the RNG */
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#define CFG_HW_RNG_SEMID 0
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/******************************************************************************
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* HW TIMER SERVER
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*****************************************************************************/
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/**
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* The user may define the maximum number of virtual timers supported.
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* It shall not exceed 255
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*/
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#define CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER 6
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/**
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* The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
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* wakeup timer.
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* This setting is the preemptpriority part of the NVIC.
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*/
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#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO \
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(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1) /* FreeRTOS requirement */
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/**
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* The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the
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* wakeup timer.
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* This setting is the subpriority part of the NVIC. It does not exist on all processors. When it is not supported
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* on the CPU, the setting is ignored
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*/
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#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO 0
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/**
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* Define a critical section in the Timer server
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* The Timer server does not support the API to be nested
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* The Application shall either:
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* a) Ensure this will never happen
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* b) Define the critical section
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* The default implementations is masking all interrupts using the PRIMASK bit
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* The TimerServer driver uses critical sections to avoid context corruption. This is achieved with the macro
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* TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION. When CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION is set
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* to 1, all STM32 interrupts are masked with the PRIMASK bit of the CortexM CPU. It is possible to use the BASEPRI
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* register of the CortexM CPU to keep allowed some interrupts with high priority. In that case, the user shall
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* re-implement TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION and shall make sure that no TimerServer
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* API are called when the TIMER critical section is entered
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*/
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#define CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION 1
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/**
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* This value shall reflect the maximum delay there could be in the application between the time the RTC interrupt
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* is generated by the Hardware and the time when the RTC interrupt handler is called. This time is measured in
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* number of RTCCLK ticks.
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* A relaxed timing would be 10ms
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* When the value is too short, the timerserver will not be able to count properly and all timeout may be random.
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* When the value is too long, the device may wake up more often than the most optimal configuration. However, the
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* impact on power consumption would be marginal (unless the value selected is extremely too long). It is strongly
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* recommended to select a value large enough to make sure it is not too short to ensure reliability of the system
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* as this will have marginal impact on low power mode
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*/
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#define CFG_HW_TS_RTC_HANDLER_MAX_DELAY (10 * (LSI_VALUE / 1000))
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/**
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* Interrupt ID in the NVIC of the RTC Wakeup interrupt handler
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* It shall be type of IRQn_Type
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*/
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#define CFG_HW_TS_RTC_WAKEUP_HANDLER_ID RTC_WKUP_IRQn
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/******************************************************************************
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* HW UART
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*****************************************************************************/
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#define CFG_HW_LPUART1_ENABLED 0
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#define CFG_HW_LPUART1_DMA_TX_SUPPORTED 0
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#define CFG_HW_USART1_ENABLED 1
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#define CFG_HW_USART1_DMA_TX_SUPPORTED 1
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/**
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* UART1
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*/
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#define CFG_HW_USART1_PREEMPTPRIORITY 0x0F
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#define CFG_HW_USART1_SUBPRIORITY 0
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/** < The application shall check the selected source clock is enable */
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#define CFG_HW_USART1_SOURCE_CLOCK RCC_USART1CLKSOURCE_SYSCLK
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#define CFG_HW_USART1_BAUDRATE 115200
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#define CFG_HW_USART1_WORDLENGTH UART_WORDLENGTH_8B
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#define CFG_HW_USART1_STOPBITS UART_STOPBITS_1
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#define CFG_HW_USART1_PARITY UART_PARITY_NONE
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#define CFG_HW_USART1_HWFLOWCTL UART_HWCONTROL_NONE
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#define CFG_HW_USART1_MODE UART_MODE_TX_RX
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#define CFG_HW_USART1_ADVFEATUREINIT UART_ADVFEATURE_NO_INIT
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#define CFG_HW_USART1_OVERSAMPLING UART_OVERSAMPLING_8
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#define CFG_HW_USART1_TX_PORT_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
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#define CFG_HW_USART1_TX_PORT GPIOB
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#define CFG_HW_USART1_TX_PIN GPIO_PIN_6
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#define CFG_HW_USART1_TX_MODE GPIO_MODE_AF_PP
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#define CFG_HW_USART1_TX_PULL GPIO_NOPULL
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#define CFG_HW_USART1_TX_SPEED GPIO_SPEED_FREQ_VERY_HIGH
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#define CFG_HW_USART1_TX_ALTERNATE GPIO_AF7_USART1
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#define CFG_HW_USART1_RX_PORT_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
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#define CFG_HW_USART1_RX_PORT GPIOB
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#define CFG_HW_USART1_RX_PIN GPIO_PIN_7
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#define CFG_HW_USART1_RX_MODE GPIO_MODE_AF_PP
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#define CFG_HW_USART1_RX_PULL GPIO_NOPULL
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#define CFG_HW_USART1_RX_SPEED GPIO_SPEED_FREQ_VERY_HIGH
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#define CFG_HW_USART1_RX_ALTERNATE GPIO_AF7_USART1
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#define CFG_HW_USART1_CTS_PORT_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
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#define CFG_HW_USART1_CTS_PORT GPIOA
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#define CFG_HW_USART1_CTS_PIN GPIO_PIN_11
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#define CFG_HW_USART1_CTS_MODE GPIO_MODE_AF_PP
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#define CFG_HW_USART1_CTS_PULL GPIO_PULLDOWN
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#define CFG_HW_USART1_CTS_SPEED GPIO_SPEED_FREQ_VERY_HIGH
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#define CFG_HW_USART1_CTS_ALTERNATE GPIO_AF7_USART1
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#define CFG_HW_USART1_DMA_TX_PREEMPTPRIORITY 0x0F
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#define CFG_HW_USART1_DMA_TX_SUBPRIORITY 0
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#define CFG_HW_USART1_DMAMUX_CLK_ENABLE __HAL_RCC_DMAMUX1_CLK_ENABLE
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#define CFG_HW_USART1_DMA_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
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#define CFG_HW_USART1_TX_DMA_REQ DMA_REQUEST_USART1_TX
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#define CFG_HW_USART1_TX_DMA_CHANNEL DMA2_Channel4
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#define CFG_HW_USART1_TX_DMA_IRQn DMA2_Channel4_IRQn
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#define CFG_HW_USART1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler
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#endif /*HW_CONF_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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