303 lines
13 KiB
C
303 lines
13 KiB
C
#include <furi_hal_bus.h>
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#include <furi.h>
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#include <stm32wbxx_ll_bus.h>
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/* Bus bitmask definitions */
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#define FURI_HAL_BUS_IGNORE (0x0U)
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#define FURI_HAL_BUS_AHB1_GRP1 \
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(LL_AHB1_GRP1_PERIPH_DMA1 | LL_AHB1_GRP1_PERIPH_DMA2 | LL_AHB1_GRP1_PERIPH_DMAMUX1 | \
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LL_AHB1_GRP1_PERIPH_CRC | LL_AHB1_GRP1_PERIPH_TSC)
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#if defined(ADC_SUPPORT_5_MSPS)
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#define FURI_HAL_BUS_AHB2_GRP1 \
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(LL_AHB2_GRP1_PERIPH_GPIOA | LL_AHB2_GRP1_PERIPH_GPIOB | LL_AHB2_GRP1_PERIPH_GPIOC | \
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LL_AHB2_GRP1_PERIPH_GPIOD | LL_AHB2_GRP1_PERIPH_GPIOE | LL_AHB2_GRP1_PERIPH_GPIOH | \
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LL_AHB2_GRP1_PERIPH_ADC | LL_AHB2_GRP1_PERIPH_AES1)
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#define FURI_HAL_BUS_APB2_GRP1 \
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(LL_APB2_GRP1_PERIPH_TIM1 | LL_APB2_GRP1_PERIPH_SPI1 | LL_APB2_GRP1_PERIPH_USART1 | \
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LL_APB2_GRP1_PERIPH_TIM16 | LL_APB2_GRP1_PERIPH_TIM17 | LL_APB2_GRP1_PERIPH_SAI1)
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#else
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#define FURI_HAL_BUS_AHB2_GRP1 \
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(LL_AHB2_GRP1_PERIPH_GPIOA | LL_AHB2_GRP1_PERIPH_GPIOB | LL_AHB2_GRP1_PERIPH_GPIOC | \
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LL_AHB2_GRP1_PERIPH_GPIOD | LL_AHB2_GRP1_PERIPH_GPIOE | LL_AHB2_GRP1_PERIPH_GPIOH | \
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LL_AHB2_GRP1_PERIPH_AES1)
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#define FURI_HAL_BUS_APB2_GRP1 \
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(LL_APB2_GRP1_PERIPH_ADC | LL_APB2_GRP1_PERIPH_TIM1 | LL_APB2_GRP1_PERIPH_SPI1 | \
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LL_APB2_GRP1_PERIPH_USART1 | LL_APB2_GRP1_PERIPH_TIM16 | LL_APB2_GRP1_PERIPH_TIM17 | \
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LL_APB2_GRP1_PERIPH_SAI1)
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#endif
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#define FURI_HAL_BUS_AHB3_GRP1 \
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(LL_AHB3_GRP1_PERIPH_QUADSPI | LL_AHB3_GRP1_PERIPH_PKA | LL_AHB3_GRP1_PERIPH_AES2 | \
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LL_AHB3_GRP1_PERIPH_RNG | LL_AHB3_GRP1_PERIPH_HSEM | LL_AHB3_GRP1_PERIPH_IPCC)
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// LL_AHB3_GRP1_PERIPH_FLASH enabled by default
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#define FURI_HAL_BUS_APB1_GRP1 \
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(LL_APB1_GRP1_PERIPH_TIM2 | LL_APB1_GRP1_PERIPH_LCD | LL_APB1_GRP1_PERIPH_SPI2 | \
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LL_APB1_GRP1_PERIPH_I2C1 | LL_APB1_GRP1_PERIPH_I2C3 | LL_APB1_GRP1_PERIPH_CRS | \
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LL_APB1_GRP1_PERIPH_USB | LL_APB1_GRP1_PERIPH_LPTIM1)
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#define FURI_HAL_BUS_APB1_GRP2 (LL_APB1_GRP2_PERIPH_LPUART1 | LL_APB1_GRP2_PERIPH_LPTIM2)
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#define FURI_HAL_BUS_APB3_GRP1 (LL_APB3_GRP1_PERIPH_RF)
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/* Test macro definitions */
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#define FURI_HAL_BUS_IS_ALL_CLEAR(reg, value) (READ_BIT((reg), (value)) == 0UL)
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#define FURI_HAL_BUS_IS_ALL_SET(reg, value) (READ_BIT((reg), (value)) == (value))
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#define FURI_HAL_BUS_IS_CLOCK_ENABLED(bus, value, ...) \
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(FURI_HAL_BUS_IS_ALL_SET(RCC->bus##ENR##__VA_ARGS__, (value)))
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#define FURI_HAL_BUS_IS_CLOCK_DISABLED(bus, value, ...) \
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(FURI_HAL_BUS_IS_ALL_CLEAR(RCC->bus##ENR##__VA_ARGS__, (value)))
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#define FURI_HAL_BUS_IS_RESET_ASSERTED(bus, value, ...) \
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(FURI_HAL_BUS_IS_ALL_SET(RCC->bus##RSTR##__VA_ARGS__, (value)))
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#define FURI_HAL_BUS_IS_RESET_DEASSERTED(bus, value, ...) \
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(FURI_HAL_BUS_IS_ALL_CLEAR(RCC->bus##RSTR##__VA_ARGS__, (value)))
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#define FURI_HAL_BUS_IS_PERIPH_ENABLED(bus, value, ...) \
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(FURI_HAL_BUS_IS_RESET_DEASSERTED(bus, (value), __VA_ARGS__) && \
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FURI_HAL_BUS_IS_CLOCK_ENABLED(bus, (value), __VA_ARGS__))
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#define FURI_HAL_BUS_IS_PERIPH_DISABLED(bus, value, ...) \
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(FURI_HAL_BUS_IS_CLOCK_DISABLED(bus, (value), __VA_ARGS__) && \
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FURI_HAL_BUS_IS_RESET_ASSERTED(bus, (value), __VA_ARGS__))
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/* Control macro definitions */
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#define FURI_HAL_BUS_RESET_ASSERT(bus, value, grp) LL_##bus##_GRP##grp##_ForceReset(value)
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#define FURI_HAL_BUS_RESET_DEASSERT(bus, value, grp) LL_##bus##_GRP##grp##_ReleaseReset(value)
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#define FURI_HAL_BUS_CLOCK_ENABLE(bus, value, grp) LL_##bus##_GRP##grp##_EnableClock(value)
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#define FURI_HAL_BUS_CLOCK_DISABLE(bus, value, grp) LL_##bus##_GRP##grp##_DisableClock(value)
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#define FURI_HAL_BUS_PERIPH_ENABLE(bus, value, grp) \
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FURI_HAL_BUS_CLOCK_ENABLE(bus, value, grp); \
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FURI_HAL_BUS_RESET_DEASSERT(bus, value, grp)
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#define FURI_HAL_BUS_PERIPH_DISABLE(bus, value, grp) \
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FURI_HAL_BUS_RESET_ASSERT(bus, value, grp); \
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FURI_HAL_BUS_CLOCK_DISABLE(bus, value, grp)
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#define FURI_HAL_BUS_PERIPH_RESET(bus, value, grp) \
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FURI_HAL_BUS_RESET_ASSERT(bus, value, grp); \
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FURI_HAL_BUS_RESET_DEASSERT(bus, value, grp)
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static const uint32_t furi_hal_bus[] = {
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[FuriHalBusAHB1_GRP1] = FURI_HAL_BUS_IGNORE,
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[FuriHalBusDMA1] = LL_AHB1_GRP1_PERIPH_DMA1,
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[FuriHalBusDMA2] = LL_AHB1_GRP1_PERIPH_DMA2,
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[FuriHalBusDMAMUX1] = LL_AHB1_GRP1_PERIPH_DMAMUX1,
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[FuriHalBusCRC] = LL_AHB1_GRP1_PERIPH_CRC,
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[FuriHalBusTSC] = LL_AHB1_GRP1_PERIPH_TSC,
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[FuriHalBusAHB2_GRP1] = FURI_HAL_BUS_IGNORE,
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[FuriHalBusGPIOA] = LL_AHB2_GRP1_PERIPH_GPIOA,
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[FuriHalBusGPIOB] = LL_AHB2_GRP1_PERIPH_GPIOB,
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[FuriHalBusGPIOC] = LL_AHB2_GRP1_PERIPH_GPIOC,
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[FuriHalBusGPIOD] = LL_AHB2_GRP1_PERIPH_GPIOD,
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[FuriHalBusGPIOE] = LL_AHB2_GRP1_PERIPH_GPIOE,
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[FuriHalBusGPIOH] = LL_AHB2_GRP1_PERIPH_GPIOH,
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#if defined(ADC_SUPPORT_5_MSPS)
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[FuriHalBusADC] = LL_AHB2_GRP1_PERIPH_ADC,
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#endif
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[FuriHalBusAES1] = LL_AHB2_GRP1_PERIPH_AES1,
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[FuriHalBusAHB3_GRP1] = FURI_HAL_BUS_IGNORE,
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[FuriHalBusQUADSPI] = LL_AHB3_GRP1_PERIPH_QUADSPI,
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[FuriHalBusPKA] = LL_AHB3_GRP1_PERIPH_PKA,
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[FuriHalBusAES2] = LL_AHB3_GRP1_PERIPH_AES2,
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[FuriHalBusRNG] = LL_AHB3_GRP1_PERIPH_RNG,
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[FuriHalBusHSEM] = LL_AHB3_GRP1_PERIPH_HSEM,
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[FuriHalBusIPCC] = LL_AHB3_GRP1_PERIPH_IPCC,
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[FuriHalBusFLASH] = LL_AHB3_GRP1_PERIPH_FLASH,
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[FuriHalBusAPB1_GRP1] = FURI_HAL_BUS_APB1_GRP1,
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[FuriHalBusTIM2] = LL_APB1_GRP1_PERIPH_TIM2,
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[FuriHalBusLCD] = LL_APB1_GRP1_PERIPH_LCD,
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[FuriHalBusSPI2] = LL_APB1_GRP1_PERIPH_SPI2,
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[FuriHalBusI2C1] = LL_APB1_GRP1_PERIPH_I2C1,
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[FuriHalBusI2C3] = LL_APB1_GRP1_PERIPH_I2C3,
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[FuriHalBusCRS] = LL_APB1_GRP1_PERIPH_CRS,
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[FuriHalBusUSB] = LL_APB1_GRP1_PERIPH_USB,
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[FuriHalBusLPTIM1] = LL_APB1_GRP1_PERIPH_LPTIM1,
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[FuriHalBusAPB1_GRP2] = FURI_HAL_BUS_APB1_GRP2,
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[FuriHalBusLPUART1] = LL_APB1_GRP2_PERIPH_LPUART1,
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[FuriHalBusLPTIM2] = LL_APB1_GRP2_PERIPH_LPTIM2,
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[FuriHalBusAPB2_GRP1] = FURI_HAL_BUS_APB2_GRP1,
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#if defined(ADC_SUPPORT_2_5_MSPS)
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[FuriHalBusADC] = LL_APB2_GRP1_PERIPH_ADC,
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#endif
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[FuriHalBusTIM1] = LL_APB2_GRP1_PERIPH_TIM1,
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[FuriHalBusSPI1] = LL_APB2_GRP1_PERIPH_SPI1,
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[FuriHalBusUSART1] = LL_APB2_GRP1_PERIPH_USART1,
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[FuriHalBusTIM16] = LL_APB2_GRP1_PERIPH_TIM16,
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[FuriHalBusTIM17] = LL_APB2_GRP1_PERIPH_TIM17,
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[FuriHalBusSAI1] = LL_APB2_GRP1_PERIPH_SAI1,
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[FuriHalBusAPB3_GRP1] = FURI_HAL_BUS_IGNORE, // APB3_GRP1 clocking cannot be changed
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[FuriHalBusRF] = LL_APB3_GRP1_PERIPH_RF,
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};
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void furi_hal_bus_init_early() {
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FURI_CRITICAL_ENTER();
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// FURI_HAL_BUS_PERIPH_DISABLE(AHB1, FURI_HAL_BUS_AHB1_GRP1, 1);
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// FURI_HAL_BUS_PERIPH_DISABLE(AHB2, FURI_HAL_BUS_AHB2_GRP1, 1);
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// FURI_HAL_BUS_PERIPH_DISABLE(AHB3, FURI_HAL_BUS_AHB3_GRP1, 1);
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FURI_HAL_BUS_PERIPH_DISABLE(APB1, FURI_HAL_BUS_APB1_GRP1, 1);
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FURI_HAL_BUS_PERIPH_DISABLE(APB1, FURI_HAL_BUS_APB1_GRP2, 2);
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FURI_HAL_BUS_PERIPH_DISABLE(APB2, FURI_HAL_BUS_APB2_GRP1, 1);
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FURI_HAL_BUS_RESET_ASSERT(APB3, FURI_HAL_BUS_APB3_GRP1, 1);
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FURI_CRITICAL_EXIT();
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}
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void furi_hal_bus_deinit_early() {
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FURI_CRITICAL_ENTER();
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// FURI_HAL_BUS_PERIPH_ENABLE(AHB1, FURI_HAL_BUS_AHB1_GRP1, 1);
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// FURI_HAL_BUS_PERIPH_ENABLE(AHB2, FURI_HAL_BUS_AHB2_GRP1, 1);
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// FURI_HAL_BUS_PERIPH_ENABLE(AHB3, FURI_HAL_BUS_AHB3_GRP1, 1);
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FURI_HAL_BUS_PERIPH_ENABLE(APB1, FURI_HAL_BUS_APB1_GRP1, 1);
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FURI_HAL_BUS_PERIPH_ENABLE(APB1, FURI_HAL_BUS_APB1_GRP2, 2);
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FURI_HAL_BUS_PERIPH_ENABLE(APB2, FURI_HAL_BUS_APB2_GRP1, 1);
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FURI_HAL_BUS_RESET_DEASSERT(APB3, FURI_HAL_BUS_APB3_GRP1, 1);
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FURI_CRITICAL_EXIT();
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}
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void furi_hal_bus_enable(FuriHalBus bus) {
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furi_check(bus < FuriHalBusMAX);
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const uint32_t value = furi_hal_bus[bus];
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if(!value) {
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return;
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}
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FURI_CRITICAL_ENTER();
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if(bus < FuriHalBusAHB2_GRP1) {
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// furi_check(FURI_HAL_BUS_IS_PERIPH_DISABLED(AHB1, value));
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FURI_HAL_BUS_PERIPH_ENABLE(AHB1, value, 1);
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} else if(bus < FuriHalBusAHB3_GRP1) {
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// furi_check(FURI_HAL_BUS_IS_PERIPH_DISABLED(AHB2, value));
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FURI_HAL_BUS_PERIPH_ENABLE(AHB2, value, 1);
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} else if(bus < FuriHalBusAPB1_GRP1) {
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// furi_check(FURI_HAL_BUS_IS_PERIPH_DISABLED(AHB3, value));
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FURI_HAL_BUS_PERIPH_ENABLE(AHB3, value, 1);
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} else if(bus < FuriHalBusAPB1_GRP2) {
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furi_check(FURI_HAL_BUS_IS_PERIPH_DISABLED(APB1, value, 1));
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FURI_HAL_BUS_PERIPH_ENABLE(APB1, value, 1);
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} else if(bus < FuriHalBusAPB2_GRP1) {
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furi_check(FURI_HAL_BUS_IS_PERIPH_DISABLED(APB1, value, 2));
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FURI_HAL_BUS_PERIPH_ENABLE(APB1, value, 2);
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} else if(bus < FuriHalBusAPB3_GRP1) {
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furi_check(FURI_HAL_BUS_IS_PERIPH_DISABLED(APB2, value));
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FURI_HAL_BUS_PERIPH_ENABLE(APB2, value, 1);
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} else {
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furi_check(FURI_HAL_BUS_IS_RESET_ASSERTED(APB3, value));
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FURI_HAL_BUS_RESET_DEASSERT(APB3, FURI_HAL_BUS_APB3_GRP1, 1);
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}
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FURI_CRITICAL_EXIT();
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}
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void furi_hal_bus_reset(FuriHalBus bus) {
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furi_check(bus < FuriHalBusMAX);
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const uint32_t value = furi_hal_bus[bus];
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if(!value) {
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return;
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}
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FURI_CRITICAL_ENTER();
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if(bus < FuriHalBusAHB2_GRP1) {
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// furi_check(FURI_HAL_BUS_IS_PERIPH_ENABLED(AHB1, value));
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FURI_HAL_BUS_PERIPH_RESET(AHB1, value, 1);
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} else if(bus < FuriHalBusAHB3_GRP1) {
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// furi_check(FURI_HAL_BUS_IS_PERIPH_ENABLED(AHB2, value));
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FURI_HAL_BUS_PERIPH_RESET(AHB2, value, 1);
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} else if(bus < FuriHalBusAPB1_GRP1) {
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// furi_check(FURI_HAL_BUS_IS_PERIPH_ENABLED(AHB3, value));
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FURI_HAL_BUS_PERIPH_RESET(AHB3, value, 1);
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} else if(bus < FuriHalBusAPB1_GRP2) {
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furi_check(FURI_HAL_BUS_IS_PERIPH_ENABLED(APB1, value, 1));
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FURI_HAL_BUS_PERIPH_RESET(APB1, value, 1);
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} else if(bus < FuriHalBusAPB2_GRP1) {
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furi_check(FURI_HAL_BUS_IS_PERIPH_ENABLED(APB1, value, 2));
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FURI_HAL_BUS_PERIPH_RESET(APB1, value, 2);
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} else if(bus < FuriHalBusAPB3_GRP1) {
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furi_check(FURI_HAL_BUS_IS_PERIPH_ENABLED(APB2, value));
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FURI_HAL_BUS_PERIPH_RESET(APB2, value, 1);
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} else {
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furi_check(FURI_HAL_BUS_IS_RESET_DEASSERTED(APB3, value));
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FURI_HAL_BUS_PERIPH_RESET(APB3, value, 1);
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}
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FURI_CRITICAL_EXIT();
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}
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void furi_hal_bus_disable(FuriHalBus bus) {
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furi_check(bus < FuriHalBusMAX);
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const uint32_t value = furi_hal_bus[bus];
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if(!value) {
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return;
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}
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FURI_CRITICAL_ENTER();
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if(bus < FuriHalBusAHB2_GRP1) {
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// furi_check(FURI_HAL_BUS_IS_PERIPH_ENABLED(AHB1, value));
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FURI_HAL_BUS_PERIPH_DISABLE(AHB1, value, 1);
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} else if(bus < FuriHalBusAHB3_GRP1) {
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// furi_check(FURI_HAL_BUS_IS_PERIPH_ENABLED(AHB2, value));
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FURI_HAL_BUS_PERIPH_DISABLE(AHB2, value, 1);
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} else if(bus < FuriHalBusAPB1_GRP1) {
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// furi_check(FURI_HAL_BUS_IS_PERIPH_ENABLED(AHB3, value));
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FURI_HAL_BUS_PERIPH_DISABLE(AHB3, value, 1);
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} else if(bus < FuriHalBusAPB1_GRP2) {
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furi_check(FURI_HAL_BUS_IS_PERIPH_ENABLED(APB1, value, 1));
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FURI_HAL_BUS_PERIPH_DISABLE(APB1, value, 1);
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} else if(bus < FuriHalBusAPB2_GRP1) {
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furi_check(FURI_HAL_BUS_IS_PERIPH_ENABLED(APB1, value, 2));
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FURI_HAL_BUS_PERIPH_DISABLE(APB1, value, 2);
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} else if(bus < FuriHalBusAPB3_GRP1) {
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furi_check(FURI_HAL_BUS_IS_PERIPH_ENABLED(APB2, value));
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FURI_HAL_BUS_PERIPH_DISABLE(APB2, value, 1);
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} else {
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furi_check(FURI_HAL_BUS_IS_RESET_DEASSERTED(APB3, value));
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FURI_HAL_BUS_RESET_ASSERT(APB3, FURI_HAL_BUS_APB3_GRP1, 1);
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}
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FURI_CRITICAL_EXIT();
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}
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bool furi_hal_bus_is_enabled(FuriHalBus bus) {
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furi_check(bus < FuriHalBusMAX);
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const uint32_t value = furi_hal_bus[bus];
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if(value == FURI_HAL_BUS_IGNORE) {
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return true;
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}
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bool ret = false;
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FURI_CRITICAL_ENTER();
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if(bus < FuriHalBusAHB2_GRP1) {
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ret = FURI_HAL_BUS_IS_PERIPH_ENABLED(AHB1, value);
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} else if(bus < FuriHalBusAHB3_GRP1) {
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ret = FURI_HAL_BUS_IS_PERIPH_ENABLED(AHB2, value);
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} else if(bus < FuriHalBusAPB1_GRP1) {
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ret = FURI_HAL_BUS_IS_PERIPH_ENABLED(AHB3, value);
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} else if(bus < FuriHalBusAPB1_GRP2) {
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ret = FURI_HAL_BUS_IS_PERIPH_ENABLED(APB1, value, 1);
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} else if(bus < FuriHalBusAPB2_GRP1) {
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ret = FURI_HAL_BUS_IS_PERIPH_ENABLED(APB1, value, 2);
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} else if(bus < FuriHalBusAPB3_GRP1) {
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ret = FURI_HAL_BUS_IS_PERIPH_ENABLED(APB2, value);
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} else {
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ret = FURI_HAL_BUS_IS_RESET_DEASSERTED(APB3, value);
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}
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FURI_CRITICAL_EXIT();
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return ret;
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}
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