136 lines
4.2 KiB
C
136 lines
4.2 KiB
C
#include <api-hal-clock.h>
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#include <main.h>
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#include <stm32wbxx_ll_pwr.h>
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#include <stm32wbxx_ll_rcc.h>
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#include <stm32wbxx_ll_utils.h>
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void api_hal_clock_init() {
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LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
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while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_3);
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/* HSE configuration and activation */
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LL_RCC_HSE_SetCapacitorTuning(0x18);
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LL_RCC_HSE_Enable();
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while(LL_RCC_HSE_IsReady() != 1) ;
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/* HSI configuration and activation */
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LL_RCC_HSI_Enable();
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while(LL_RCC_HSI_IsReady() != 1)
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/* LSE configuration and activation */
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LL_PWR_EnableBkUpAccess();
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LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_MEDIUMLOW);
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LL_RCC_LSE_Enable();
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while(LL_RCC_LSE_IsReady() != 1) ;
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LL_RCC_HSE_EnableCSS();
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LL_RCC_EnableIT_LSECSS();
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LL_RCC_LSE_EnableCSS();
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/* Main PLL configuration and activation */
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LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_2, 8, LL_RCC_PLLR_DIV_2);
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LL_RCC_PLL_Enable();
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LL_RCC_PLL_EnableDomain_SYS();
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while(LL_RCC_PLL_IsReady() != 1);
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LL_RCC_PLLSAI1_ConfigDomain_48M(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_2, 6, LL_RCC_PLLSAI1Q_DIV_2);
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LL_RCC_PLLSAI1_ConfigDomain_ADC(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_2, 6, LL_RCC_PLLSAI1R_DIV_2);
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LL_RCC_PLLSAI1_Enable();
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LL_RCC_PLLSAI1_EnableDomain_48M();
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LL_RCC_PLLSAI1_EnableDomain_ADC();
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while(LL_RCC_PLLSAI1_IsReady() != 1);
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/* Sysclk activation on the main PLL */
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/* Set CPU1 prescaler*/
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LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
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/* Set CPU2 prescaler*/
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LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
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while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
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/* Set AHB SHARED prescaler*/
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LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
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/* Set APB1 prescaler*/
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LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
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/* Set APB2 prescaler*/
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LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
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/* Disable MSI */
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LL_RCC_MSI_Disable();
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while(LL_RCC_MSI_IsReady() != 0);
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/* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
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LL_SetSystemCoreClock(64000000);
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/* Update the time base */
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if (HAL_InitTick (TICK_INT_PRIORITY) != HAL_OK)
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{
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Error_Handler();
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}
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if(LL_RCC_GetRTCClockSource() != LL_RCC_RTC_CLKSOURCE_LSE) {
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LL_RCC_ForceBackupDomainReset();
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LL_RCC_ReleaseBackupDomainReset();
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LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSE);
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}
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LL_RCC_EnableRTC();
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LL_RCC_SetUSARTClockSource(LL_RCC_USART1_CLKSOURCE_PCLK2);
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LL_RCC_SetADCClockSource(LL_RCC_ADC_CLKSOURCE_PLLSAI1);
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LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_PCLK1);
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LL_RCC_SetRNGClockSource(LL_RCC_RNG_CLKSOURCE_CLK48);
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LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLLSAI1);
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LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSE);
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LL_RCC_SetSMPSPrescaler(LL_RCC_SMPS_DIV_1);
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LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_LSE);
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// AHB1
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1);
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1);
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// AHB2
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH);
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// APB1
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
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// APB2
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
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}
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void api_hal_clock_switch_to_hsi() {
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LL_RCC_HSI_Enable( );
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while(!LL_RCC_HSI_IsReady());
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
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LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
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}
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void api_hal_clock_switch_to_pll() {
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LL_RCC_HSE_Enable();
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LL_RCC_PLL_Enable();
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while(!LL_RCC_HSE_IsReady());
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while(!LL_RCC_PLL_IsReady());
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
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LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSE);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
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}
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