224d0aefe4
* First part of multitarget porting * Delete firmware/targets/f7/Inc directory * Delete firmware/targets/f7/Src directory * gpio: cli fixes; about: using version from HAL * sdk: path fixes * gui: include fixes * applications: more include fixes * gpio: ported to new apis * hal: introduced furi_hal_target_hw.h; libs: added one_wire * hal: f18 target * github: also build f18 by default * typo fix * fbt: removed extra checks on app list * api: explicitly bundling select mlib headers with sdk * hal: f18: changed INPUT_DEBOUNCE_TICKS to match f7 * cleaned up commented out code * docs: added info on hw targets * docs: targets: formatting fixes * f18: fixed link error * f18: fixed API version to match f7 * docs: hardware: minor wording fixes * faploader: added fw target check * docs: typo fixes * github: not building komi target by default * fbt: support for `targets` field for built-in apps * github: reworked build flow to exclude app_set; fbt: removed komi-specific appset; added additional target buildset check * github: fixed build; nfc: fixed pvs warnings * attempt to fix target id * f7, f18: removed certain HAL function from public API * apps: debug: enabled bt_debug_app for f18 * Targets: backport input pins configuration routine from F7 to F18 Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com>
98 lines
3.0 KiB
C
98 lines
3.0 KiB
C
#include "stm32wbxx.h"
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/*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#ifndef VECT_TAB_OFFSET
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#define VECT_TAB_OFFSET \
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0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */
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#endif
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#define VECT_TAB_BASE_ADDRESS \
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SRAM1_BASE /*!< Vector Table base offset field. This value must be a multiple of 0x200. */
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/* The SystemCoreClock variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 4000000UL; /*CPU1: M4 on MSI clock after startup (4MHz)*/
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const uint32_t AHBPrescTable[16UL] =
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{1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
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const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
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const uint32_t MSIRangeTable[16UL] = {
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100000UL,
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200000UL,
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400000UL,
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800000UL,
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1000000UL,
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2000000UL,
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4000000UL,
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8000000UL,
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16000000UL,
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24000000UL,
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32000000UL,
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48000000UL,
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0UL,
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0UL,
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0UL,
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0UL}; /* 0UL values are incorrect cases */
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/**
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* @brief Setup the microcontroller system.
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* @param None
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* @retval None
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*/
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void SystemInit(void) {
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/* Configure the Vector Table location add offset address ------------------*/
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#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)
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/* program in SRAMx */
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SCB->VTOR = VECT_TAB_BASE_ADDRESS |
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VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAMx for CPU1 */
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#else /* program in FLASH */
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SCB->VTOR = VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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/* FPU settings ------------------------------------------------------------*/
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#if(__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |=
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((3UL << (10UL * 2UL)) | (3UL << (11UL * 2UL))); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set MSION bit */
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RCC->CR |= RCC_CR_MSION;
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/* Reset CFGR register */
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RCC->CFGR = 0x00070000U;
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/* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
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RCC->CR &= (uint32_t)0xFAF6FEFBU;
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/*!< Reset LSI1 and LSI2 bits */
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RCC->CSR &= (uint32_t)0xFFFFFFFAU;
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/*!< Reset HSI48ON bit */
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RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x22041000U;
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#if defined(STM32WB55xx) || defined(STM32WB5Mxx)
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/* Reset PLLSAI1CFGR register */
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RCC->PLLSAI1CFGR = 0x22041000U;
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#endif
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/* Reset HSEBYP bit */
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RCC->CR &= 0xFFFBFFFFU;
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/* Disable all interrupts */
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RCC->CIER = 0x00000000;
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}
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