01434265f6
* Disable USART in sleep * Restore UART state on suspend/resume * FuriHal: Enable stop mode and add insomnia to I2C and SPI * Remove IDLE interrupt * FuriHal: add FPU isr and disable all FPU interrupt, add core2 stop mode configuration on deep sleep * FuriHal: tie stop mode debug with debug rtc flag * FuriHal: adjust flash latency on clock switch, tie mcu debug with RTC debug flag * FuriHal: move resource init to early stage * Add EXTI pending check, enable debug traps with compile-time flag * Wrap sleep debug functions in conditional compilation * Remove erroneous changed * Do not use CSS, remove it from everywhere * Enable/disable USB on VBUS connect (prototype) * FuriHal: add LPMS and DEEPSLEEP magic, workaround state inconsistency between cores * FuriHal: honor c1 LMPS * USB mode switch fix * Applications: add flags and insomnia bypass system * Correct spelling * FuriHal: cleanup insomnia usage, reset sleep flags on wakeup, add shutdown api * FuriHal: extra check on reinit request * FuriHal: rename gpio_display_rst pin to gpio_display_rst_n * FuriHal: add debug HAL * FuriHal: add some magic to core2 reload procedure, fix issue with crash on ble keyboard exit * FuriHal: cleanup ble glue, add BLE_GLUE_DEBUG flag * FuriHal: ble reinit API, move os timer to LPTIM1 for deep sleep capability, shutdown that works * FuriHal: take insomnia while shutdown * Remove USB switch on/off on VBUS change * Better tick skew handling * Improve tick consistency under load * Add USB_HP dummy IRQ handler * Move interrupt check closer to sleep * Clean up includes * Re-enable Insomnia globally * FuriHal: enable CSS * FuriHal: remove questionable core2 clock shenanigans * FuriHal: use core1 RCC registers in idle timer config * FuriHal: return back CSS handlers, add lptim isr dispatching Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com> Co-authored-by: nminaylov <nm29719@gmail.com>
236 lines
8.1 KiB
C
236 lines
8.1 KiB
C
#include <furi_hal_clock.h>
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#include <furi.h>
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#include <stm32wbxx_ll_pwr.h>
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#include <stm32wbxx_ll_rcc.h>
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#include <stm32wbxx_ll_utils.h>
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#include <stm32wbxx_ll_cortex.h>
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#include <stm32wbxx_ll_bus.h>
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#define TAG "FuriHalClock"
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#define CPU_CLOCK_HZ_EARLY 4000000
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#define CPU_CLOCK_HZ_MAIN 64000000
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#define TICK_INT_PRIORITY 15U
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#define HS_CLOCK_IS_READY() (LL_RCC_HSE_IsReady() && LL_RCC_HSI_IsReady())
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#define LS_CLOCK_IS_READY() (LL_RCC_LSE_IsReady() && LL_RCC_LSI1_IsReady())
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void furi_hal_clock_init_early() {
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LL_SetSystemCoreClock(CPU_CLOCK_HZ_EARLY);
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LL_Init1msTick(SystemCoreClock);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2);
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3);
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}
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void furi_hal_clock_deinit_early() {
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LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1);
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LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3);
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LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1);
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LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2);
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LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
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LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
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LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC);
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LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOD);
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LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE);
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LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH);
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}
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void furi_hal_clock_init() {
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/* Prepare Flash memory for 64MHz system clock */
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LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
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while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_3)
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;
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/* HSE and HSI configuration and activation */
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LL_RCC_HSE_SetCapacitorTuning(0x26);
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LL_RCC_HSE_Enable();
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LL_RCC_HSI_Enable();
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while(!HS_CLOCK_IS_READY())
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;
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LL_RCC_HSE_EnableCSS();
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/* LSE and LSI1 configuration and activation */
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LL_PWR_EnableBkUpAccess();
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LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_HIGH);
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LL_RCC_LSE_Enable();
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LL_RCC_LSI1_Enable();
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while(!LS_CLOCK_IS_READY())
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;
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LL_EXTI_EnableIT_0_31(
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LL_EXTI_LINE_18); /* Why? Because that's why. See RM0434, Table 61. CPU1 vector table. */
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LL_EXTI_EnableRisingTrig_0_31(LL_EXTI_LINE_18);
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LL_RCC_EnableIT_LSECSS();
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LL_RCC_LSE_EnableCSS();
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/* Main PLL configuration and activation */
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LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_2, 8, LL_RCC_PLLR_DIV_2);
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LL_RCC_PLL_Enable();
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LL_RCC_PLL_EnableDomain_SYS();
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while(LL_RCC_PLL_IsReady() != 1)
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;
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LL_RCC_PLLSAI1_ConfigDomain_48M(
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LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_2, 6, LL_RCC_PLLSAI1Q_DIV_2);
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LL_RCC_PLLSAI1_ConfigDomain_ADC(
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LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_2, 6, LL_RCC_PLLSAI1R_DIV_2);
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LL_RCC_PLLSAI1_Enable();
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LL_RCC_PLLSAI1_EnableDomain_48M();
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LL_RCC_PLLSAI1_EnableDomain_ADC();
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while(LL_RCC_PLLSAI1_IsReady() != 1)
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;
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/* Sysclk activation on the main PLL */
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/* Set CPU1 prescaler*/
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LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
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/* Set CPU2 prescaler*/
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LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
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while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
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;
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/* Set AHB SHARED prescaler*/
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LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
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/* Set APB1 prescaler*/
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LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
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/* Set APB2 prescaler*/
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LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
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/* Disable MSI */
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LL_RCC_MSI_Disable();
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while(LL_RCC_MSI_IsReady() != 0)
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;
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/* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
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LL_SetSystemCoreClock(CPU_CLOCK_HZ_MAIN);
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/* Update the time base */
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LL_Init1msTick(SystemCoreClock);
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LL_SYSTICK_EnableIT();
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NVIC_SetPriority(
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SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), TICK_INT_PRIORITY, 0));
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NVIC_EnableIRQ(SysTick_IRQn);
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LL_RCC_SetUSARTClockSource(LL_RCC_USART1_CLKSOURCE_PCLK2);
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LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1);
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LL_RCC_SetADCClockSource(LL_RCC_ADC_CLKSOURCE_PLLSAI1);
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LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_PCLK1);
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LL_RCC_SetRNGClockSource(LL_RCC_RNG_CLKSOURCE_CLK48);
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LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLLSAI1);
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LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_PLLSAI1);
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LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSE);
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LL_RCC_SetSMPSPrescaler(LL_RCC_SMPS_DIV_1);
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LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_LSE);
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// AHB1 GRP1
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2);
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1);
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC);
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// LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_TSC);
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// AHB2 GRP1
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES1);
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// AHB3 GRP1
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// LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_QUADSPI);
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA);
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_AES2);
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG);
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM);
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FLASH);
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// APB1 GRP1
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
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// LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LCD);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB);
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// LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USB);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1);
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// APB1 GRP2
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1);
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// APB2
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// LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17);
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// LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1);
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FURI_LOG_I(TAG, "Init OK");
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}
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void furi_hal_clock_switch_to_hsi() {
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LL_RCC_HSI_Enable();
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while(!LL_RCC_HSI_IsReady())
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;
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
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LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
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while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
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;
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LL_FLASH_SetLatency(LL_FLASH_LATENCY_1);
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}
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void furi_hal_clock_switch_to_pll() {
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LL_RCC_HSE_Enable();
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LL_RCC_PLL_Enable();
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while(!LL_RCC_HSE_IsReady())
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;
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while(!LL_RCC_PLL_IsReady())
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;
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LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
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LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSE);
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while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
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;
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}
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void furi_hal_clock_suspend_tick() {
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CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_ENABLE_Msk);
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}
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void furi_hal_clock_resume_tick() {
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SET_BIT(SysTick->CTRL, SysTick_CTRL_ENABLE_Msk);
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}
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