 1d7966f74e
			
		
	
	
		1d7966f74e
		
			
		
	
	
	
	
		
			
			* digital signal: add optimization * nfc test: more restrict tests * digital signal: build as separate library * digital signal: remove unused flags, format sources * digital signal: fix cflag name * target: fix build for f18 target Co-authored-by: あく <alleteam@gmail.com>
		
			
				
	
	
		
			659 lines
		
	
	
		
			22 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			659 lines
		
	
	
		
			22 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| #include "digital_signal.h"
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| 
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| #include <furi.h>
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| #include <furi_hal.h>
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| #include <furi_hal_resources.h>
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| #include <math.h>
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| 
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| #include <stm32wbxx_ll_dma.h>
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| #include <stm32wbxx_ll_tim.h>
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| 
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| /* must be on bank B */
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| #define DEBUG_OUTPUT gpio_ext_pb3
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| 
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| struct ReloadBuffer {
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|     uint32_t* buffer; /* DMA ringbuffer */
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|     uint32_t size; /* maximum entry count of the ring buffer */
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|     uint32_t write_pos; /* current buffer write index */
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|     uint32_t read_pos; /* current buffer read index */
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|     bool dma_active;
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| };
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| 
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| struct DigitalSequence {
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|     uint8_t signals_size;
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|     bool bake;
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|     uint32_t sequence_used;
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|     uint32_t sequence_size;
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|     DigitalSignal** signals;
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|     uint8_t* sequence;
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|     const GpioPin* gpio;
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|     uint32_t send_time;
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|     bool send_time_active;
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|     LL_DMA_InitTypeDef dma_config_gpio;
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|     LL_DMA_InitTypeDef dma_config_timer;
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|     uint32_t* gpio_buff;
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|     struct ReloadBuffer* dma_buffer;
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| };
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| 
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| struct DigitalSignalInternals {
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|     uint64_t factor;
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|     uint32_t reload_reg_entries;
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|     uint32_t reload_reg_remainder;
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|     uint32_t gpio_buff[2];
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|     const GpioPin* gpio;
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|     LL_DMA_InitTypeDef dma_config_gpio;
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|     LL_DMA_InitTypeDef dma_config_timer;
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| };
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| 
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| #define TAG "DigitalSignal"
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| 
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| #define F_TIM (64000000.0)
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| #define T_TIM 1562 /* 15.625 ns *100 */
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| #define T_TIM_DIV2 781 /* 15.625 ns / 2 *100 */
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| 
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| /* maximum entry count of the sequence dma ring buffer */
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| #define SEQUENCE_DMA_RINGBUFFER_SIZE 32
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| /* maximum number of DigitalSignals in a sequence */
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| #define SEQUENCE_SIGNALS_SIZE 32
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| /*
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|  * if sequence size runs out from the initial value passed to digital_sequence_alloc
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|  * the size will be increased by this amount and reallocated
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|  */
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| #define SEQUENCE_SIZE_REALLOCATE_INCREMENT 256
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| 
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| DigitalSignal* digital_signal_alloc(uint32_t max_edges_cnt) {
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|     DigitalSignal* signal = malloc(sizeof(DigitalSignal));
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|     signal->start_level = true;
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|     signal->edges_max_cnt = max_edges_cnt;
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|     signal->edge_timings = malloc(signal->edges_max_cnt * sizeof(uint32_t));
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|     signal->edge_cnt = 0;
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|     signal->reload_reg_buff = malloc(signal->edges_max_cnt * sizeof(uint32_t));
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| 
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|     signal->internals = malloc(sizeof(DigitalSignalInternals));
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|     DigitalSignalInternals* internals = signal->internals;
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| 
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|     internals->factor = 1024 * 1024;
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| 
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|     internals->dma_config_gpio.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
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|     internals->dma_config_gpio.Mode = LL_DMA_MODE_CIRCULAR;
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|     internals->dma_config_gpio.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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|     internals->dma_config_gpio.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
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|     internals->dma_config_gpio.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
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|     internals->dma_config_gpio.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD;
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|     internals->dma_config_gpio.NbData = 2;
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|     internals->dma_config_gpio.PeriphRequest = LL_DMAMUX_REQ_TIM2_UP;
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|     internals->dma_config_gpio.Priority = LL_DMA_PRIORITY_VERYHIGH;
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| 
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|     internals->dma_config_timer.PeriphOrM2MSrcAddress = (uint32_t) & (TIM2->ARR);
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|     internals->dma_config_timer.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
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|     internals->dma_config_timer.Mode = LL_DMA_MODE_NORMAL;
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|     internals->dma_config_timer.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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|     internals->dma_config_timer.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
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|     internals->dma_config_timer.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
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|     internals->dma_config_timer.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD;
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|     internals->dma_config_timer.PeriphRequest = LL_DMAMUX_REQ_TIM2_UP;
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|     internals->dma_config_timer.Priority = LL_DMA_PRIORITY_HIGH;
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| 
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|     return signal;
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| }
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| 
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| void digital_signal_free(DigitalSignal* signal) {
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|     furi_assert(signal);
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| 
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|     free(signal->edge_timings);
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|     free(signal->reload_reg_buff);
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|     free(signal->internals);
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|     free(signal);
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| }
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| 
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| bool digital_signal_append(DigitalSignal* signal_a, DigitalSignal* signal_b) {
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|     furi_assert(signal_a);
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|     furi_assert(signal_b);
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| 
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|     if(signal_a->edges_max_cnt < signal_a->edge_cnt + signal_b->edge_cnt) {
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|         return false;
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|     }
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|     /* in case there are no edges in our target signal, the signal to append makes the rules */
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|     if(!signal_a->edge_cnt) {
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|         signal_a->start_level = signal_b->start_level;
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|     }
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|     bool end_level = signal_a->start_level;
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|     if(signal_a->edge_cnt) {
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|         end_level = signal_a->start_level ^ !(signal_a->edge_cnt % 2);
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|     }
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|     uint8_t start_copy = 0;
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|     if(end_level == signal_b->start_level) {
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|         if(signal_a->edge_cnt) {
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|             signal_a->edge_timings[signal_a->edge_cnt - 1] += signal_b->edge_timings[0];
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|             start_copy += 1;
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|         } else {
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|             signal_a->edge_timings[signal_a->edge_cnt] += signal_b->edge_timings[0];
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|         }
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|     }
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| 
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|     for(size_t i = 0; i < signal_b->edge_cnt - start_copy; i++) {
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|         signal_a->edge_timings[signal_a->edge_cnt + i] = signal_b->edge_timings[start_copy + i];
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|     }
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|     signal_a->edge_cnt += signal_b->edge_cnt - start_copy;
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| 
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|     return true;
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| }
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| 
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| bool digital_signal_get_start_level(DigitalSignal* signal) {
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|     furi_assert(signal);
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| 
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|     return signal->start_level;
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| }
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| 
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| uint32_t digital_signal_get_edges_cnt(DigitalSignal* signal) {
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|     furi_assert(signal);
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| 
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|     return signal->edge_cnt;
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| }
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| 
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| void digital_signal_add(DigitalSignal* signal, uint32_t ticks) {
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|     furi_assert(signal);
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|     furi_assert(signal->edge_cnt < signal->edges_max_cnt);
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| 
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|     signal->edge_timings[signal->edge_cnt++] = ticks;
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| }
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| 
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| void digital_signal_add_pulse(DigitalSignal* signal, uint32_t ticks, bool level) {
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|     furi_assert(signal);
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|     furi_assert(signal->edge_cnt < signal->edges_max_cnt);
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| 
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|     /* virgin signal? add it as the only level */
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|     if(signal->edge_cnt == 0) {
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|         signal->start_level = level;
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|         signal->edge_timings[signal->edge_cnt++] = ticks;
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|     } else {
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|         bool end_level = signal->start_level ^ !(signal->edge_cnt % 2);
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| 
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|         if(level != end_level) {
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|             signal->edge_timings[signal->edge_cnt++] = ticks;
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|         } else {
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|             signal->edge_timings[signal->edge_cnt - 1] += ticks;
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|         }
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|     }
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| }
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| 
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| uint32_t digital_signal_get_edge(DigitalSignal* signal, uint32_t edge_num) {
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|     furi_assert(signal);
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|     furi_assert(edge_num < signal->edge_cnt);
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| 
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|     return signal->edge_timings[edge_num];
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| }
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| 
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| void digital_signal_prepare_arr(DigitalSignal* signal) {
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|     furi_assert(signal);
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| 
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|     DigitalSignalInternals* internals = signal->internals;
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| 
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|     /* set up signal polarities */
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|     if(internals->gpio) {
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|         uint32_t bit_set = internals->gpio->pin;
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|         uint32_t bit_reset = internals->gpio->pin << 16;
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| 
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| #ifdef DEBUG_OUTPUT
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|         bit_set |= DEBUG_OUTPUT.pin;
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|         bit_reset |= DEBUG_OUTPUT.pin << 16;
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| #endif
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| 
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|         if(signal->start_level) {
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|             internals->gpio_buff[0] = bit_set;
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|             internals->gpio_buff[1] = bit_reset;
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|         } else {
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|             internals->gpio_buff[0] = bit_reset;
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|             internals->gpio_buff[1] = bit_set;
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|         }
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|     }
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| 
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|     /* set up edge timings */
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|     internals->reload_reg_entries = 0;
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| 
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|     for(size_t pos = 0; pos < signal->edge_cnt; pos++) {
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|         uint32_t pulse_duration = signal->edge_timings[pos] + internals->reload_reg_remainder;
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|         if(pulse_duration < 10 || pulse_duration > 10000000) {
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|             FURI_LOG_D(
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|                 TAG,
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|                 "[prepare] pulse_duration out of range: %lu = %lu * %llu",
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|                 pulse_duration,
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|                 signal->edge_timings[pos],
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|                 internals->factor);
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|             pulse_duration = 100;
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|         }
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|         uint32_t pulse_ticks = (pulse_duration + T_TIM_DIV2) / T_TIM;
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|         internals->reload_reg_remainder = pulse_duration - (pulse_ticks * T_TIM);
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| 
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|         if(pulse_ticks > 1) {
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|             signal->reload_reg_buff[internals->reload_reg_entries++] = pulse_ticks - 1;
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|         }
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|     }
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| }
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| 
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| static void digital_signal_stop_dma() {
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|     LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1);
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|     LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_2);
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|     LL_DMA_ClearFlag_TC1(DMA1);
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|     LL_DMA_ClearFlag_TC2(DMA1);
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| }
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| 
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| static void digital_signal_stop_timer() {
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|     LL_TIM_DisableCounter(TIM2);
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|     LL_TIM_DisableUpdateEvent(TIM2);
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|     LL_TIM_DisableDMAReq_UPDATE(TIM2);
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| 
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|     furi_hal_bus_disable(FuriHalBusTIM2);
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| }
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| 
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| static void digital_signal_setup_timer() {
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|     furi_hal_bus_enable(FuriHalBusTIM2);
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| 
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|     LL_TIM_SetCounterMode(TIM2, LL_TIM_COUNTERMODE_UP);
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|     LL_TIM_SetClockDivision(TIM2, LL_TIM_CLOCKDIVISION_DIV1);
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|     LL_TIM_SetPrescaler(TIM2, 0);
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|     LL_TIM_SetAutoReload(TIM2, 0xFFFFFFFF);
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|     LL_TIM_SetCounter(TIM2, 0);
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| }
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| 
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| static void digital_signal_start_timer() {
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|     LL_TIM_EnableCounter(TIM2);
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|     LL_TIM_EnableUpdateEvent(TIM2);
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|     LL_TIM_EnableDMAReq_UPDATE(TIM2);
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|     LL_TIM_GenerateEvent_UPDATE(TIM2);
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| }
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| 
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| static bool digital_signal_setup_dma(DigitalSignal* signal) {
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|     furi_assert(signal);
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|     DigitalSignalInternals* internals = signal->internals;
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| 
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|     if(!signal->internals->reload_reg_entries) {
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|         return false;
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|     }
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|     digital_signal_stop_dma();
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| 
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|     internals->dma_config_gpio.MemoryOrM2MDstAddress = (uint32_t)internals->gpio_buff;
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|     internals->dma_config_gpio.PeriphOrM2MSrcAddress = (uint32_t) & (internals->gpio->port->BSRR);
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|     internals->dma_config_timer.MemoryOrM2MDstAddress = (uint32_t)signal->reload_reg_buff;
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|     internals->dma_config_timer.NbData = signal->internals->reload_reg_entries;
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| 
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|     /* set up DMA channel 1 and 2 for GPIO and timer copy operations */
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|     LL_DMA_Init(DMA1, LL_DMA_CHANNEL_1, &internals->dma_config_gpio);
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|     LL_DMA_Init(DMA1, LL_DMA_CHANNEL_2, &internals->dma_config_timer);
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| 
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|     /* enable both DMA channels */
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|     LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
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|     LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
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| 
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|     return true;
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| }
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| 
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| void digital_signal_send(DigitalSignal* signal, const GpioPin* gpio) {
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|     furi_assert(signal);
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| 
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|     if(!signal->edge_cnt) {
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|         return;
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|     }
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| 
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|     /* Configure gpio as output */
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|     signal->internals->gpio = gpio;
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|     furi_hal_gpio_init(
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|         signal->internals->gpio, GpioModeOutputPushPull, GpioPullNo, GpioSpeedVeryHigh);
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| 
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|     digital_signal_prepare_arr(signal);
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| 
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|     digital_signal_setup_dma(signal);
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|     digital_signal_setup_timer();
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|     digital_signal_start_timer();
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| 
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|     while(!LL_DMA_IsActiveFlag_TC2(DMA1)) {
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|     }
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| 
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|     digital_signal_stop_timer();
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|     digital_signal_stop_dma();
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| }
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| 
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| static void digital_sequence_alloc_signals(DigitalSequence* sequence, uint32_t size) {
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|     sequence->signals_size = size;
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|     sequence->signals = malloc(sequence->signals_size * sizeof(DigitalSignal*));
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| }
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| 
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| static void digital_sequence_alloc_sequence(DigitalSequence* sequence, uint32_t size) {
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|     sequence->sequence_used = 0;
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|     sequence->sequence_size = size;
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|     sequence->sequence = malloc(sequence->sequence_size);
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|     sequence->send_time = 0;
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|     sequence->send_time_active = false;
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| }
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| 
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| DigitalSequence* digital_sequence_alloc(uint32_t size, const GpioPin* gpio) {
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|     furi_assert(gpio);
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| 
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|     DigitalSequence* sequence = malloc(sizeof(DigitalSequence));
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| 
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|     sequence->gpio = gpio;
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|     sequence->bake = false;
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| 
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|     sequence->dma_buffer = malloc(sizeof(struct ReloadBuffer));
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|     sequence->dma_buffer->size = SEQUENCE_DMA_RINGBUFFER_SIZE;
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|     sequence->dma_buffer->buffer = malloc(sequence->dma_buffer->size * sizeof(uint32_t));
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| 
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|     sequence->dma_config_gpio.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
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|     sequence->dma_config_gpio.Mode = LL_DMA_MODE_CIRCULAR;
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|     sequence->dma_config_gpio.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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|     sequence->dma_config_gpio.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
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|     sequence->dma_config_gpio.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
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|     sequence->dma_config_gpio.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD;
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|     sequence->dma_config_gpio.NbData = 2;
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|     sequence->dma_config_gpio.PeriphRequest = LL_DMAMUX_REQ_TIM2_UP;
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|     sequence->dma_config_gpio.Priority = LL_DMA_PRIORITY_VERYHIGH;
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| 
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|     sequence->dma_config_timer.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
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|     sequence->dma_config_timer.Mode = LL_DMA_MODE_CIRCULAR;
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|     sequence->dma_config_timer.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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|     sequence->dma_config_timer.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
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|     sequence->dma_config_timer.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD;
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|     sequence->dma_config_timer.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD;
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|     sequence->dma_config_timer.PeriphOrM2MSrcAddress = (uint32_t) & (TIM2->ARR);
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|     sequence->dma_config_timer.MemoryOrM2MDstAddress = (uint32_t)sequence->dma_buffer->buffer;
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|     sequence->dma_config_timer.NbData = sequence->dma_buffer->size;
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|     sequence->dma_config_timer.PeriphRequest = LL_DMAMUX_REQ_TIM2_UP;
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|     sequence->dma_config_timer.Priority = LL_DMA_PRIORITY_HIGH;
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| 
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|     digital_sequence_alloc_signals(sequence, SEQUENCE_SIGNALS_SIZE);
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|     digital_sequence_alloc_sequence(sequence, size);
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| 
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|     return sequence;
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| }
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| 
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| void digital_sequence_free(DigitalSequence* sequence) {
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|     furi_assert(sequence);
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| 
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|     free(sequence->signals);
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|     free(sequence->sequence);
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|     free(sequence->dma_buffer->buffer);
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|     free(sequence->dma_buffer);
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|     free(sequence);
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| }
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| 
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| void digital_sequence_set_signal(
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|     DigitalSequence* sequence,
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|     uint8_t signal_index,
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|     DigitalSignal* signal) {
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|     furi_assert(sequence);
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|     furi_assert(signal);
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|     furi_assert(signal_index < sequence->signals_size);
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| 
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|     sequence->signals[signal_index] = signal;
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|     signal->internals->gpio = sequence->gpio;
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|     signal->internals->reload_reg_remainder = 0;
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| 
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|     digital_signal_prepare_arr(signal);
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| }
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| 
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| void digital_sequence_set_sendtime(DigitalSequence* sequence, uint32_t send_time) {
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|     furi_assert(sequence);
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| 
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|     sequence->send_time = send_time;
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|     sequence->send_time_active = true;
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| }
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| 
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| void digital_sequence_add(DigitalSequence* sequence, uint8_t signal_index) {
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|     furi_assert(sequence);
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|     furi_assert(signal_index < sequence->signals_size);
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| 
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|     if(sequence->sequence_used >= sequence->sequence_size) {
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|         sequence->sequence_size += SEQUENCE_SIZE_REALLOCATE_INCREMENT;
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|         sequence->sequence = realloc(sequence->sequence, sequence->sequence_size); //-V701
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|         furi_assert(sequence->sequence);
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|     }
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| 
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|     sequence->sequence[sequence->sequence_used++] = signal_index;
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| }
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| 
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| static bool digital_sequence_setup_dma(DigitalSequence* sequence) {
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|     furi_assert(sequence);
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| 
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|     digital_signal_stop_dma();
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| 
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|     sequence->dma_config_gpio.MemoryOrM2MDstAddress = (uint32_t)sequence->gpio_buff;
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|     sequence->dma_config_gpio.PeriphOrM2MSrcAddress = (uint32_t) & (sequence->gpio->port->BSRR);
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| 
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|     /* set up DMA channel 1 and 2 for GPIO and timer copy operations */
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|     LL_DMA_Init(DMA1, LL_DMA_CHANNEL_1, &sequence->dma_config_gpio);
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|     LL_DMA_Init(DMA1, LL_DMA_CHANNEL_2, &sequence->dma_config_timer);
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| 
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|     /* enable both DMA channels */
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|     LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
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|     LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
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| 
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|     return true;
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| }
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| 
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| static DigitalSignal* digital_sequence_bake(DigitalSequence* sequence) {
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|     furi_assert(sequence);
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| 
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|     uint32_t edges = 0;
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| 
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|     for(uint32_t pos = 0; pos < sequence->sequence_used; pos++) {
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|         uint8_t signal_index = sequence->sequence[pos];
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|         DigitalSignal* sig = sequence->signals[signal_index];
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| 
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|         edges += sig->edge_cnt;
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|     }
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| 
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|     DigitalSignal* ret = digital_signal_alloc(edges);
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| 
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|     for(uint32_t pos = 0; pos < sequence->sequence_used; pos++) {
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|         uint8_t signal_index = sequence->sequence[pos];
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|         DigitalSignal* sig = sequence->signals[signal_index];
 | |
| 
 | |
|         digital_signal_append(ret, sig);
 | |
|     }
 | |
| 
 | |
|     return ret;
 | |
| }
 | |
| 
 | |
| static void digital_sequence_update_pos(DigitalSequence* sequence) {
 | |
|     struct ReloadBuffer* dma_buffer = sequence->dma_buffer;
 | |
| 
 | |
|     dma_buffer->read_pos = dma_buffer->size - LL_DMA_GetDataLength(DMA1, LL_DMA_CHANNEL_2);
 | |
| }
 | |
| 
 | |
| static const uint32_t wait_ms = 10;
 | |
| static const uint32_t wait_ticks = wait_ms * 1000 * 64;
 | |
| 
 | |
| static void digital_sequence_finish(DigitalSequence* sequence) {
 | |
|     struct ReloadBuffer* dma_buffer = sequence->dma_buffer;
 | |
| 
 | |
|     if(dma_buffer->dma_active) {
 | |
|         uint32_t prev_timer = DWT->CYCCNT;
 | |
|         uint32_t end_pos = (dma_buffer->write_pos + 1) % dma_buffer->size;
 | |
|         do {
 | |
|             uint32_t last_pos = dma_buffer->read_pos;
 | |
| 
 | |
|             digital_sequence_update_pos(sequence);
 | |
| 
 | |
|             /* we are finished, when the DMA transferred the 0xFFFFFFFF-timer which is the current write_pos */
 | |
|             if(dma_buffer->read_pos == end_pos) {
 | |
|                 break;
 | |
|             }
 | |
| 
 | |
|             if(last_pos != dma_buffer->read_pos) { //-V547
 | |
|                 prev_timer = DWT->CYCCNT;
 | |
|             }
 | |
|             if(DWT->CYCCNT - prev_timer > wait_ticks) {
 | |
|                 FURI_LOG_D(
 | |
|                     TAG,
 | |
|                     "[SEQ] hung %lu ms in finish (ARR 0x%08lx, read %lu, write %lu)",
 | |
|                     wait_ms,
 | |
|                     TIM2->ARR,
 | |
|                     dma_buffer->read_pos,
 | |
|                     dma_buffer->write_pos);
 | |
|                 break;
 | |
|             }
 | |
|         } while(1);
 | |
|     }
 | |
| 
 | |
|     digital_signal_stop_timer();
 | |
|     digital_signal_stop_dma();
 | |
| }
 | |
| 
 | |
| static void digital_sequence_queue_pulse(DigitalSequence* sequence, uint32_t length) {
 | |
|     struct ReloadBuffer* dma_buffer = sequence->dma_buffer;
 | |
| 
 | |
|     if(dma_buffer->dma_active) {
 | |
|         uint32_t prev_timer = DWT->CYCCNT;
 | |
|         uint32_t end_pos = (dma_buffer->write_pos + 1) % dma_buffer->size;
 | |
|         do {
 | |
|             uint32_t last_pos = dma_buffer->read_pos;
 | |
|             digital_sequence_update_pos(sequence);
 | |
| 
 | |
|             if(dma_buffer->read_pos != end_pos) {
 | |
|                 break;
 | |
|             }
 | |
| 
 | |
|             if(last_pos != dma_buffer->read_pos) { //-V547
 | |
|                 prev_timer = DWT->CYCCNT;
 | |
|             }
 | |
|             if(DWT->CYCCNT - prev_timer > wait_ticks) {
 | |
|                 FURI_LOG_D(
 | |
|                     TAG,
 | |
|                     "[SEQ] hung %lu ms in queue (ARR 0x%08lx, read %lu, write %lu)",
 | |
|                     wait_ms,
 | |
|                     TIM2->ARR,
 | |
|                     dma_buffer->read_pos,
 | |
|                     dma_buffer->write_pos);
 | |
|                 break;
 | |
|             }
 | |
|         } while(1);
 | |
|     }
 | |
| 
 | |
|     dma_buffer->buffer[dma_buffer->write_pos] = length;
 | |
|     dma_buffer->write_pos = (dma_buffer->write_pos + 1) % dma_buffer->size;
 | |
|     dma_buffer->buffer[dma_buffer->write_pos] = 0xFFFFFFFF;
 | |
| }
 | |
| 
 | |
| bool digital_sequence_send(DigitalSequence* sequence) {
 | |
|     furi_assert(sequence);
 | |
| 
 | |
|     struct ReloadBuffer* dma_buffer = sequence->dma_buffer;
 | |
| 
 | |
|     furi_hal_gpio_init(sequence->gpio, GpioModeOutputPushPull, GpioPullNo, GpioSpeedVeryHigh);
 | |
| #ifdef DEBUG_OUTPUT
 | |
|     furi_hal_gpio_init(&DEBUG_OUTPUT, GpioModeOutputPushPull, GpioPullNo, GpioSpeedVeryHigh);
 | |
| #endif
 | |
| 
 | |
|     if(sequence->bake) {
 | |
|         DigitalSignal* sig = digital_sequence_bake(sequence);
 | |
| 
 | |
|         digital_signal_send(sig, sequence->gpio);
 | |
|         digital_signal_free(sig);
 | |
|         return true;
 | |
|     }
 | |
| 
 | |
|     int32_t remainder = 0;
 | |
|     bool traded_first = false;
 | |
| 
 | |
|     FURI_CRITICAL_ENTER();
 | |
| 
 | |
|     dma_buffer->dma_active = false;
 | |
|     dma_buffer->buffer[0] = 0xFFFFFFFF;
 | |
|     dma_buffer->read_pos = 0;
 | |
|     dma_buffer->write_pos = 0;
 | |
| 
 | |
|     for(uint32_t seq_pos = 0; seq_pos < sequence->sequence_used; seq_pos++) {
 | |
|         uint8_t signal_index = sequence->sequence[seq_pos];
 | |
|         DigitalSignal* sig = sequence->signals[signal_index];
 | |
|         bool last_signal = ((seq_pos + 1) == sequence->sequence_used);
 | |
| 
 | |
|         /* all signals are prepared and we can re-use the GPIO buffer from the fist signal */
 | |
|         if(seq_pos == 0) {
 | |
|             sequence->gpio_buff = sig->internals->gpio_buff;
 | |
|         }
 | |
| 
 | |
|         for(uint32_t pulse_pos = 0; pulse_pos < sig->internals->reload_reg_entries; pulse_pos++) {
 | |
|             if(traded_first) {
 | |
|                 traded_first = false;
 | |
|                 continue;
 | |
|             }
 | |
|             uint32_t pulse_length = 0;
 | |
|             bool last_pulse = ((pulse_pos + 1) == sig->internals->reload_reg_entries);
 | |
| 
 | |
|             pulse_length = sig->reload_reg_buff[pulse_pos];
 | |
| 
 | |
|             /* when we are too late more than half a tick, make the first edge temporarily longer */
 | |
|             if(remainder >= T_TIM_DIV2) {
 | |
|                 remainder -= T_TIM;
 | |
|                 pulse_length += 1;
 | |
|             }
 | |
|             remainder += sig->internals->reload_reg_remainder;
 | |
| 
 | |
|             /* last pulse in that signal and have a next signal? */
 | |
|             if(last_pulse) {
 | |
|                 if((seq_pos + 1) < sequence->sequence_used) {
 | |
|                     DigitalSignal* sig_next = sequence->signals[sequence->sequence[seq_pos + 1]];
 | |
| 
 | |
|                     /* when a signal ends with the same level as the next signal begins, let the fist signal generate the whole pulse */
 | |
|                     /* beware, we do not want the level after the last edge, but the last level before that edge */
 | |
|                     bool end_level = sig->start_level ^ ((sig->edge_cnt % 2) == 0);
 | |
| 
 | |
|                     /* take from the next, add it to the current if they have the same level */
 | |
|                     if(end_level == sig_next->start_level) {
 | |
|                         pulse_length += sig_next->reload_reg_buff[0];
 | |
|                         traded_first = true;
 | |
|                     }
 | |
|                 }
 | |
|             }
 | |
| 
 | |
|             digital_sequence_queue_pulse(sequence, pulse_length);
 | |
| 
 | |
|             /* start transmission when buffer was filled enough */
 | |
|             bool start_send = sequence->dma_buffer->write_pos >= (sequence->dma_buffer->size - 4);
 | |
| 
 | |
|             /* or it was the last pulse */
 | |
|             if(last_pulse && last_signal) {
 | |
|                 start_send = true;
 | |
|             }
 | |
| 
 | |
|             /* start transmission */
 | |
|             if(start_send && !dma_buffer->dma_active) {
 | |
|                 digital_sequence_setup_dma(sequence);
 | |
|                 digital_signal_setup_timer();
 | |
| 
 | |
|                 /* if the send time is specified, wait till the core timer passed beyond that time */
 | |
|                 if(sequence->send_time_active) {
 | |
|                     sequence->send_time_active = false;
 | |
|                     while(sequence->send_time - DWT->CYCCNT < 0x80000000) {
 | |
|                     }
 | |
|                 }
 | |
|                 digital_signal_start_timer();
 | |
|                 dma_buffer->dma_active = true;
 | |
|             }
 | |
|         }
 | |
|     }
 | |
| 
 | |
|     /* wait until last dma transaction was finished */
 | |
|     digital_sequence_finish(sequence);
 | |
|     FURI_CRITICAL_EXIT();
 | |
| 
 | |
|     return true;
 | |
| }
 | |
| 
 | |
| void digital_sequence_clear(DigitalSequence* sequence) {
 | |
|     furi_assert(sequence);
 | |
| 
 | |
|     sequence->sequence_used = 0;
 | |
| }
 | |
| 
 | |
| void digital_sequence_timebase_correction(DigitalSequence* sequence, float factor) {
 | |
|     for(uint32_t sig_pos = 0; sig_pos < sequence->signals_size; sig_pos++) {
 | |
|         DigitalSignal* signal = sequence->signals[sig_pos];
 | |
| 
 | |
|         if(signal) {
 | |
|             signal->internals->factor = (uint32_t)(1024 * 1024 * factor);
 | |
|             digital_signal_prepare_arr(signal);
 | |
|         }
 | |
|     }
 | |
| }
 |